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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'a'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6 7; It should fail to compile without fp64.8; RUN: not llc -mtriple=mips-elf -mattr=+msa < %s 2>&1 | \9; RUN: FileCheck -check-prefix=FP32ERROR %s10; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode).11 12@llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1613@llvm_mips_add_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1614@llvm_mips_add_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1615 16define void @llvm_mips_add_a_b_test() nounwind {17entry:18 %0 = load <16 x i8>, ptr @llvm_mips_add_a_b_ARG119 %1 = load <16 x i8>, ptr @llvm_mips_add_a_b_ARG220 %2 = tail call <16 x i8> @llvm.mips.add.a.b(<16 x i8> %0, <16 x i8> %1)21 store <16 x i8> %2, ptr @llvm_mips_add_a_b_RES22 ret void23}24 25declare <16 x i8> @llvm.mips.add.a.b(<16 x i8>, <16 x i8>) nounwind26 27; CHECK: llvm_mips_add_a_b_test:28; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_b_ARG1)29; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_b_ARG2)30; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])31; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])32; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]33; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_b_RES)34; CHECK-DAG: st.b [[WD]], 0([[R3]])35; CHECK: .size llvm_mips_add_a_b_test36;37@llvm_mips_add_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1638@llvm_mips_add_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1639@llvm_mips_add_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1640 41define void @llvm_mips_add_a_h_test() nounwind {42entry:43 %0 = load <8 x i16>, ptr @llvm_mips_add_a_h_ARG144 %1 = load <8 x i16>, ptr @llvm_mips_add_a_h_ARG245 %2 = tail call <8 x i16> @llvm.mips.add.a.h(<8 x i16> %0, <8 x i16> %1)46 store <8 x i16> %2, ptr @llvm_mips_add_a_h_RES47 ret void48}49 50declare <8 x i16> @llvm.mips.add.a.h(<8 x i16>, <8 x i16>) nounwind51 52; CHECK: llvm_mips_add_a_h_test:53; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_h_ARG1)54; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_h_ARG2)55; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])56; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])57; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]58; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_h_RES)59; CHECK-DAG: st.h [[WD]], 0([[R3]])60; CHECK: .size llvm_mips_add_a_h_test61;62@llvm_mips_add_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1663@llvm_mips_add_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1664@llvm_mips_add_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1665 66define void @llvm_mips_add_a_w_test() nounwind {67entry:68 %0 = load <4 x i32>, ptr @llvm_mips_add_a_w_ARG169 %1 = load <4 x i32>, ptr @llvm_mips_add_a_w_ARG270 %2 = tail call <4 x i32> @llvm.mips.add.a.w(<4 x i32> %0, <4 x i32> %1)71 store <4 x i32> %2, ptr @llvm_mips_add_a_w_RES72 ret void73}74 75declare <4 x i32> @llvm.mips.add.a.w(<4 x i32>, <4 x i32>) nounwind76 77; CHECK: llvm_mips_add_a_w_test:78; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_w_ARG1)79; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_w_ARG2)80; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])81; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])82; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]83; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_w_RES)84; CHECK-DAG: st.w [[WD]], 0([[R3]])85; CHECK: .size llvm_mips_add_a_w_test86;87@llvm_mips_add_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1688@llvm_mips_add_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1689@llvm_mips_add_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 1690 91define void @llvm_mips_add_a_d_test() nounwind {92entry:93 %0 = load <2 x i64>, ptr @llvm_mips_add_a_d_ARG194 %1 = load <2 x i64>, ptr @llvm_mips_add_a_d_ARG295 %2 = tail call <2 x i64> @llvm.mips.add.a.d(<2 x i64> %0, <2 x i64> %1)96 store <2 x i64> %2, ptr @llvm_mips_add_a_d_RES97 ret void98}99 100declare <2 x i64> @llvm.mips.add.a.d(<2 x i64>, <2 x i64>) nounwind101 102; CHECK: llvm_mips_add_a_d_test:103; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_d_ARG1)104; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_d_ARG2)105; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])106; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])107; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]108; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_d_RES)109; CHECK-DAG: st.d [[WD]], 0([[R3]])110; CHECK: .size llvm_mips_add_a_d_test111;112@llvm_mips_adds_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16113@llvm_mips_adds_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16114@llvm_mips_adds_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16115 116define void @llvm_mips_adds_a_b_test() nounwind {117entry:118 %0 = load <16 x i8>, ptr @llvm_mips_adds_a_b_ARG1119 %1 = load <16 x i8>, ptr @llvm_mips_adds_a_b_ARG2120 %2 = tail call <16 x i8> @llvm.mips.adds.a.b(<16 x i8> %0, <16 x i8> %1)121 store <16 x i8> %2, ptr @llvm_mips_adds_a_b_RES122 ret void123}124 125declare <16 x i8> @llvm.mips.adds.a.b(<16 x i8>, <16 x i8>) nounwind126 127; CHECK: llvm_mips_adds_a_b_test:128; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_b_ARG1)129; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_b_ARG2)130; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])131; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])132; CHECK-DAG: adds_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]133; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_b_RES)134; CHECK-DAG: st.b [[WD]], 0([[R3]])135; CHECK: .size llvm_mips_adds_a_b_test136;137@llvm_mips_adds_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16138@llvm_mips_adds_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16139@llvm_mips_adds_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16140 141define void @llvm_mips_adds_a_h_test() nounwind {142entry:143 %0 = load <8 x i16>, ptr @llvm_mips_adds_a_h_ARG1144 %1 = load <8 x i16>, ptr @llvm_mips_adds_a_h_ARG2145 %2 = tail call <8 x i16> @llvm.mips.adds.a.h(<8 x i16> %0, <8 x i16> %1)146 store <8 x i16> %2, ptr @llvm_mips_adds_a_h_RES147 ret void148}149 150declare <8 x i16> @llvm.mips.adds.a.h(<8 x i16>, <8 x i16>) nounwind151 152; CHECK: llvm_mips_adds_a_h_test:153; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_h_ARG1)154; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_h_ARG2)155; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])156; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])157; CHECK-DAG: adds_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]158; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_h_RES)159; CHECK-DAG: st.h [[WD]], 0([[R3]])160; CHECK: .size llvm_mips_adds_a_h_test161;162@llvm_mips_adds_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16163@llvm_mips_adds_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16164@llvm_mips_adds_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16165 166define void @llvm_mips_adds_a_w_test() nounwind {167entry:168 %0 = load <4 x i32>, ptr @llvm_mips_adds_a_w_ARG1169 %1 = load <4 x i32>, ptr @llvm_mips_adds_a_w_ARG2170 %2 = tail call <4 x i32> @llvm.mips.adds.a.w(<4 x i32> %0, <4 x i32> %1)171 store <4 x i32> %2, ptr @llvm_mips_adds_a_w_RES172 ret void173}174 175declare <4 x i32> @llvm.mips.adds.a.w(<4 x i32>, <4 x i32>) nounwind176 177; CHECK: llvm_mips_adds_a_w_test:178; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_w_ARG1)179; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_w_ARG2)180; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])181; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])182; CHECK-DAG: adds_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]183; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_w_RES)184; CHECK-DAG: st.w [[WD]], 0([[R3]])185; CHECK: .size llvm_mips_adds_a_w_test186;187@llvm_mips_adds_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16188@llvm_mips_adds_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16189@llvm_mips_adds_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16190 191define void @llvm_mips_adds_a_d_test() nounwind {192entry:193 %0 = load <2 x i64>, ptr @llvm_mips_adds_a_d_ARG1194 %1 = load <2 x i64>, ptr @llvm_mips_adds_a_d_ARG2195 %2 = tail call <2 x i64> @llvm.mips.adds.a.d(<2 x i64> %0, <2 x i64> %1)196 store <2 x i64> %2, ptr @llvm_mips_adds_a_d_RES197 ret void198}199 200declare <2 x i64> @llvm.mips.adds.a.d(<2 x i64>, <2 x i64>) nounwind201 202; CHECK: llvm_mips_adds_a_d_test:203; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_d_ARG1)204; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_d_ARG2)205; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])206; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])207; CHECK-DAG: adds_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]208; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_d_RES)209; CHECK-DAG: st.d [[WD]], 0([[R3]])210; CHECK: .size llvm_mips_adds_a_d_test211;212@llvm_mips_adds_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16213@llvm_mips_adds_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16214@llvm_mips_adds_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16215 216define void @llvm_mips_adds_s_b_test() nounwind {217entry:218 %0 = load <16 x i8>, ptr @llvm_mips_adds_s_b_ARG1219 %1 = load <16 x i8>, ptr @llvm_mips_adds_s_b_ARG2220 %2 = tail call <16 x i8> @llvm.mips.adds.s.b(<16 x i8> %0, <16 x i8> %1)221 store <16 x i8> %2, ptr @llvm_mips_adds_s_b_RES222 ret void223}224 225declare <16 x i8> @llvm.mips.adds.s.b(<16 x i8>, <16 x i8>) nounwind226 227; CHECK: llvm_mips_adds_s_b_test:228; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_b_ARG1)229; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_b_ARG2)230; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])231; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])232; CHECK-DAG: adds_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]233; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_b_RES)234; CHECK-DAG: st.b [[WD]], 0([[R3]])235; CHECK: .size llvm_mips_adds_s_b_test236;237@llvm_mips_adds_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16238@llvm_mips_adds_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16239@llvm_mips_adds_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16240 241define void @llvm_mips_adds_s_h_test() nounwind {242entry:243 %0 = load <8 x i16>, ptr @llvm_mips_adds_s_h_ARG1244 %1 = load <8 x i16>, ptr @llvm_mips_adds_s_h_ARG2245 %2 = tail call <8 x i16> @llvm.mips.adds.s.h(<8 x i16> %0, <8 x i16> %1)246 store <8 x i16> %2, ptr @llvm_mips_adds_s_h_RES247 ret void248}249 250declare <8 x i16> @llvm.mips.adds.s.h(<8 x i16>, <8 x i16>) nounwind251 252; CHECK: llvm_mips_adds_s_h_test:253; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_h_ARG1)254; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_h_ARG2)255; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])256; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])257; CHECK-DAG: adds_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]258; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_h_RES)259; CHECK-DAG: st.h [[WD]], 0([[R3]])260; CHECK: .size llvm_mips_adds_s_h_test261;262@llvm_mips_adds_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16263@llvm_mips_adds_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16264@llvm_mips_adds_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16265 266define void @llvm_mips_adds_s_w_test() nounwind {267entry:268 %0 = load <4 x i32>, ptr @llvm_mips_adds_s_w_ARG1269 %1 = load <4 x i32>, ptr @llvm_mips_adds_s_w_ARG2270 %2 = tail call <4 x i32> @llvm.mips.adds.s.w(<4 x i32> %0, <4 x i32> %1)271 store <4 x i32> %2, ptr @llvm_mips_adds_s_w_RES272 ret void273}274 275declare <4 x i32> @llvm.mips.adds.s.w(<4 x i32>, <4 x i32>) nounwind276 277; CHECK: llvm_mips_adds_s_w_test:278; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_w_ARG1)279; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_w_ARG2)280; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])281; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])282; CHECK-DAG: adds_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]283; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_w_RES)284; CHECK-DAG: st.w [[WD]], 0([[R3]])285; CHECK: .size llvm_mips_adds_s_w_test286;287@llvm_mips_adds_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16288@llvm_mips_adds_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16289@llvm_mips_adds_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16290 291define void @llvm_mips_adds_s_d_test() nounwind {292entry:293 %0 = load <2 x i64>, ptr @llvm_mips_adds_s_d_ARG1294 %1 = load <2 x i64>, ptr @llvm_mips_adds_s_d_ARG2295 %2 = tail call <2 x i64> @llvm.mips.adds.s.d(<2 x i64> %0, <2 x i64> %1)296 store <2 x i64> %2, ptr @llvm_mips_adds_s_d_RES297 ret void298}299 300declare <2 x i64> @llvm.mips.adds.s.d(<2 x i64>, <2 x i64>) nounwind301 302; CHECK: llvm_mips_adds_s_d_test:303; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_d_ARG1)304; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_d_ARG2)305; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])306; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])307; CHECK-DAG: adds_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]308; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_d_RES)309; CHECK-DAG: st.d [[WD]], 0([[R3]])310; CHECK: .size llvm_mips_adds_s_d_test311;312@llvm_mips_adds_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16313@llvm_mips_adds_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16314@llvm_mips_adds_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16315 316define void @llvm_mips_adds_u_b_test() nounwind {317entry:318 %0 = load <16 x i8>, ptr @llvm_mips_adds_u_b_ARG1319 %1 = load <16 x i8>, ptr @llvm_mips_adds_u_b_ARG2320 %2 = tail call <16 x i8> @llvm.mips.adds.u.b(<16 x i8> %0, <16 x i8> %1)321 store <16 x i8> %2, ptr @llvm_mips_adds_u_b_RES322 ret void323}324 325declare <16 x i8> @llvm.mips.adds.u.b(<16 x i8>, <16 x i8>) nounwind326 327; CHECK: llvm_mips_adds_u_b_test:328; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_b_ARG1)329; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_b_ARG2)330; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])331; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])332; CHECK-DAG: adds_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]333; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_b_RES)334; CHECK-DAG: st.b [[WD]], 0([[R3]])335; CHECK: .size llvm_mips_adds_u_b_test336;337@llvm_mips_adds_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16338@llvm_mips_adds_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16339@llvm_mips_adds_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16340 341define void @llvm_mips_adds_u_h_test() nounwind {342entry:343 %0 = load <8 x i16>, ptr @llvm_mips_adds_u_h_ARG1344 %1 = load <8 x i16>, ptr @llvm_mips_adds_u_h_ARG2345 %2 = tail call <8 x i16> @llvm.mips.adds.u.h(<8 x i16> %0, <8 x i16> %1)346 store <8 x i16> %2, ptr @llvm_mips_adds_u_h_RES347 ret void348}349 350declare <8 x i16> @llvm.mips.adds.u.h(<8 x i16>, <8 x i16>) nounwind351 352; CHECK: llvm_mips_adds_u_h_test:353; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_h_ARG1)354; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_h_ARG2)355; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])356; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])357; CHECK-DAG: adds_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]358; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_h_RES)359; CHECK-DAG: st.h [[WD]], 0([[R3]])360; CHECK: .size llvm_mips_adds_u_h_test361;362@llvm_mips_adds_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16363@llvm_mips_adds_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16364@llvm_mips_adds_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16365 366define void @llvm_mips_adds_u_w_test() nounwind {367entry:368 %0 = load <4 x i32>, ptr @llvm_mips_adds_u_w_ARG1369 %1 = load <4 x i32>, ptr @llvm_mips_adds_u_w_ARG2370 %2 = tail call <4 x i32> @llvm.mips.adds.u.w(<4 x i32> %0, <4 x i32> %1)371 store <4 x i32> %2, ptr @llvm_mips_adds_u_w_RES372 ret void373}374 375declare <4 x i32> @llvm.mips.adds.u.w(<4 x i32>, <4 x i32>) nounwind376 377; CHECK: llvm_mips_adds_u_w_test:378; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_w_ARG1)379; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_w_ARG2)380; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])381; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])382; CHECK-DAG: adds_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]383; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_w_RES)384; CHECK-DAG: st.w [[WD]], 0([[R3]])385; CHECK: .size llvm_mips_adds_u_w_test386;387@llvm_mips_adds_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16388@llvm_mips_adds_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16389@llvm_mips_adds_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16390 391define void @llvm_mips_adds_u_d_test() nounwind {392entry:393 %0 = load <2 x i64>, ptr @llvm_mips_adds_u_d_ARG1394 %1 = load <2 x i64>, ptr @llvm_mips_adds_u_d_ARG2395 %2 = tail call <2 x i64> @llvm.mips.adds.u.d(<2 x i64> %0, <2 x i64> %1)396 store <2 x i64> %2, ptr @llvm_mips_adds_u_d_RES397 ret void398}399 400declare <2 x i64> @llvm.mips.adds.u.d(<2 x i64>, <2 x i64>) nounwind401 402; CHECK: llvm_mips_adds_u_d_test:403; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_d_ARG1)404; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_d_ARG2)405; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])406; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])407; CHECK-DAG: adds_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]408; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_d_RES)409; CHECK-DAG: st.d [[WD]], 0([[R3]])410; CHECK: .size llvm_mips_adds_u_d_test411;412@llvm_mips_addv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16413@llvm_mips_addv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16414@llvm_mips_addv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16415 416define void @llvm_mips_addv_b_test() nounwind {417entry:418 %0 = load <16 x i8>, ptr @llvm_mips_addv_b_ARG1419 %1 = load <16 x i8>, ptr @llvm_mips_addv_b_ARG2420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)421 store <16 x i8> %2, ptr @llvm_mips_addv_b_RES422 ret void423}424 425declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind426 427; CHECK: llvm_mips_addv_b_test:428; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_b_ARG1)429; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_b_ARG2)430; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])431; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])432; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]433; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_b_RES)434; CHECK-DAG: st.b [[WD]], 0([[R3]])435; CHECK: .size llvm_mips_addv_b_test436;437@llvm_mips_addv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16438@llvm_mips_addv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16439@llvm_mips_addv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16440 441define void @llvm_mips_addv_h_test() nounwind {442entry:443 %0 = load <8 x i16>, ptr @llvm_mips_addv_h_ARG1444 %1 = load <8 x i16>, ptr @llvm_mips_addv_h_ARG2445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)446 store <8 x i16> %2, ptr @llvm_mips_addv_h_RES447 ret void448}449 450declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind451 452; CHECK: llvm_mips_addv_h_test:453; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_h_ARG1)454; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_h_ARG2)455; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])456; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])457; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]458; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_h_RES)459; CHECK-DAG: st.h [[WD]], 0([[R3]])460; CHECK: .size llvm_mips_addv_h_test461;462@llvm_mips_addv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16463@llvm_mips_addv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16464@llvm_mips_addv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16465 466define void @llvm_mips_addv_w_test() nounwind {467entry:468 %0 = load <4 x i32>, ptr @llvm_mips_addv_w_ARG1469 %1 = load <4 x i32>, ptr @llvm_mips_addv_w_ARG2470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)471 store <4 x i32> %2, ptr @llvm_mips_addv_w_RES472 ret void473}474 475declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind476 477; CHECK: llvm_mips_addv_w_test:478; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_w_ARG1)479; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_w_ARG2)480; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])481; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])482; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]483; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_w_RES)484; CHECK-DAG: st.w [[WD]], 0([[R3]])485; CHECK: .size llvm_mips_addv_w_test486;487@llvm_mips_addv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16488@llvm_mips_addv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16489@llvm_mips_addv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16490 491define void @llvm_mips_addv_d_test() nounwind {492entry:493 %0 = load <2 x i64>, ptr @llvm_mips_addv_d_ARG1494 %1 = load <2 x i64>, ptr @llvm_mips_addv_d_ARG2495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)496 store <2 x i64> %2, ptr @llvm_mips_addv_d_RES497 ret void498}499 500declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind501 502; CHECK: llvm_mips_addv_d_test:503; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_d_ARG1)504; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_d_ARG2)505; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])506; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])507; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]508; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_d_RES)509; CHECK-DAG: st.d [[WD]], 0([[R3]])510; CHECK: .size llvm_mips_addv_d_test511;512 513define void @addv_b_test() nounwind {514entry:515 %0 = load <16 x i8>, ptr @llvm_mips_addv_b_ARG1516 %1 = load <16 x i8>, ptr @llvm_mips_addv_b_ARG2517 %2 = add <16 x i8> %0, %1518 store <16 x i8> %2, ptr @llvm_mips_addv_b_RES519 ret void520}521 522; CHECK: addv_b_test:523; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_b_ARG1)524; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_b_ARG2)525; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])526; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])527; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]528; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_b_RES)529; CHECK-DAG: st.b [[WD]], 0([[R3]])530; CHECK: .size addv_b_test531;532 533define void @addv_h_test() nounwind {534entry:535 %0 = load <8 x i16>, ptr @llvm_mips_addv_h_ARG1536 %1 = load <8 x i16>, ptr @llvm_mips_addv_h_ARG2537 %2 = add <8 x i16> %0, %1538 store <8 x i16> %2, ptr @llvm_mips_addv_h_RES539 ret void540}541 542; CHECK: addv_h_test:543; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_h_ARG1)544; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_h_ARG2)545; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])546; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])547; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]548; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_h_RES)549; CHECK-DAG: st.h [[WD]], 0([[R3]])550; CHECK: .size addv_h_test551;552 553define void @addv_w_test() nounwind {554entry:555 %0 = load <4 x i32>, ptr @llvm_mips_addv_w_ARG1556 %1 = load <4 x i32>, ptr @llvm_mips_addv_w_ARG2557 %2 = add <4 x i32> %0, %1558 store <4 x i32> %2, ptr @llvm_mips_addv_w_RES559 ret void560}561 562; CHECK: addv_w_test:563; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_w_ARG1)564; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_w_ARG2)565; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])566; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])567; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]568; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_w_RES)569; CHECK-DAG: st.w [[WD]], 0([[R3]])570; CHECK: .size addv_w_test571;572 573define void @addv_d_test() nounwind {574entry:575 %0 = load <2 x i64>, ptr @llvm_mips_addv_d_ARG1576 %1 = load <2 x i64>, ptr @llvm_mips_addv_d_ARG2577 %2 = add <2 x i64> %0, %1578 store <2 x i64> %2, ptr @llvm_mips_addv_d_RES579 ret void580}581 582; CHECK: addv_d_test:583; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_d_ARG1)584; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_d_ARG2)585; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])586; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])587; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]588; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_d_RES)589; CHECK-DAG: st.d [[WD]], 0([[R3]])590; CHECK: .size addv_d_test591;592@llvm_mips_asub_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16593@llvm_mips_asub_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16594@llvm_mips_asub_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16595 596define void @llvm_mips_asub_s_b_test() nounwind {597entry:598 %0 = load <16 x i8>, ptr @llvm_mips_asub_s_b_ARG1599 %1 = load <16 x i8>, ptr @llvm_mips_asub_s_b_ARG2600 %2 = tail call <16 x i8> @llvm.mips.asub.s.b(<16 x i8> %0, <16 x i8> %1)601 store <16 x i8> %2, ptr @llvm_mips_asub_s_b_RES602 ret void603}604 605declare <16 x i8> @llvm.mips.asub.s.b(<16 x i8>, <16 x i8>) nounwind606 607; CHECK: llvm_mips_asub_s_b_test:608; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_b_ARG1)609; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_b_ARG2)610; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])611; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])612; CHECK-DAG: asub_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]613; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_b_RES)614; CHECK-DAG: st.b [[WD]], 0([[R3]])615; CHECK: .size llvm_mips_asub_s_b_test616;617@llvm_mips_asub_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16618@llvm_mips_asub_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16619@llvm_mips_asub_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16620 621define void @llvm_mips_asub_s_h_test() nounwind {622entry:623 %0 = load <8 x i16>, ptr @llvm_mips_asub_s_h_ARG1624 %1 = load <8 x i16>, ptr @llvm_mips_asub_s_h_ARG2625 %2 = tail call <8 x i16> @llvm.mips.asub.s.h(<8 x i16> %0, <8 x i16> %1)626 store <8 x i16> %2, ptr @llvm_mips_asub_s_h_RES627 ret void628}629 630declare <8 x i16> @llvm.mips.asub.s.h(<8 x i16>, <8 x i16>) nounwind631 632; CHECK: llvm_mips_asub_s_h_test:633; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_h_ARG1)634; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_h_ARG2)635; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])636; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])637; CHECK-DAG: asub_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]638; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_h_RES)639; CHECK-DAG: st.h [[WD]], 0([[R3]])640; CHECK: .size llvm_mips_asub_s_h_test641;642@llvm_mips_asub_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16643@llvm_mips_asub_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16644@llvm_mips_asub_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16645 646define void @llvm_mips_asub_s_w_test() nounwind {647entry:648 %0 = load <4 x i32>, ptr @llvm_mips_asub_s_w_ARG1649 %1 = load <4 x i32>, ptr @llvm_mips_asub_s_w_ARG2650 %2 = tail call <4 x i32> @llvm.mips.asub.s.w(<4 x i32> %0, <4 x i32> %1)651 store <4 x i32> %2, ptr @llvm_mips_asub_s_w_RES652 ret void653}654 655declare <4 x i32> @llvm.mips.asub.s.w(<4 x i32>, <4 x i32>) nounwind656 657; CHECK: llvm_mips_asub_s_w_test:658; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_w_ARG1)659; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_w_ARG2)660; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])661; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])662; CHECK-DAG: asub_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]663; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_w_RES)664; CHECK-DAG: st.w [[WD]], 0([[R3]])665; CHECK: .size llvm_mips_asub_s_w_test666;667@llvm_mips_asub_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16668@llvm_mips_asub_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16669@llvm_mips_asub_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16670 671define void @llvm_mips_asub_s_d_test() nounwind {672entry:673 %0 = load <2 x i64>, ptr @llvm_mips_asub_s_d_ARG1674 %1 = load <2 x i64>, ptr @llvm_mips_asub_s_d_ARG2675 %2 = tail call <2 x i64> @llvm.mips.asub.s.d(<2 x i64> %0, <2 x i64> %1)676 store <2 x i64> %2, ptr @llvm_mips_asub_s_d_RES677 ret void678}679 680declare <2 x i64> @llvm.mips.asub.s.d(<2 x i64>, <2 x i64>) nounwind681 682; CHECK: llvm_mips_asub_s_d_test:683; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_d_ARG1)684; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_d_ARG2)685; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])686; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])687; CHECK-DAG: asub_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]688; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_d_RES)689; CHECK-DAG: st.d [[WD]], 0([[R3]])690; CHECK: .size llvm_mips_asub_s_d_test691;692@llvm_mips_asub_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16693@llvm_mips_asub_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16694@llvm_mips_asub_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16695 696define void @llvm_mips_asub_u_b_test() nounwind {697entry:698 %0 = load <16 x i8>, ptr @llvm_mips_asub_u_b_ARG1699 %1 = load <16 x i8>, ptr @llvm_mips_asub_u_b_ARG2700 %2 = tail call <16 x i8> @llvm.mips.asub.u.b(<16 x i8> %0, <16 x i8> %1)701 store <16 x i8> %2, ptr @llvm_mips_asub_u_b_RES702 ret void703}704 705declare <16 x i8> @llvm.mips.asub.u.b(<16 x i8>, <16 x i8>) nounwind706 707; CHECK: llvm_mips_asub_u_b_test:708; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_b_ARG1)709; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_b_ARG2)710; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])711; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])712; CHECK-DAG: asub_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]713; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_b_RES)714; CHECK-DAG: st.b [[WD]], 0([[R3]])715; CHECK: .size llvm_mips_asub_u_b_test716;717@llvm_mips_asub_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16718@llvm_mips_asub_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16719@llvm_mips_asub_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16720 721define void @llvm_mips_asub_u_h_test() nounwind {722entry:723 %0 = load <8 x i16>, ptr @llvm_mips_asub_u_h_ARG1724 %1 = load <8 x i16>, ptr @llvm_mips_asub_u_h_ARG2725 %2 = tail call <8 x i16> @llvm.mips.asub.u.h(<8 x i16> %0, <8 x i16> %1)726 store <8 x i16> %2, ptr @llvm_mips_asub_u_h_RES727 ret void728}729 730declare <8 x i16> @llvm.mips.asub.u.h(<8 x i16>, <8 x i16>) nounwind731 732; CHECK: llvm_mips_asub_u_h_test:733; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_h_ARG1)734; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_h_ARG2)735; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])736; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])737; CHECK-DAG: asub_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]738; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_h_RES)739; CHECK-DAG: st.h [[WD]], 0([[R3]])740; CHECK: .size llvm_mips_asub_u_h_test741;742@llvm_mips_asub_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16743@llvm_mips_asub_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16744@llvm_mips_asub_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16745 746define void @llvm_mips_asub_u_w_test() nounwind {747entry:748 %0 = load <4 x i32>, ptr @llvm_mips_asub_u_w_ARG1749 %1 = load <4 x i32>, ptr @llvm_mips_asub_u_w_ARG2750 %2 = tail call <4 x i32> @llvm.mips.asub.u.w(<4 x i32> %0, <4 x i32> %1)751 store <4 x i32> %2, ptr @llvm_mips_asub_u_w_RES752 ret void753}754 755declare <4 x i32> @llvm.mips.asub.u.w(<4 x i32>, <4 x i32>) nounwind756 757; CHECK: llvm_mips_asub_u_w_test:758; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_w_ARG1)759; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_w_ARG2)760; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])761; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])762; CHECK-DAG: asub_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]763; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_w_RES)764; CHECK-DAG: st.w [[WD]], 0([[R3]])765; CHECK: .size llvm_mips_asub_u_w_test766;767@llvm_mips_asub_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16768@llvm_mips_asub_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16769@llvm_mips_asub_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16770 771define void @llvm_mips_asub_u_d_test() nounwind {772entry:773 %0 = load <2 x i64>, ptr @llvm_mips_asub_u_d_ARG1774 %1 = load <2 x i64>, ptr @llvm_mips_asub_u_d_ARG2775 %2 = tail call <2 x i64> @llvm.mips.asub.u.d(<2 x i64> %0, <2 x i64> %1)776 store <2 x i64> %2, ptr @llvm_mips_asub_u_d_RES777 ret void778}779 780declare <2 x i64> @llvm.mips.asub.u.d(<2 x i64>, <2 x i64>) nounwind781 782; CHECK: llvm_mips_asub_u_d_test:783; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_d_ARG1)784; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_d_ARG2)785; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])786; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])787; CHECK-DAG: asub_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]788; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_d_RES)789; CHECK-DAG: st.d [[WD]], 0([[R3]])790; CHECK: .size llvm_mips_asub_u_d_test791;792@llvm_mips_ave_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16793@llvm_mips_ave_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16794@llvm_mips_ave_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16795 796define void @llvm_mips_ave_s_b_test() nounwind {797entry:798 %0 = load <16 x i8>, ptr @llvm_mips_ave_s_b_ARG1799 %1 = load <16 x i8>, ptr @llvm_mips_ave_s_b_ARG2800 %2 = tail call <16 x i8> @llvm.mips.ave.s.b(<16 x i8> %0, <16 x i8> %1)801 store <16 x i8> %2, ptr @llvm_mips_ave_s_b_RES802 ret void803}804 805declare <16 x i8> @llvm.mips.ave.s.b(<16 x i8>, <16 x i8>) nounwind806 807; CHECK: llvm_mips_ave_s_b_test:808; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_b_ARG1)809; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_b_ARG2)810; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])811; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])812; CHECK-DAG: ave_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]813; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_b_RES)814; CHECK-DAG: st.b [[WD]], 0([[R3]])815; CHECK: .size llvm_mips_ave_s_b_test816;817@llvm_mips_ave_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16818@llvm_mips_ave_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16819@llvm_mips_ave_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16820 821define void @llvm_mips_ave_s_h_test() nounwind {822entry:823 %0 = load <8 x i16>, ptr @llvm_mips_ave_s_h_ARG1824 %1 = load <8 x i16>, ptr @llvm_mips_ave_s_h_ARG2825 %2 = tail call <8 x i16> @llvm.mips.ave.s.h(<8 x i16> %0, <8 x i16> %1)826 store <8 x i16> %2, ptr @llvm_mips_ave_s_h_RES827 ret void828}829 830declare <8 x i16> @llvm.mips.ave.s.h(<8 x i16>, <8 x i16>) nounwind831 832; CHECK: llvm_mips_ave_s_h_test:833; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_h_ARG1)834; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_h_ARG2)835; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])836; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])837; CHECK-DAG: ave_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]838; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_h_RES)839; CHECK-DAG: st.h [[WD]], 0([[R3]])840; CHECK: .size llvm_mips_ave_s_h_test841;842@llvm_mips_ave_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16843@llvm_mips_ave_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16844@llvm_mips_ave_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16845 846define void @llvm_mips_ave_s_w_test() nounwind {847entry:848 %0 = load <4 x i32>, ptr @llvm_mips_ave_s_w_ARG1849 %1 = load <4 x i32>, ptr @llvm_mips_ave_s_w_ARG2850 %2 = tail call <4 x i32> @llvm.mips.ave.s.w(<4 x i32> %0, <4 x i32> %1)851 store <4 x i32> %2, ptr @llvm_mips_ave_s_w_RES852 ret void853}854 855declare <4 x i32> @llvm.mips.ave.s.w(<4 x i32>, <4 x i32>) nounwind856 857; CHECK: llvm_mips_ave_s_w_test:858; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_w_ARG1)859; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_w_ARG2)860; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])861; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])862; CHECK-DAG: ave_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]863; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_w_RES)864; CHECK-DAG: st.w [[WD]], 0([[R3]])865; CHECK: .size llvm_mips_ave_s_w_test866;867@llvm_mips_ave_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16868@llvm_mips_ave_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16869@llvm_mips_ave_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16870 871define void @llvm_mips_ave_s_d_test() nounwind {872entry:873 %0 = load <2 x i64>, ptr @llvm_mips_ave_s_d_ARG1874 %1 = load <2 x i64>, ptr @llvm_mips_ave_s_d_ARG2875 %2 = tail call <2 x i64> @llvm.mips.ave.s.d(<2 x i64> %0, <2 x i64> %1)876 store <2 x i64> %2, ptr @llvm_mips_ave_s_d_RES877 ret void878}879 880declare <2 x i64> @llvm.mips.ave.s.d(<2 x i64>, <2 x i64>) nounwind881 882; CHECK: llvm_mips_ave_s_d_test:883; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_d_ARG1)884; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_d_ARG2)885; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])886; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])887; CHECK-DAG: ave_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]888; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_d_RES)889; CHECK-DAG: st.d [[WD]], 0([[R3]])890; CHECK: .size llvm_mips_ave_s_d_test891;892@llvm_mips_ave_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16893@llvm_mips_ave_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16894@llvm_mips_ave_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16895 896define void @llvm_mips_ave_u_b_test() nounwind {897entry:898 %0 = load <16 x i8>, ptr @llvm_mips_ave_u_b_ARG1899 %1 = load <16 x i8>, ptr @llvm_mips_ave_u_b_ARG2900 %2 = tail call <16 x i8> @llvm.mips.ave.u.b(<16 x i8> %0, <16 x i8> %1)901 store <16 x i8> %2, ptr @llvm_mips_ave_u_b_RES902 ret void903}904 905declare <16 x i8> @llvm.mips.ave.u.b(<16 x i8>, <16 x i8>) nounwind906 907; CHECK: llvm_mips_ave_u_b_test:908; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_b_ARG1)909; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_b_ARG2)910; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])911; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])912; CHECK-DAG: ave_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]913; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_b_RES)914; CHECK-DAG: st.b [[WD]], 0([[R3]])915; CHECK: .size llvm_mips_ave_u_b_test916;917@llvm_mips_ave_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16918@llvm_mips_ave_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16919@llvm_mips_ave_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16920 921define void @llvm_mips_ave_u_h_test() nounwind {922entry:923 %0 = load <8 x i16>, ptr @llvm_mips_ave_u_h_ARG1924 %1 = load <8 x i16>, ptr @llvm_mips_ave_u_h_ARG2925 %2 = tail call <8 x i16> @llvm.mips.ave.u.h(<8 x i16> %0, <8 x i16> %1)926 store <8 x i16> %2, ptr @llvm_mips_ave_u_h_RES927 ret void928}929 930declare <8 x i16> @llvm.mips.ave.u.h(<8 x i16>, <8 x i16>) nounwind931 932; CHECK: llvm_mips_ave_u_h_test:933; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_h_ARG1)934; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_h_ARG2)935; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])936; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])937; CHECK-DAG: ave_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]938; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_h_RES)939; CHECK-DAG: st.h [[WD]], 0([[R3]])940; CHECK: .size llvm_mips_ave_u_h_test941;942@llvm_mips_ave_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16943@llvm_mips_ave_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16944@llvm_mips_ave_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16945 946define void @llvm_mips_ave_u_w_test() nounwind {947entry:948 %0 = load <4 x i32>, ptr @llvm_mips_ave_u_w_ARG1949 %1 = load <4 x i32>, ptr @llvm_mips_ave_u_w_ARG2950 %2 = tail call <4 x i32> @llvm.mips.ave.u.w(<4 x i32> %0, <4 x i32> %1)951 store <4 x i32> %2, ptr @llvm_mips_ave_u_w_RES952 ret void953}954 955declare <4 x i32> @llvm.mips.ave.u.w(<4 x i32>, <4 x i32>) nounwind956 957; CHECK: llvm_mips_ave_u_w_test:958; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_w_ARG1)959; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_w_ARG2)960; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])961; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])962; CHECK-DAG: ave_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]963; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_w_RES)964; CHECK-DAG: st.w [[WD]], 0([[R3]])965; CHECK: .size llvm_mips_ave_u_w_test966;967@llvm_mips_ave_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16968@llvm_mips_ave_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16969@llvm_mips_ave_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16970 971define void @llvm_mips_ave_u_d_test() nounwind {972entry:973 %0 = load <2 x i64>, ptr @llvm_mips_ave_u_d_ARG1974 %1 = load <2 x i64>, ptr @llvm_mips_ave_u_d_ARG2975 %2 = tail call <2 x i64> @llvm.mips.ave.u.d(<2 x i64> %0, <2 x i64> %1)976 store <2 x i64> %2, ptr @llvm_mips_ave_u_d_RES977 ret void978}979 980declare <2 x i64> @llvm.mips.ave.u.d(<2 x i64>, <2 x i64>) nounwind981 982; CHECK: llvm_mips_ave_u_d_test:983; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_d_ARG1)984; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_d_ARG2)985; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])986; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])987; CHECK-DAG: ave_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]988; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_d_RES)989; CHECK-DAG: st.d [[WD]], 0([[R3]])990; CHECK: .size llvm_mips_ave_u_d_test991;992@llvm_mips_aver_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16993@llvm_mips_aver_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16994@llvm_mips_aver_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16995 996define void @llvm_mips_aver_s_b_test() nounwind {997entry:998 %0 = load <16 x i8>, ptr @llvm_mips_aver_s_b_ARG1999 %1 = load <16 x i8>, ptr @llvm_mips_aver_s_b_ARG21000 %2 = tail call <16 x i8> @llvm.mips.aver.s.b(<16 x i8> %0, <16 x i8> %1)1001 store <16 x i8> %2, ptr @llvm_mips_aver_s_b_RES1002 ret void1003}1004 1005declare <16 x i8> @llvm.mips.aver.s.b(<16 x i8>, <16 x i8>) nounwind1006 1007; CHECK: llvm_mips_aver_s_b_test:1008; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_b_ARG1)1009; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_b_ARG2)1010; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1011; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1012; CHECK-DAG: aver_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1013; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_b_RES)1014; CHECK-DAG: st.b [[WD]], 0([[R3]])1015; CHECK: .size llvm_mips_aver_s_b_test1016;1017@llvm_mips_aver_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 161018@llvm_mips_aver_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 161019@llvm_mips_aver_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 161020 1021define void @llvm_mips_aver_s_h_test() nounwind {1022entry:1023 %0 = load <8 x i16>, ptr @llvm_mips_aver_s_h_ARG11024 %1 = load <8 x i16>, ptr @llvm_mips_aver_s_h_ARG21025 %2 = tail call <8 x i16> @llvm.mips.aver.s.h(<8 x i16> %0, <8 x i16> %1)1026 store <8 x i16> %2, ptr @llvm_mips_aver_s_h_RES1027 ret void1028}1029 1030declare <8 x i16> @llvm.mips.aver.s.h(<8 x i16>, <8 x i16>) nounwind1031 1032; CHECK: llvm_mips_aver_s_h_test:1033; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_h_ARG1)1034; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_h_ARG2)1035; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1036; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1037; CHECK-DAG: aver_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1038; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_h_RES)1039; CHECK-DAG: st.h [[WD]], 0([[R3]])1040; CHECK: .size llvm_mips_aver_s_h_test1041;1042@llvm_mips_aver_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 161043@llvm_mips_aver_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 161044@llvm_mips_aver_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 161045 1046define void @llvm_mips_aver_s_w_test() nounwind {1047entry:1048 %0 = load <4 x i32>, ptr @llvm_mips_aver_s_w_ARG11049 %1 = load <4 x i32>, ptr @llvm_mips_aver_s_w_ARG21050 %2 = tail call <4 x i32> @llvm.mips.aver.s.w(<4 x i32> %0, <4 x i32> %1)1051 store <4 x i32> %2, ptr @llvm_mips_aver_s_w_RES1052 ret void1053}1054 1055declare <4 x i32> @llvm.mips.aver.s.w(<4 x i32>, <4 x i32>) nounwind1056 1057; CHECK: llvm_mips_aver_s_w_test:1058; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_w_ARG1)1059; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_w_ARG2)1060; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1061; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1062; CHECK-DAG: aver_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1063; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_w_RES)1064; CHECK-DAG: st.w [[WD]], 0([[R3]])1065; CHECK: .size llvm_mips_aver_s_w_test1066;1067@llvm_mips_aver_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 161068@llvm_mips_aver_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 161069@llvm_mips_aver_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 161070 1071define void @llvm_mips_aver_s_d_test() nounwind {1072entry:1073 %0 = load <2 x i64>, ptr @llvm_mips_aver_s_d_ARG11074 %1 = load <2 x i64>, ptr @llvm_mips_aver_s_d_ARG21075 %2 = tail call <2 x i64> @llvm.mips.aver.s.d(<2 x i64> %0, <2 x i64> %1)1076 store <2 x i64> %2, ptr @llvm_mips_aver_s_d_RES1077 ret void1078}1079 1080declare <2 x i64> @llvm.mips.aver.s.d(<2 x i64>, <2 x i64>) nounwind1081 1082; CHECK: llvm_mips_aver_s_d_test:1083; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_d_ARG1)1084; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_d_ARG2)1085; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1086; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1087; CHECK-DAG: aver_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1088; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_d_RES)1089; CHECK-DAG: st.d [[WD]], 0([[R3]])1090; CHECK: .size llvm_mips_aver_s_d_test1091;1092@llvm_mips_aver_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 161093@llvm_mips_aver_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 161094@llvm_mips_aver_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 161095 1096define void @llvm_mips_aver_u_b_test() nounwind {1097entry:1098 %0 = load <16 x i8>, ptr @llvm_mips_aver_u_b_ARG11099 %1 = load <16 x i8>, ptr @llvm_mips_aver_u_b_ARG21100 %2 = tail call <16 x i8> @llvm.mips.aver.u.b(<16 x i8> %0, <16 x i8> %1)1101 store <16 x i8> %2, ptr @llvm_mips_aver_u_b_RES1102 ret void1103}1104 1105declare <16 x i8> @llvm.mips.aver.u.b(<16 x i8>, <16 x i8>) nounwind1106 1107; CHECK: llvm_mips_aver_u_b_test:1108; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_b_ARG1)1109; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_b_ARG2)1110; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1111; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1112; CHECK-DAG: aver_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1113; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_b_RES)1114; CHECK-DAG: st.b [[WD]], 0([[R3]])1115; CHECK: .size llvm_mips_aver_u_b_test1116;1117@llvm_mips_aver_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 161118@llvm_mips_aver_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 161119@llvm_mips_aver_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 161120 1121define void @llvm_mips_aver_u_h_test() nounwind {1122entry:1123 %0 = load <8 x i16>, ptr @llvm_mips_aver_u_h_ARG11124 %1 = load <8 x i16>, ptr @llvm_mips_aver_u_h_ARG21125 %2 = tail call <8 x i16> @llvm.mips.aver.u.h(<8 x i16> %0, <8 x i16> %1)1126 store <8 x i16> %2, ptr @llvm_mips_aver_u_h_RES1127 ret void1128}1129 1130declare <8 x i16> @llvm.mips.aver.u.h(<8 x i16>, <8 x i16>) nounwind1131 1132; CHECK: llvm_mips_aver_u_h_test:1133; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_h_ARG1)1134; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_h_ARG2)1135; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1136; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1137; CHECK-DAG: aver_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1138; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_h_RES)1139; CHECK-DAG: st.h [[WD]], 0([[R3]])1140; CHECK: .size llvm_mips_aver_u_h_test1141;1142@llvm_mips_aver_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 161143@llvm_mips_aver_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 161144@llvm_mips_aver_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 161145 1146define void @llvm_mips_aver_u_w_test() nounwind {1147entry:1148 %0 = load <4 x i32>, ptr @llvm_mips_aver_u_w_ARG11149 %1 = load <4 x i32>, ptr @llvm_mips_aver_u_w_ARG21150 %2 = tail call <4 x i32> @llvm.mips.aver.u.w(<4 x i32> %0, <4 x i32> %1)1151 store <4 x i32> %2, ptr @llvm_mips_aver_u_w_RES1152 ret void1153}1154 1155declare <4 x i32> @llvm.mips.aver.u.w(<4 x i32>, <4 x i32>) nounwind1156 1157; CHECK: llvm_mips_aver_u_w_test:1158; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_w_ARG1)1159; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_w_ARG2)1160; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1161; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1162; CHECK-DAG: aver_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1163; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_w_RES)1164; CHECK-DAG: st.w [[WD]], 0([[R3]])1165; CHECK: .size llvm_mips_aver_u_w_test1166;1167@llvm_mips_aver_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 161168@llvm_mips_aver_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 161169@llvm_mips_aver_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 161170 1171define void @llvm_mips_aver_u_d_test() nounwind {1172entry:1173 %0 = load <2 x i64>, ptr @llvm_mips_aver_u_d_ARG11174 %1 = load <2 x i64>, ptr @llvm_mips_aver_u_d_ARG21175 %2 = tail call <2 x i64> @llvm.mips.aver.u.d(<2 x i64> %0, <2 x i64> %1)1176 store <2 x i64> %2, ptr @llvm_mips_aver_u_d_RES1177 ret void1178}1179 1180declare <2 x i64> @llvm.mips.aver.u.d(<2 x i64>, <2 x i64>) nounwind1181 1182; CHECK: llvm_mips_aver_u_d_test:1183; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_d_ARG1)1184; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_d_ARG2)1185; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1186; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1187; CHECK-DAG: aver_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1188; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_d_RES)1189; CHECK-DAG: st.d [[WD]], 0([[R3]])1190; CHECK: .size llvm_mips_aver_u_d_test1191;1192