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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'b'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6 7@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_bclr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_bclr_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_bclr_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_bclr_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1)16 store <16 x i8> %2, ptr @llvm_mips_bclr_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind21 22; CHECK: llvm_mips_bclr_b_test:23; CHECK: ld.b24; CHECK: ld.b25; CHECK: bclr.b26; CHECK: st.b27; CHECK: .size llvm_mips_bclr_b_test28;29@llvm_mips_bclr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_bclr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1631@llvm_mips_bclr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1632 33define void @llvm_mips_bclr_h_test() nounwind {34entry:35 %0 = load <8 x i16>, ptr @llvm_mips_bclr_h_ARG136 %1 = load <8 x i16>, ptr @llvm_mips_bclr_h_ARG237 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1)38 store <8 x i16> %2, ptr @llvm_mips_bclr_h_RES39 ret void40}41 42declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind43 44; CHECK: llvm_mips_bclr_h_test:45; CHECK: ld.h46; CHECK: ld.h47; CHECK: bclr.h48; CHECK: st.h49; CHECK: .size llvm_mips_bclr_h_test50;51@llvm_mips_bclr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1652@llvm_mips_bclr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1653@llvm_mips_bclr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_bclr_w_test() nounwind {56entry:57 %0 = load <4 x i32>, ptr @llvm_mips_bclr_w_ARG158 %1 = load <4 x i32>, ptr @llvm_mips_bclr_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1)60 store <4 x i32> %2, ptr @llvm_mips_bclr_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind65 66; CHECK: llvm_mips_bclr_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: bclr.w70; CHECK: st.w71; CHECK: .size llvm_mips_bclr_w_test72;73@llvm_mips_bclr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1674@llvm_mips_bclr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1675@llvm_mips_bclr_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_bclr_d_test() nounwind {78entry:79 %0 = load <2 x i64>, ptr @llvm_mips_bclr_d_ARG180 %1 = load <2 x i64>, ptr @llvm_mips_bclr_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1)82 store <2 x i64> %2, ptr @llvm_mips_bclr_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind87 88; CHECK: llvm_mips_bclr_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: bclr.d92; CHECK: st.d93; CHECK: .size llvm_mips_bclr_d_test94 95@llvm_mips_binsl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1696@llvm_mips_binsl_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1697@llvm_mips_binsl_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1698@llvm_mips_binsl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1699 100define void @llvm_mips_binsl_b_test() nounwind {101entry:102 %0 = load <16 x i8>, ptr @llvm_mips_binsl_b_ARG1103 %1 = load <16 x i8>, ptr @llvm_mips_binsl_b_ARG2104 %2 = load <16 x i8>, ptr @llvm_mips_binsl_b_ARG3105 %3 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)106 store <16 x i8> %3, ptr @llvm_mips_binsl_b_RES107 ret void108}109 110declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind111 112; CHECK: llvm_mips_binsl_b_test:113; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG1)(114; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG2)(115; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG3)(116; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])117; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])118; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])119; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]]120; CHECK-DAG: st.b [[R4]], 0(121; CHECK: .size llvm_mips_binsl_b_test122 123@llvm_mips_binsl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16124@llvm_mips_binsl_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16125@llvm_mips_binsl_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16126@llvm_mips_binsl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16127 128define void @llvm_mips_binsl_h_test() nounwind {129entry:130 %0 = load <8 x i16>, ptr @llvm_mips_binsl_h_ARG1131 %1 = load <8 x i16>, ptr @llvm_mips_binsl_h_ARG2132 %2 = load <8 x i16>, ptr @llvm_mips_binsl_h_ARG3133 %3 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)134 store <8 x i16> %3, ptr @llvm_mips_binsl_h_RES135 ret void136}137 138declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind139 140; CHECK: llvm_mips_binsl_h_test:141; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG1)(142; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG2)(143; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG3)(144; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]])145; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]])146; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]])147; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]]148; CHECK-DAG: st.h [[R4]], 0(149; CHECK: .size llvm_mips_binsl_h_test150 151@llvm_mips_binsl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16152@llvm_mips_binsl_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16153@llvm_mips_binsl_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16154@llvm_mips_binsl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16155 156define void @llvm_mips_binsl_w_test() nounwind {157entry:158 %0 = load <4 x i32>, ptr @llvm_mips_binsl_w_ARG1159 %1 = load <4 x i32>, ptr @llvm_mips_binsl_w_ARG2160 %2 = load <4 x i32>, ptr @llvm_mips_binsl_w_ARG3161 %3 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)162 store <4 x i32> %3, ptr @llvm_mips_binsl_w_RES163 ret void164}165 166declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind167 168; CHECK: llvm_mips_binsl_w_test:169; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG1)(170; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG2)(171; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG3)(172; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]])173; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]])174; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]])175; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]]176; CHECK-DAG: st.w [[R4]], 0(177; CHECK: .size llvm_mips_binsl_w_test178 179@llvm_mips_binsl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16180@llvm_mips_binsl_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16181@llvm_mips_binsl_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16182@llvm_mips_binsl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16183 184define void @llvm_mips_binsl_d_test() nounwind {185entry:186 %0 = load <2 x i64>, ptr @llvm_mips_binsl_d_ARG1187 %1 = load <2 x i64>, ptr @llvm_mips_binsl_d_ARG2188 %2 = load <2 x i64>, ptr @llvm_mips_binsl_d_ARG3189 %3 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)190 store <2 x i64> %3, ptr @llvm_mips_binsl_d_RES191 ret void192}193 194declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind195 196; CHECK: llvm_mips_binsl_d_test:197; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG1)(198; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG2)(199; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG3)(200; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]])201; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]])202; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]])203; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]]204; CHECK-DAG: st.d [[R4]], 0(205; CHECK: .size llvm_mips_binsl_d_test206 207@llvm_mips_binsr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16208@llvm_mips_binsr_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16209@llvm_mips_binsr_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16210@llvm_mips_binsr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16211 212define void @llvm_mips_binsr_b_test() nounwind {213entry:214 %0 = load <16 x i8>, ptr @llvm_mips_binsr_b_ARG1215 %1 = load <16 x i8>, ptr @llvm_mips_binsr_b_ARG2216 %2 = load <16 x i8>, ptr @llvm_mips_binsr_b_ARG3217 %3 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)218 store <16 x i8> %3, ptr @llvm_mips_binsr_b_RES219 ret void220}221 222declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind223 224; CHECK: llvm_mips_binsr_b_test:225; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG1)(226; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG2)(227; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG3)(228; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])229; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])230; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])231; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]]232; CHECK-DAG: st.b [[R4]], 0(233; CHECK: .size llvm_mips_binsr_b_test234 235@llvm_mips_binsr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16236@llvm_mips_binsr_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16237@llvm_mips_binsr_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16238@llvm_mips_binsr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16239 240define void @llvm_mips_binsr_h_test() nounwind {241entry:242 %0 = load <8 x i16>, ptr @llvm_mips_binsr_h_ARG1243 %1 = load <8 x i16>, ptr @llvm_mips_binsr_h_ARG2244 %2 = load <8 x i16>, ptr @llvm_mips_binsr_h_ARG3245 %3 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)246 store <8 x i16> %3, ptr @llvm_mips_binsr_h_RES247 ret void248}249 250declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind251 252; CHECK: llvm_mips_binsr_h_test:253; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG1)(254; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG2)(255; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG3)(256; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]])257; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]])258; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]])259; CHECK-DAG: binsr.h [[R4]], [[R5]], [[R6]]260; CHECK-DAG: st.h [[R4]], 0(261; CHECK: .size llvm_mips_binsr_h_test262 263@llvm_mips_binsr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16264@llvm_mips_binsr_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16265@llvm_mips_binsr_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16266@llvm_mips_binsr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16267 268define void @llvm_mips_binsr_w_test() nounwind {269entry:270 %0 = load <4 x i32>, ptr @llvm_mips_binsr_w_ARG1271 %1 = load <4 x i32>, ptr @llvm_mips_binsr_w_ARG2272 %2 = load <4 x i32>, ptr @llvm_mips_binsr_w_ARG3273 %3 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)274 store <4 x i32> %3, ptr @llvm_mips_binsr_w_RES275 ret void276}277 278declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind279 280; CHECK: llvm_mips_binsr_w_test:281; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG1)(282; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG2)(283; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG3)(284; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]])285; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]])286; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]])287; CHECK-DAG: binsr.w [[R4]], [[R5]], [[R6]]288; CHECK-DAG: st.w [[R4]], 0(289; CHECK: .size llvm_mips_binsr_w_test290 291@llvm_mips_binsr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16292@llvm_mips_binsr_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16293@llvm_mips_binsr_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16294@llvm_mips_binsr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16295 296define void @llvm_mips_binsr_d_test() nounwind {297entry:298 %0 = load <2 x i64>, ptr @llvm_mips_binsr_d_ARG1299 %1 = load <2 x i64>, ptr @llvm_mips_binsr_d_ARG2300 %2 = load <2 x i64>, ptr @llvm_mips_binsr_d_ARG3301 %3 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)302 store <2 x i64> %3, ptr @llvm_mips_binsr_d_RES303 ret void304}305 306declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind307 308; CHECK: llvm_mips_binsr_d_test:309; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG1)(310; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG2)(311; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG3)(312; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]])313; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]])314; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]])315; CHECK-DAG: binsr.d [[R4]], [[R5]], [[R6]]316; CHECK-DAG: st.d [[R4]], 0(317; CHECK: .size llvm_mips_binsr_d_test318 319@llvm_mips_bneg_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16320@llvm_mips_bneg_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16321@llvm_mips_bneg_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16322 323define void @llvm_mips_bneg_b_test() nounwind {324entry:325 %0 = load <16 x i8>, ptr @llvm_mips_bneg_b_ARG1326 %1 = load <16 x i8>, ptr @llvm_mips_bneg_b_ARG2327 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)328 store <16 x i8> %2, ptr @llvm_mips_bneg_b_RES329 ret void330}331 332declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind333 334; CHECK: llvm_mips_bneg_b_test:335; CHECK: ld.b336; CHECK: ld.b337; CHECK: bneg.b338; CHECK: st.b339; CHECK: .size llvm_mips_bneg_b_test340;341@llvm_mips_bneg_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16342@llvm_mips_bneg_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16343@llvm_mips_bneg_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16344 345define void @llvm_mips_bneg_h_test() nounwind {346entry:347 %0 = load <8 x i16>, ptr @llvm_mips_bneg_h_ARG1348 %1 = load <8 x i16>, ptr @llvm_mips_bneg_h_ARG2349 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)350 store <8 x i16> %2, ptr @llvm_mips_bneg_h_RES351 ret void352}353 354declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind355 356; CHECK: llvm_mips_bneg_h_test:357; CHECK: ld.h358; CHECK: ld.h359; CHECK: bneg.h360; CHECK: st.h361; CHECK: .size llvm_mips_bneg_h_test362;363@llvm_mips_bneg_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16364@llvm_mips_bneg_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16365@llvm_mips_bneg_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16366 367define void @llvm_mips_bneg_w_test() nounwind {368entry:369 %0 = load <4 x i32>, ptr @llvm_mips_bneg_w_ARG1370 %1 = load <4 x i32>, ptr @llvm_mips_bneg_w_ARG2371 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)372 store <4 x i32> %2, ptr @llvm_mips_bneg_w_RES373 ret void374}375 376declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind377 378; CHECK: llvm_mips_bneg_w_test:379; CHECK: ld.w380; CHECK: ld.w381; CHECK: bneg.w382; CHECK: st.w383; CHECK: .size llvm_mips_bneg_w_test384;385@llvm_mips_bneg_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16386@llvm_mips_bneg_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16387@llvm_mips_bneg_d_RES = global <2 x i64> <i64 0, i64 0>, align 16388 389define void @llvm_mips_bneg_d_test() nounwind {390entry:391 %0 = load <2 x i64>, ptr @llvm_mips_bneg_d_ARG1392 %1 = load <2 x i64>, ptr @llvm_mips_bneg_d_ARG2393 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)394 store <2 x i64> %2, ptr @llvm_mips_bneg_d_RES395 ret void396}397 398declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind399 400; CHECK: llvm_mips_bneg_d_test:401; CHECK: ld.d402; CHECK: ld.d403; CHECK: bneg.d404; CHECK: st.d405; CHECK: .size llvm_mips_bneg_d_test406;407@llvm_mips_bset_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16408@llvm_mips_bset_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16409@llvm_mips_bset_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16410 411define void @llvm_mips_bset_b_test() nounwind {412entry:413 %0 = load <16 x i8>, ptr @llvm_mips_bset_b_ARG1414 %1 = load <16 x i8>, ptr @llvm_mips_bset_b_ARG2415 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)416 store <16 x i8> %2, ptr @llvm_mips_bset_b_RES417 ret void418}419 420declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind421 422; CHECK: llvm_mips_bset_b_test:423; CHECK: ld.b424; CHECK: ld.b425; CHECK: bset.b426; CHECK: st.b427; CHECK: .size llvm_mips_bset_b_test428;429@llvm_mips_bset_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16430@llvm_mips_bset_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16431@llvm_mips_bset_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16432 433define void @llvm_mips_bset_h_test() nounwind {434entry:435 %0 = load <8 x i16>, ptr @llvm_mips_bset_h_ARG1436 %1 = load <8 x i16>, ptr @llvm_mips_bset_h_ARG2437 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)438 store <8 x i16> %2, ptr @llvm_mips_bset_h_RES439 ret void440}441 442declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind443 444; CHECK: llvm_mips_bset_h_test:445; CHECK: ld.h446; CHECK: ld.h447; CHECK: bset.h448; CHECK: st.h449; CHECK: .size llvm_mips_bset_h_test450;451@llvm_mips_bset_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16452@llvm_mips_bset_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16453@llvm_mips_bset_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16454 455define void @llvm_mips_bset_w_test() nounwind {456entry:457 %0 = load <4 x i32>, ptr @llvm_mips_bset_w_ARG1458 %1 = load <4 x i32>, ptr @llvm_mips_bset_w_ARG2459 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)460 store <4 x i32> %2, ptr @llvm_mips_bset_w_RES461 ret void462}463 464declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind465 466; CHECK: llvm_mips_bset_w_test:467; CHECK: ld.w468; CHECK: ld.w469; CHECK: bset.w470; CHECK: st.w471; CHECK: .size llvm_mips_bset_w_test472;473@llvm_mips_bset_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16474@llvm_mips_bset_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16475@llvm_mips_bset_d_RES = global <2 x i64> <i64 0, i64 0>, align 16476 477define void @llvm_mips_bset_d_test() nounwind {478entry:479 %0 = load <2 x i64>, ptr @llvm_mips_bset_d_ARG1480 %1 = load <2 x i64>, ptr @llvm_mips_bset_d_ARG2481 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)482 store <2 x i64> %2, ptr @llvm_mips_bset_d_RES483 ret void484}485 486declare <2 x i64> @llvm.mips.bset.d(<2 x i64>, <2 x i64>) nounwind487 488; CHECK: llvm_mips_bset_d_test:489; CHECK: ld.d490; CHECK: ld.d491; CHECK: bset.d492; CHECK: st.d493; CHECK: .size llvm_mips_bset_d_test494;495