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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'c'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_ceq_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_ceq_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_ceq_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_ceq_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.ceq.b(<16 x i8> %0, <16 x i8> %1)16 store <16 x i8> %2, ptr @llvm_mips_ceq_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.ceq.b(<16 x i8>, <16 x i8>) nounwind21 22; CHECK: llvm_mips_ceq_b_test:23; CHECK: ld.b24; CHECK: ld.b25; CHECK: ceq.b26; CHECK: st.b27; CHECK: .size llvm_mips_ceq_b_test28;29@llvm_mips_ceq_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_ceq_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1631@llvm_mips_ceq_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1632 33define void @llvm_mips_ceq_h_test() nounwind {34entry:35 %0 = load <8 x i16>, ptr @llvm_mips_ceq_h_ARG136 %1 = load <8 x i16>, ptr @llvm_mips_ceq_h_ARG237 %2 = tail call <8 x i16> @llvm.mips.ceq.h(<8 x i16> %0, <8 x i16> %1)38 store <8 x i16> %2, ptr @llvm_mips_ceq_h_RES39 ret void40}41 42declare <8 x i16> @llvm.mips.ceq.h(<8 x i16>, <8 x i16>) nounwind43 44; CHECK: llvm_mips_ceq_h_test:45; CHECK: ld.h46; CHECK: ld.h47; CHECK: ceq.h48; CHECK: st.h49; CHECK: .size llvm_mips_ceq_h_test50;51@llvm_mips_ceq_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1652@llvm_mips_ceq_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1653@llvm_mips_ceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_ceq_w_test() nounwind {56entry:57 %0 = load <4 x i32>, ptr @llvm_mips_ceq_w_ARG158 %1 = load <4 x i32>, ptr @llvm_mips_ceq_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.ceq.w(<4 x i32> %0, <4 x i32> %1)60 store <4 x i32> %2, ptr @llvm_mips_ceq_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.ceq.w(<4 x i32>, <4 x i32>) nounwind65 66; CHECK: llvm_mips_ceq_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: ceq.w70; CHECK: st.w71; CHECK: .size llvm_mips_ceq_w_test72;73@llvm_mips_ceq_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1674@llvm_mips_ceq_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1675@llvm_mips_ceq_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_ceq_d_test() nounwind {78entry:79 %0 = load <2 x i64>, ptr @llvm_mips_ceq_d_ARG180 %1 = load <2 x i64>, ptr @llvm_mips_ceq_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.ceq.d(<2 x i64> %0, <2 x i64> %1)82 store <2 x i64> %2, ptr @llvm_mips_ceq_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.ceq.d(<2 x i64>, <2 x i64>) nounwind87 88; CHECK: llvm_mips_ceq_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: ceq.d92; CHECK: st.d93; CHECK: .size llvm_mips_ceq_d_test94;95@llvm_mips_cle_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1696@llvm_mips_cle_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1697@llvm_mips_cle_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1698 99define void @llvm_mips_cle_s_b_test() nounwind {100entry:101 %0 = load <16 x i8>, ptr @llvm_mips_cle_s_b_ARG1102 %1 = load <16 x i8>, ptr @llvm_mips_cle_s_b_ARG2103 %2 = tail call <16 x i8> @llvm.mips.cle.s.b(<16 x i8> %0, <16 x i8> %1)104 store <16 x i8> %2, ptr @llvm_mips_cle_s_b_RES105 ret void106}107 108declare <16 x i8> @llvm.mips.cle.s.b(<16 x i8>, <16 x i8>) nounwind109 110; CHECK: llvm_mips_cle_s_b_test:111; CHECK: ld.b112; CHECK: ld.b113; CHECK: cle_s.b114; CHECK: st.b115; CHECK: .size llvm_mips_cle_s_b_test116;117@llvm_mips_cle_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16118@llvm_mips_cle_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16119@llvm_mips_cle_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16120 121define void @llvm_mips_cle_s_h_test() nounwind {122entry:123 %0 = load <8 x i16>, ptr @llvm_mips_cle_s_h_ARG1124 %1 = load <8 x i16>, ptr @llvm_mips_cle_s_h_ARG2125 %2 = tail call <8 x i16> @llvm.mips.cle.s.h(<8 x i16> %0, <8 x i16> %1)126 store <8 x i16> %2, ptr @llvm_mips_cle_s_h_RES127 ret void128}129 130declare <8 x i16> @llvm.mips.cle.s.h(<8 x i16>, <8 x i16>) nounwind131 132; CHECK: llvm_mips_cle_s_h_test:133; CHECK: ld.h134; CHECK: ld.h135; CHECK: cle_s.h136; CHECK: st.h137; CHECK: .size llvm_mips_cle_s_h_test138;139@llvm_mips_cle_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16140@llvm_mips_cle_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16141@llvm_mips_cle_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16142 143define void @llvm_mips_cle_s_w_test() nounwind {144entry:145 %0 = load <4 x i32>, ptr @llvm_mips_cle_s_w_ARG1146 %1 = load <4 x i32>, ptr @llvm_mips_cle_s_w_ARG2147 %2 = tail call <4 x i32> @llvm.mips.cle.s.w(<4 x i32> %0, <4 x i32> %1)148 store <4 x i32> %2, ptr @llvm_mips_cle_s_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.cle.s.w(<4 x i32>, <4 x i32>) nounwind153 154; CHECK: llvm_mips_cle_s_w_test:155; CHECK: ld.w156; CHECK: ld.w157; CHECK: cle_s.w158; CHECK: st.w159; CHECK: .size llvm_mips_cle_s_w_test160;161@llvm_mips_cle_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16162@llvm_mips_cle_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16163@llvm_mips_cle_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16164 165define void @llvm_mips_cle_s_d_test() nounwind {166entry:167 %0 = load <2 x i64>, ptr @llvm_mips_cle_s_d_ARG1168 %1 = load <2 x i64>, ptr @llvm_mips_cle_s_d_ARG2169 %2 = tail call <2 x i64> @llvm.mips.cle.s.d(<2 x i64> %0, <2 x i64> %1)170 store <2 x i64> %2, ptr @llvm_mips_cle_s_d_RES171 ret void172}173 174declare <2 x i64> @llvm.mips.cle.s.d(<2 x i64>, <2 x i64>) nounwind175 176; CHECK: llvm_mips_cle_s_d_test:177; CHECK: ld.d178; CHECK: ld.d179; CHECK: cle_s.d180; CHECK: st.d181; CHECK: .size llvm_mips_cle_s_d_test182;183@llvm_mips_cle_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16184@llvm_mips_cle_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16185@llvm_mips_cle_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16186 187define void @llvm_mips_cle_u_b_test() nounwind {188entry:189 %0 = load <16 x i8>, ptr @llvm_mips_cle_u_b_ARG1190 %1 = load <16 x i8>, ptr @llvm_mips_cle_u_b_ARG2191 %2 = tail call <16 x i8> @llvm.mips.cle.u.b(<16 x i8> %0, <16 x i8> %1)192 store <16 x i8> %2, ptr @llvm_mips_cle_u_b_RES193 ret void194}195 196declare <16 x i8> @llvm.mips.cle.u.b(<16 x i8>, <16 x i8>) nounwind197 198; CHECK: llvm_mips_cle_u_b_test:199; CHECK: ld.b200; CHECK: ld.b201; CHECK: cle_u.b202; CHECK: st.b203; CHECK: .size llvm_mips_cle_u_b_test204;205@llvm_mips_cle_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16206@llvm_mips_cle_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16207@llvm_mips_cle_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16208 209define void @llvm_mips_cle_u_h_test() nounwind {210entry:211 %0 = load <8 x i16>, ptr @llvm_mips_cle_u_h_ARG1212 %1 = load <8 x i16>, ptr @llvm_mips_cle_u_h_ARG2213 %2 = tail call <8 x i16> @llvm.mips.cle.u.h(<8 x i16> %0, <8 x i16> %1)214 store <8 x i16> %2, ptr @llvm_mips_cle_u_h_RES215 ret void216}217 218declare <8 x i16> @llvm.mips.cle.u.h(<8 x i16>, <8 x i16>) nounwind219 220; CHECK: llvm_mips_cle_u_h_test:221; CHECK: ld.h222; CHECK: ld.h223; CHECK: cle_u.h224; CHECK: st.h225; CHECK: .size llvm_mips_cle_u_h_test226;227@llvm_mips_cle_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16228@llvm_mips_cle_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16229@llvm_mips_cle_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16230 231define void @llvm_mips_cle_u_w_test() nounwind {232entry:233 %0 = load <4 x i32>, ptr @llvm_mips_cle_u_w_ARG1234 %1 = load <4 x i32>, ptr @llvm_mips_cle_u_w_ARG2235 %2 = tail call <4 x i32> @llvm.mips.cle.u.w(<4 x i32> %0, <4 x i32> %1)236 store <4 x i32> %2, ptr @llvm_mips_cle_u_w_RES237 ret void238}239 240declare <4 x i32> @llvm.mips.cle.u.w(<4 x i32>, <4 x i32>) nounwind241 242; CHECK: llvm_mips_cle_u_w_test:243; CHECK: ld.w244; CHECK: ld.w245; CHECK: cle_u.w246; CHECK: st.w247; CHECK: .size llvm_mips_cle_u_w_test248;249@llvm_mips_cle_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16250@llvm_mips_cle_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16251@llvm_mips_cle_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16252 253define void @llvm_mips_cle_u_d_test() nounwind {254entry:255 %0 = load <2 x i64>, ptr @llvm_mips_cle_u_d_ARG1256 %1 = load <2 x i64>, ptr @llvm_mips_cle_u_d_ARG2257 %2 = tail call <2 x i64> @llvm.mips.cle.u.d(<2 x i64> %0, <2 x i64> %1)258 store <2 x i64> %2, ptr @llvm_mips_cle_u_d_RES259 ret void260}261 262declare <2 x i64> @llvm.mips.cle.u.d(<2 x i64>, <2 x i64>) nounwind263 264; CHECK: llvm_mips_cle_u_d_test:265; CHECK: ld.d266; CHECK: ld.d267; CHECK: cle_u.d268; CHECK: st.d269; CHECK: .size llvm_mips_cle_u_d_test270;271@llvm_mips_clt_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16272@llvm_mips_clt_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16273@llvm_mips_clt_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16274 275define void @llvm_mips_clt_s_b_test() nounwind {276entry:277 %0 = load <16 x i8>, ptr @llvm_mips_clt_s_b_ARG1278 %1 = load <16 x i8>, ptr @llvm_mips_clt_s_b_ARG2279 %2 = tail call <16 x i8> @llvm.mips.clt.s.b(<16 x i8> %0, <16 x i8> %1)280 store <16 x i8> %2, ptr @llvm_mips_clt_s_b_RES281 ret void282}283 284declare <16 x i8> @llvm.mips.clt.s.b(<16 x i8>, <16 x i8>) nounwind285 286; CHECK: llvm_mips_clt_s_b_test:287; CHECK: ld.b288; CHECK: ld.b289; CHECK: clt_s.b290; CHECK: st.b291; CHECK: .size llvm_mips_clt_s_b_test292;293@llvm_mips_clt_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16294@llvm_mips_clt_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16295@llvm_mips_clt_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16296 297define void @llvm_mips_clt_s_h_test() nounwind {298entry:299 %0 = load <8 x i16>, ptr @llvm_mips_clt_s_h_ARG1300 %1 = load <8 x i16>, ptr @llvm_mips_clt_s_h_ARG2301 %2 = tail call <8 x i16> @llvm.mips.clt.s.h(<8 x i16> %0, <8 x i16> %1)302 store <8 x i16> %2, ptr @llvm_mips_clt_s_h_RES303 ret void304}305 306declare <8 x i16> @llvm.mips.clt.s.h(<8 x i16>, <8 x i16>) nounwind307 308; CHECK: llvm_mips_clt_s_h_test:309; CHECK: ld.h310; CHECK: ld.h311; CHECK: clt_s.h312; CHECK: st.h313; CHECK: .size llvm_mips_clt_s_h_test314;315@llvm_mips_clt_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16316@llvm_mips_clt_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16317@llvm_mips_clt_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16318 319define void @llvm_mips_clt_s_w_test() nounwind {320entry:321 %0 = load <4 x i32>, ptr @llvm_mips_clt_s_w_ARG1322 %1 = load <4 x i32>, ptr @llvm_mips_clt_s_w_ARG2323 %2 = tail call <4 x i32> @llvm.mips.clt.s.w(<4 x i32> %0, <4 x i32> %1)324 store <4 x i32> %2, ptr @llvm_mips_clt_s_w_RES325 ret void326}327 328declare <4 x i32> @llvm.mips.clt.s.w(<4 x i32>, <4 x i32>) nounwind329 330; CHECK: llvm_mips_clt_s_w_test:331; CHECK: ld.w332; CHECK: ld.w333; CHECK: clt_s.w334; CHECK: st.w335; CHECK: .size llvm_mips_clt_s_w_test336;337@llvm_mips_clt_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16338@llvm_mips_clt_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16339@llvm_mips_clt_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16340 341define void @llvm_mips_clt_s_d_test() nounwind {342entry:343 %0 = load <2 x i64>, ptr @llvm_mips_clt_s_d_ARG1344 %1 = load <2 x i64>, ptr @llvm_mips_clt_s_d_ARG2345 %2 = tail call <2 x i64> @llvm.mips.clt.s.d(<2 x i64> %0, <2 x i64> %1)346 store <2 x i64> %2, ptr @llvm_mips_clt_s_d_RES347 ret void348}349 350declare <2 x i64> @llvm.mips.clt.s.d(<2 x i64>, <2 x i64>) nounwind351 352; CHECK: llvm_mips_clt_s_d_test:353; CHECK: ld.d354; CHECK: ld.d355; CHECK: clt_s.d356; CHECK: st.d357; CHECK: .size llvm_mips_clt_s_d_test358;359@llvm_mips_clt_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16360@llvm_mips_clt_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16361@llvm_mips_clt_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16362 363define void @llvm_mips_clt_u_b_test() nounwind {364entry:365 %0 = load <16 x i8>, ptr @llvm_mips_clt_u_b_ARG1366 %1 = load <16 x i8>, ptr @llvm_mips_clt_u_b_ARG2367 %2 = tail call <16 x i8> @llvm.mips.clt.u.b(<16 x i8> %0, <16 x i8> %1)368 store <16 x i8> %2, ptr @llvm_mips_clt_u_b_RES369 ret void370}371 372declare <16 x i8> @llvm.mips.clt.u.b(<16 x i8>, <16 x i8>) nounwind373 374; CHECK: llvm_mips_clt_u_b_test:375; CHECK: ld.b376; CHECK: ld.b377; CHECK: clt_u.b378; CHECK: st.b379; CHECK: .size llvm_mips_clt_u_b_test380;381@llvm_mips_clt_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16382@llvm_mips_clt_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16383@llvm_mips_clt_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16384 385define void @llvm_mips_clt_u_h_test() nounwind {386entry:387 %0 = load <8 x i16>, ptr @llvm_mips_clt_u_h_ARG1388 %1 = load <8 x i16>, ptr @llvm_mips_clt_u_h_ARG2389 %2 = tail call <8 x i16> @llvm.mips.clt.u.h(<8 x i16> %0, <8 x i16> %1)390 store <8 x i16> %2, ptr @llvm_mips_clt_u_h_RES391 ret void392}393 394declare <8 x i16> @llvm.mips.clt.u.h(<8 x i16>, <8 x i16>) nounwind395 396; CHECK: llvm_mips_clt_u_h_test:397; CHECK: ld.h398; CHECK: ld.h399; CHECK: clt_u.h400; CHECK: st.h401; CHECK: .size llvm_mips_clt_u_h_test402;403@llvm_mips_clt_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16404@llvm_mips_clt_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16405@llvm_mips_clt_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16406 407define void @llvm_mips_clt_u_w_test() nounwind {408entry:409 %0 = load <4 x i32>, ptr @llvm_mips_clt_u_w_ARG1410 %1 = load <4 x i32>, ptr @llvm_mips_clt_u_w_ARG2411 %2 = tail call <4 x i32> @llvm.mips.clt.u.w(<4 x i32> %0, <4 x i32> %1)412 store <4 x i32> %2, ptr @llvm_mips_clt_u_w_RES413 ret void414}415 416declare <4 x i32> @llvm.mips.clt.u.w(<4 x i32>, <4 x i32>) nounwind417 418; CHECK: llvm_mips_clt_u_w_test:419; CHECK: ld.w420; CHECK: ld.w421; CHECK: clt_u.w422; CHECK: st.w423; CHECK: .size llvm_mips_clt_u_w_test424;425@llvm_mips_clt_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16426@llvm_mips_clt_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16427@llvm_mips_clt_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16428 429define void @llvm_mips_clt_u_d_test() nounwind {430entry:431 %0 = load <2 x i64>, ptr @llvm_mips_clt_u_d_ARG1432 %1 = load <2 x i64>, ptr @llvm_mips_clt_u_d_ARG2433 %2 = tail call <2 x i64> @llvm.mips.clt.u.d(<2 x i64> %0, <2 x i64> %1)434 store <2 x i64> %2, ptr @llvm_mips_clt_u_d_RES435 ret void436}437 438declare <2 x i64> @llvm.mips.clt.u.d(<2 x i64>, <2 x i64>) nounwind439 440; CHECK: llvm_mips_clt_u_d_test:441; CHECK: ld.d442; CHECK: ld.d443; CHECK: clt_u.d444; CHECK: st.d445; CHECK: .size llvm_mips_clt_u_d_test446;447