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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'd'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_div_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_div_s_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_div_s_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_div_s_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1)16 store <16 x i8> %2, ptr @llvm_mips_div_s_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind21 22; CHECK: llvm_mips_div_s_b_test:23; CHECK: ld.b24; CHECK: ld.b25; CHECK: div_s.b26; CHECK: st.b27; CHECK: .size llvm_mips_div_s_b_test28;29@llvm_mips_div_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_div_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1631@llvm_mips_div_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1632 33define void @llvm_mips_div_s_h_test() nounwind {34entry:35 %0 = load <8 x i16>, ptr @llvm_mips_div_s_h_ARG136 %1 = load <8 x i16>, ptr @llvm_mips_div_s_h_ARG237 %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1)38 store <8 x i16> %2, ptr @llvm_mips_div_s_h_RES39 ret void40}41 42declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind43 44; CHECK: llvm_mips_div_s_h_test:45; CHECK: ld.h46; CHECK: ld.h47; CHECK: div_s.h48; CHECK: st.h49; CHECK: .size llvm_mips_div_s_h_test50;51@llvm_mips_div_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1652@llvm_mips_div_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1653@llvm_mips_div_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_div_s_w_test() nounwind {56entry:57 %0 = load <4 x i32>, ptr @llvm_mips_div_s_w_ARG158 %1 = load <4 x i32>, ptr @llvm_mips_div_s_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1)60 store <4 x i32> %2, ptr @llvm_mips_div_s_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind65 66; CHECK: llvm_mips_div_s_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: div_s.w70; CHECK: st.w71; CHECK: .size llvm_mips_div_s_w_test72;73@llvm_mips_div_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1674@llvm_mips_div_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1675@llvm_mips_div_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_div_s_d_test() nounwind {78entry:79 %0 = load <2 x i64>, ptr @llvm_mips_div_s_d_ARG180 %1 = load <2 x i64>, ptr @llvm_mips_div_s_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1)82 store <2 x i64> %2, ptr @llvm_mips_div_s_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind87 88; CHECK: llvm_mips_div_s_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: div_s.d92; CHECK: st.d93; CHECK: .size llvm_mips_div_s_d_test94;95 96define void @div_s_b_test() nounwind {97entry:98 %0 = load <16 x i8>, ptr @llvm_mips_div_s_b_ARG199 %1 = load <16 x i8>, ptr @llvm_mips_div_s_b_ARG2100 %2 = sdiv <16 x i8> %0, %1101 store <16 x i8> %2, ptr @llvm_mips_div_s_b_RES102 ret void103}104 105; CHECK: div_s_b_test:106; CHECK: ld.b107; CHECK: ld.b108; CHECK: div_s.b109; CHECK: st.b110; CHECK: .size div_s_b_test111 112define void @div_s_h_test() nounwind {113entry:114 %0 = load <8 x i16>, ptr @llvm_mips_div_s_h_ARG1115 %1 = load <8 x i16>, ptr @llvm_mips_div_s_h_ARG2116 %2 = sdiv <8 x i16> %0, %1117 store <8 x i16> %2, ptr @llvm_mips_div_s_h_RES118 ret void119}120 121; CHECK: div_s_h_test:122; CHECK: ld.h123; CHECK: ld.h124; CHECK: div_s.h125; CHECK: st.h126; CHECK: .size div_s_h_test127 128define void @div_s_w_test() nounwind {129entry:130 %0 = load <4 x i32>, ptr @llvm_mips_div_s_w_ARG1131 %1 = load <4 x i32>, ptr @llvm_mips_div_s_w_ARG2132 %2 = sdiv <4 x i32> %0, %1133 store <4 x i32> %2, ptr @llvm_mips_div_s_w_RES134 ret void135}136 137; CHECK: div_s_w_test:138; CHECK: ld.w139; CHECK: ld.w140; CHECK: div_s.w141; CHECK: st.w142; CHECK: .size div_s_w_test143 144define void @div_s_d_test() nounwind {145entry:146 %0 = load <2 x i64>, ptr @llvm_mips_div_s_d_ARG1147 %1 = load <2 x i64>, ptr @llvm_mips_div_s_d_ARG2148 %2 = sdiv <2 x i64> %0, %1149 store <2 x i64> %2, ptr @llvm_mips_div_s_d_RES150 ret void151}152 153; CHECK: div_s_d_test:154; CHECK: ld.d155; CHECK: ld.d156; CHECK: div_s.d157; CHECK: st.d158; CHECK: .size div_s_d_test159;160@llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16161@llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16162@llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16163 164define void @llvm_mips_div_u_b_test() nounwind {165entry:166 %0 = load <16 x i8>, ptr @llvm_mips_div_u_b_ARG1167 %1 = load <16 x i8>, ptr @llvm_mips_div_u_b_ARG2168 %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1)169 store <16 x i8> %2, ptr @llvm_mips_div_u_b_RES170 ret void171}172 173declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind174 175; CHECK: llvm_mips_div_u_b_test:176; CHECK: ld.b177; CHECK: ld.b178; CHECK: div_u.b179; CHECK: st.b180; CHECK: .size llvm_mips_div_u_b_test181;182@llvm_mips_div_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16183@llvm_mips_div_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16184@llvm_mips_div_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16185 186define void @llvm_mips_div_u_h_test() nounwind {187entry:188 %0 = load <8 x i16>, ptr @llvm_mips_div_u_h_ARG1189 %1 = load <8 x i16>, ptr @llvm_mips_div_u_h_ARG2190 %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1)191 store <8 x i16> %2, ptr @llvm_mips_div_u_h_RES192 ret void193}194 195declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind196 197; CHECK: llvm_mips_div_u_h_test:198; CHECK: ld.h199; CHECK: ld.h200; CHECK: div_u.h201; CHECK: st.h202; CHECK: .size llvm_mips_div_u_h_test203;204@llvm_mips_div_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16205@llvm_mips_div_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16206@llvm_mips_div_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16207 208define void @llvm_mips_div_u_w_test() nounwind {209entry:210 %0 = load <4 x i32>, ptr @llvm_mips_div_u_w_ARG1211 %1 = load <4 x i32>, ptr @llvm_mips_div_u_w_ARG2212 %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1)213 store <4 x i32> %2, ptr @llvm_mips_div_u_w_RES214 ret void215}216 217declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind218 219; CHECK: llvm_mips_div_u_w_test:220; CHECK: ld.w221; CHECK: ld.w222; CHECK: div_u.w223; CHECK: st.w224; CHECK: .size llvm_mips_div_u_w_test225;226@llvm_mips_div_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16227@llvm_mips_div_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16228@llvm_mips_div_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16229 230define void @llvm_mips_div_u_d_test() nounwind {231entry:232 %0 = load <2 x i64>, ptr @llvm_mips_div_u_d_ARG1233 %1 = load <2 x i64>, ptr @llvm_mips_div_u_d_ARG2234 %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1)235 store <2 x i64> %2, ptr @llvm_mips_div_u_d_RES236 ret void237}238 239declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind240 241; CHECK: llvm_mips_div_u_d_test:242; CHECK: ld.d243; CHECK: ld.d244; CHECK: div_u.d245; CHECK: st.d246; CHECK: .size llvm_mips_div_u_d_test247;248 249define void @div_u_b_test() nounwind {250entry:251 %0 = load <16 x i8>, ptr @llvm_mips_div_u_b_ARG1252 %1 = load <16 x i8>, ptr @llvm_mips_div_u_b_ARG2253 %2 = udiv <16 x i8> %0, %1254 store <16 x i8> %2, ptr @llvm_mips_div_u_b_RES255 ret void256}257 258; CHECK: div_u_b_test:259; CHECK: ld.b260; CHECK: ld.b261; CHECK: div_u.b262; CHECK: st.b263; CHECK: .size div_u_b_test264 265define void @div_u_h_test() nounwind {266entry:267 %0 = load <8 x i16>, ptr @llvm_mips_div_u_h_ARG1268 %1 = load <8 x i16>, ptr @llvm_mips_div_u_h_ARG2269 %2 = udiv <8 x i16> %0, %1270 store <8 x i16> %2, ptr @llvm_mips_div_u_h_RES271 ret void272}273 274; CHECK: div_u_h_test:275; CHECK: ld.h276; CHECK: ld.h277; CHECK: div_u.h278; CHECK: st.h279; CHECK: .size div_u_h_test280 281define void @div_u_w_test() nounwind {282entry:283 %0 = load <4 x i32>, ptr @llvm_mips_div_u_w_ARG1284 %1 = load <4 x i32>, ptr @llvm_mips_div_u_w_ARG2285 %2 = udiv <4 x i32> %0, %1286 store <4 x i32> %2, ptr @llvm_mips_div_u_w_RES287 ret void288}289 290; CHECK: div_u_w_test:291; CHECK: ld.w292; CHECK: ld.w293; CHECK: div_u.w294; CHECK: st.w295; CHECK: .size div_u_w_test296 297define void @div_u_d_test() nounwind {298entry:299 %0 = load <2 x i64>, ptr @llvm_mips_div_u_d_ARG1300 %1 = load <2 x i64>, ptr @llvm_mips_div_u_d_ARG2301 %2 = udiv <2 x i64> %0, %1302 store <2 x i64> %2, ptr @llvm_mips_div_u_d_RES303 ret void304}305 306; CHECK: div_u_d_test:307; CHECK: ld.d308; CHECK: ld.d309; CHECK: div_u.d310; CHECK: st.d311; CHECK: .size div_u_d_test312;313@llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,314 i8 4, i8 5, i8 6, i8 7,315 i8 8, i8 9, i8 10, i8 11,316 i8 12, i8 13, i8 14, i8 15>,317 align 16318@llvm_mips_dotp_s_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,319 i8 20, i8 21, i8 22, i8 23,320 i8 24, i8 25, i8 26, i8 27,321 i8 28, i8 29, i8 30, i8 31>,322 align 16323@llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,324 i16 0, i16 0, i16 0, i16 0>,325 align 16326 327define void @llvm_mips_dotp_s_h_test() nounwind {328entry:329 %0 = load <16 x i8>, ptr @llvm_mips_dotp_s_h_ARG1330 %1 = load <16 x i8>, ptr @llvm_mips_dotp_s_h_ARG2331 %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1)332 store <8 x i16> %2, ptr @llvm_mips_dotp_s_h_RES333 ret void334}335 336declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind337 338; CHECK: llvm_mips_dotp_s_h_test:339; CHECK: ld.b340; CHECK: ld.b341; CHECK: dotp_s.h342; CHECK: st.h343; CHECK: .size llvm_mips_dotp_s_h_test344;345@llvm_mips_dotp_s_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,346 i16 4, i16 5, i16 6, i16 7>,347 align 16348@llvm_mips_dotp_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,349 i16 8, i16 9, i16 10, i16 11>,350 align 16351@llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,352 align 16353 354define void @llvm_mips_dotp_s_w_test() nounwind {355entry:356 %0 = load <8 x i16>, ptr @llvm_mips_dotp_s_w_ARG1357 %1 = load <8 x i16>, ptr @llvm_mips_dotp_s_w_ARG2358 %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1)359 store <4 x i32> %2, ptr @llvm_mips_dotp_s_w_RES360 ret void361}362 363declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind364 365; CHECK: llvm_mips_dotp_s_w_test:366; CHECK: ld.h367; CHECK: ld.h368; CHECK: dotp_s.w369; CHECK: st.w370; CHECK: .size llvm_mips_dotp_s_w_test371;372@llvm_mips_dotp_s_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,373 align 16374@llvm_mips_dotp_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,375 align 16376@llvm_mips_dotp_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16377 378define void @llvm_mips_dotp_s_d_test() nounwind {379entry:380 %0 = load <4 x i32>, ptr @llvm_mips_dotp_s_d_ARG1381 %1 = load <4 x i32>, ptr @llvm_mips_dotp_s_d_ARG2382 %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1)383 store <2 x i64> %2, ptr @llvm_mips_dotp_s_d_RES384 ret void385}386 387declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind388 389; CHECK: llvm_mips_dotp_s_d_test:390; CHECK: ld.w391; CHECK: ld.w392; CHECK: dotp_s.d393; CHECK: st.d394; CHECK: .size llvm_mips_dotp_s_d_test395;396@llvm_mips_dotp_u_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,397 i8 4, i8 5, i8 6, i8 7,398 i8 8, i8 9, i8 10, i8 11,399 i8 12, i8 13, i8 14, i8 15>,400 align 16401@llvm_mips_dotp_u_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,402 i8 20, i8 21, i8 22, i8 23,403 i8 24, i8 25, i8 26, i8 27,404 i8 28, i8 29, i8 30, i8 31>,405 align 16406@llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,407 i16 0, i16 0, i16 0, i16 0>,408 align 16409 410define void @llvm_mips_dotp_u_h_test() nounwind {411entry:412 %0 = load <16 x i8>, ptr @llvm_mips_dotp_u_h_ARG1413 %1 = load <16 x i8>, ptr @llvm_mips_dotp_u_h_ARG2414 %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1)415 store <8 x i16> %2, ptr @llvm_mips_dotp_u_h_RES416 ret void417}418 419declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind420 421; CHECK: llvm_mips_dotp_u_h_test:422; CHECK: ld.b423; CHECK: ld.b424; CHECK: dotp_u.h425; CHECK: st.h426; CHECK: .size llvm_mips_dotp_u_h_test427;428@llvm_mips_dotp_u_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,429 i16 4, i16 5, i16 6, i16 7>,430 align 16431@llvm_mips_dotp_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,432 i16 8, i16 9, i16 10, i16 11>,433 align 16434@llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,435 align 16436 437define void @llvm_mips_dotp_u_w_test() nounwind {438entry:439 %0 = load <8 x i16>, ptr @llvm_mips_dotp_u_w_ARG1440 %1 = load <8 x i16>, ptr @llvm_mips_dotp_u_w_ARG2441 %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1)442 store <4 x i32> %2, ptr @llvm_mips_dotp_u_w_RES443 ret void444}445 446declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind447 448; CHECK: llvm_mips_dotp_u_w_test:449; CHECK: ld.h450; CHECK: ld.h451; CHECK: dotp_u.w452; CHECK: st.w453; CHECK: .size llvm_mips_dotp_u_w_test454;455@llvm_mips_dotp_u_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,456 align 16457@llvm_mips_dotp_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,458 align 16459@llvm_mips_dotp_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16460 461define void @llvm_mips_dotp_u_d_test() nounwind {462entry:463 %0 = load <4 x i32>, ptr @llvm_mips_dotp_u_d_ARG1464 %1 = load <4 x i32>, ptr @llvm_mips_dotp_u_d_ARG2465 %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1)466 store <2 x i64> %2, ptr @llvm_mips_dotp_u_d_RES467 ret void468}469 470declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind471 472; CHECK: llvm_mips_dotp_u_d_test:473; CHECK: ld.w474; CHECK: ld.w475; CHECK: dotp_u.d476; CHECK: st.d477; CHECK: .size llvm_mips_dotp_u_d_test478;479