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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'm'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_max_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_max_a_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_max_a_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_max_a_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.max.a.b(<16 x i8> %0, <16 x i8> %1)16 store <16 x i8> %2, ptr @llvm_mips_max_a_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.max.a.b(<16 x i8>, <16 x i8>) nounwind21 22; CHECK: llvm_mips_max_a_b_test:23; CHECK: ld.b24; CHECK: ld.b25; CHECK: max_a.b26; CHECK: st.b27; CHECK: .size llvm_mips_max_a_b_test28;29@llvm_mips_max_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_max_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1631@llvm_mips_max_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1632 33define void @llvm_mips_max_a_h_test() nounwind {34entry:35 %0 = load <8 x i16>, ptr @llvm_mips_max_a_h_ARG136 %1 = load <8 x i16>, ptr @llvm_mips_max_a_h_ARG237 %2 = tail call <8 x i16> @llvm.mips.max.a.h(<8 x i16> %0, <8 x i16> %1)38 store <8 x i16> %2, ptr @llvm_mips_max_a_h_RES39 ret void40}41 42declare <8 x i16> @llvm.mips.max.a.h(<8 x i16>, <8 x i16>) nounwind43 44; CHECK: llvm_mips_max_a_h_test:45; CHECK: ld.h46; CHECK: ld.h47; CHECK: max_a.h48; CHECK: st.h49; CHECK: .size llvm_mips_max_a_h_test50;51@llvm_mips_max_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1652@llvm_mips_max_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1653@llvm_mips_max_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_max_a_w_test() nounwind {56entry:57 %0 = load <4 x i32>, ptr @llvm_mips_max_a_w_ARG158 %1 = load <4 x i32>, ptr @llvm_mips_max_a_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.max.a.w(<4 x i32> %0, <4 x i32> %1)60 store <4 x i32> %2, ptr @llvm_mips_max_a_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.max.a.w(<4 x i32>, <4 x i32>) nounwind65 66; CHECK: llvm_mips_max_a_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: max_a.w70; CHECK: st.w71; CHECK: .size llvm_mips_max_a_w_test72;73@llvm_mips_max_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1674@llvm_mips_max_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1675@llvm_mips_max_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_max_a_d_test() nounwind {78entry:79 %0 = load <2 x i64>, ptr @llvm_mips_max_a_d_ARG180 %1 = load <2 x i64>, ptr @llvm_mips_max_a_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.max.a.d(<2 x i64> %0, <2 x i64> %1)82 store <2 x i64> %2, ptr @llvm_mips_max_a_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.max.a.d(<2 x i64>, <2 x i64>) nounwind87 88; CHECK: llvm_mips_max_a_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: max_a.d92; CHECK: st.d93; CHECK: .size llvm_mips_max_a_d_test94;95@llvm_mips_max_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1696@llvm_mips_max_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1697@llvm_mips_max_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1698 99define void @llvm_mips_max_s_b_test() nounwind {100entry:101 %0 = load <16 x i8>, ptr @llvm_mips_max_s_b_ARG1102 %1 = load <16 x i8>, ptr @llvm_mips_max_s_b_ARG2103 %2 = tail call <16 x i8> @llvm.mips.max.s.b(<16 x i8> %0, <16 x i8> %1)104 store <16 x i8> %2, ptr @llvm_mips_max_s_b_RES105 ret void106}107 108declare <16 x i8> @llvm.mips.max.s.b(<16 x i8>, <16 x i8>) nounwind109 110; CHECK: llvm_mips_max_s_b_test:111; CHECK: ld.b112; CHECK: ld.b113; CHECK: max_s.b114; CHECK: st.b115; CHECK: .size llvm_mips_max_s_b_test116;117@llvm_mips_max_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16118@llvm_mips_max_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16119@llvm_mips_max_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16120 121define void @llvm_mips_max_s_h_test() nounwind {122entry:123 %0 = load <8 x i16>, ptr @llvm_mips_max_s_h_ARG1124 %1 = load <8 x i16>, ptr @llvm_mips_max_s_h_ARG2125 %2 = tail call <8 x i16> @llvm.mips.max.s.h(<8 x i16> %0, <8 x i16> %1)126 store <8 x i16> %2, ptr @llvm_mips_max_s_h_RES127 ret void128}129 130declare <8 x i16> @llvm.mips.max.s.h(<8 x i16>, <8 x i16>) nounwind131 132; CHECK: llvm_mips_max_s_h_test:133; CHECK: ld.h134; CHECK: ld.h135; CHECK: max_s.h136; CHECK: st.h137; CHECK: .size llvm_mips_max_s_h_test138;139@llvm_mips_max_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16140@llvm_mips_max_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16141@llvm_mips_max_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16142 143define void @llvm_mips_max_s_w_test() nounwind {144entry:145 %0 = load <4 x i32>, ptr @llvm_mips_max_s_w_ARG1146 %1 = load <4 x i32>, ptr @llvm_mips_max_s_w_ARG2147 %2 = tail call <4 x i32> @llvm.mips.max.s.w(<4 x i32> %0, <4 x i32> %1)148 store <4 x i32> %2, ptr @llvm_mips_max_s_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.max.s.w(<4 x i32>, <4 x i32>) nounwind153 154; CHECK: llvm_mips_max_s_w_test:155; CHECK: ld.w156; CHECK: ld.w157; CHECK: max_s.w158; CHECK: st.w159; CHECK: .size llvm_mips_max_s_w_test160;161@llvm_mips_max_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16162@llvm_mips_max_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16163@llvm_mips_max_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16164 165define void @llvm_mips_max_s_d_test() nounwind {166entry:167 %0 = load <2 x i64>, ptr @llvm_mips_max_s_d_ARG1168 %1 = load <2 x i64>, ptr @llvm_mips_max_s_d_ARG2169 %2 = tail call <2 x i64> @llvm.mips.max.s.d(<2 x i64> %0, <2 x i64> %1)170 store <2 x i64> %2, ptr @llvm_mips_max_s_d_RES171 ret void172}173 174declare <2 x i64> @llvm.mips.max.s.d(<2 x i64>, <2 x i64>) nounwind175 176; CHECK: llvm_mips_max_s_d_test:177; CHECK: ld.d178; CHECK: ld.d179; CHECK: max_s.d180; CHECK: st.d181; CHECK: .size llvm_mips_max_s_d_test182;183@llvm_mips_max_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16184@llvm_mips_max_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16185@llvm_mips_max_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16186 187define void @llvm_mips_max_u_b_test() nounwind {188entry:189 %0 = load <16 x i8>, ptr @llvm_mips_max_u_b_ARG1190 %1 = load <16 x i8>, ptr @llvm_mips_max_u_b_ARG2191 %2 = tail call <16 x i8> @llvm.mips.max.u.b(<16 x i8> %0, <16 x i8> %1)192 store <16 x i8> %2, ptr @llvm_mips_max_u_b_RES193 ret void194}195 196declare <16 x i8> @llvm.mips.max.u.b(<16 x i8>, <16 x i8>) nounwind197 198; CHECK: llvm_mips_max_u_b_test:199; CHECK: ld.b200; CHECK: ld.b201; CHECK: max_u.b202; CHECK: st.b203; CHECK: .size llvm_mips_max_u_b_test204;205@llvm_mips_max_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16206@llvm_mips_max_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16207@llvm_mips_max_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16208 209define void @llvm_mips_max_u_h_test() nounwind {210entry:211 %0 = load <8 x i16>, ptr @llvm_mips_max_u_h_ARG1212 %1 = load <8 x i16>, ptr @llvm_mips_max_u_h_ARG2213 %2 = tail call <8 x i16> @llvm.mips.max.u.h(<8 x i16> %0, <8 x i16> %1)214 store <8 x i16> %2, ptr @llvm_mips_max_u_h_RES215 ret void216}217 218declare <8 x i16> @llvm.mips.max.u.h(<8 x i16>, <8 x i16>) nounwind219 220; CHECK: llvm_mips_max_u_h_test:221; CHECK: ld.h222; CHECK: ld.h223; CHECK: max_u.h224; CHECK: st.h225; CHECK: .size llvm_mips_max_u_h_test226;227@llvm_mips_max_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16228@llvm_mips_max_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16229@llvm_mips_max_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16230 231define void @llvm_mips_max_u_w_test() nounwind {232entry:233 %0 = load <4 x i32>, ptr @llvm_mips_max_u_w_ARG1234 %1 = load <4 x i32>, ptr @llvm_mips_max_u_w_ARG2235 %2 = tail call <4 x i32> @llvm.mips.max.u.w(<4 x i32> %0, <4 x i32> %1)236 store <4 x i32> %2, ptr @llvm_mips_max_u_w_RES237 ret void238}239 240declare <4 x i32> @llvm.mips.max.u.w(<4 x i32>, <4 x i32>) nounwind241 242; CHECK: llvm_mips_max_u_w_test:243; CHECK: ld.w244; CHECK: ld.w245; CHECK: max_u.w246; CHECK: st.w247; CHECK: .size llvm_mips_max_u_w_test248;249@llvm_mips_max_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16250@llvm_mips_max_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16251@llvm_mips_max_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16252 253define void @llvm_mips_max_u_d_test() nounwind {254entry:255 %0 = load <2 x i64>, ptr @llvm_mips_max_u_d_ARG1256 %1 = load <2 x i64>, ptr @llvm_mips_max_u_d_ARG2257 %2 = tail call <2 x i64> @llvm.mips.max.u.d(<2 x i64> %0, <2 x i64> %1)258 store <2 x i64> %2, ptr @llvm_mips_max_u_d_RES259 ret void260}261 262declare <2 x i64> @llvm.mips.max.u.d(<2 x i64>, <2 x i64>) nounwind263 264; CHECK: llvm_mips_max_u_d_test:265; CHECK: ld.d266; CHECK: ld.d267; CHECK: max_u.d268; CHECK: st.d269; CHECK: .size llvm_mips_max_u_d_test270;271@llvm_mips_min_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16272@llvm_mips_min_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16273@llvm_mips_min_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16274 275define void @llvm_mips_min_a_b_test() nounwind {276entry:277 %0 = load <16 x i8>, ptr @llvm_mips_min_a_b_ARG1278 %1 = load <16 x i8>, ptr @llvm_mips_min_a_b_ARG2279 %2 = tail call <16 x i8> @llvm.mips.min.a.b(<16 x i8> %0, <16 x i8> %1)280 store <16 x i8> %2, ptr @llvm_mips_min_a_b_RES281 ret void282}283 284declare <16 x i8> @llvm.mips.min.a.b(<16 x i8>, <16 x i8>) nounwind285 286; CHECK: llvm_mips_min_a_b_test:287; CHECK: ld.b288; CHECK: ld.b289; CHECK: min_a.b290; CHECK: st.b291; CHECK: .size llvm_mips_min_a_b_test292;293@llvm_mips_min_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16294@llvm_mips_min_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16295@llvm_mips_min_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16296 297define void @llvm_mips_min_a_h_test() nounwind {298entry:299 %0 = load <8 x i16>, ptr @llvm_mips_min_a_h_ARG1300 %1 = load <8 x i16>, ptr @llvm_mips_min_a_h_ARG2301 %2 = tail call <8 x i16> @llvm.mips.min.a.h(<8 x i16> %0, <8 x i16> %1)302 store <8 x i16> %2, ptr @llvm_mips_min_a_h_RES303 ret void304}305 306declare <8 x i16> @llvm.mips.min.a.h(<8 x i16>, <8 x i16>) nounwind307 308; CHECK: llvm_mips_min_a_h_test:309; CHECK: ld.h310; CHECK: ld.h311; CHECK: min_a.h312; CHECK: st.h313; CHECK: .size llvm_mips_min_a_h_test314;315@llvm_mips_min_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16316@llvm_mips_min_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16317@llvm_mips_min_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16318 319define void @llvm_mips_min_a_w_test() nounwind {320entry:321 %0 = load <4 x i32>, ptr @llvm_mips_min_a_w_ARG1322 %1 = load <4 x i32>, ptr @llvm_mips_min_a_w_ARG2323 %2 = tail call <4 x i32> @llvm.mips.min.a.w(<4 x i32> %0, <4 x i32> %1)324 store <4 x i32> %2, ptr @llvm_mips_min_a_w_RES325 ret void326}327 328declare <4 x i32> @llvm.mips.min.a.w(<4 x i32>, <4 x i32>) nounwind329 330; CHECK: llvm_mips_min_a_w_test:331; CHECK: ld.w332; CHECK: ld.w333; CHECK: min_a.w334; CHECK: st.w335; CHECK: .size llvm_mips_min_a_w_test336;337@llvm_mips_min_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16338@llvm_mips_min_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16339@llvm_mips_min_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16340 341define void @llvm_mips_min_a_d_test() nounwind {342entry:343 %0 = load <2 x i64>, ptr @llvm_mips_min_a_d_ARG1344 %1 = load <2 x i64>, ptr @llvm_mips_min_a_d_ARG2345 %2 = tail call <2 x i64> @llvm.mips.min.a.d(<2 x i64> %0, <2 x i64> %1)346 store <2 x i64> %2, ptr @llvm_mips_min_a_d_RES347 ret void348}349 350declare <2 x i64> @llvm.mips.min.a.d(<2 x i64>, <2 x i64>) nounwind351 352; CHECK: llvm_mips_min_a_d_test:353; CHECK: ld.d354; CHECK: ld.d355; CHECK: min_a.d356; CHECK: st.d357; CHECK: .size llvm_mips_min_a_d_test358;359@llvm_mips_min_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16360@llvm_mips_min_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16361@llvm_mips_min_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16362 363define void @llvm_mips_min_s_b_test() nounwind {364entry:365 %0 = load <16 x i8>, ptr @llvm_mips_min_s_b_ARG1366 %1 = load <16 x i8>, ptr @llvm_mips_min_s_b_ARG2367 %2 = tail call <16 x i8> @llvm.mips.min.s.b(<16 x i8> %0, <16 x i8> %1)368 store <16 x i8> %2, ptr @llvm_mips_min_s_b_RES369 ret void370}371 372declare <16 x i8> @llvm.mips.min.s.b(<16 x i8>, <16 x i8>) nounwind373 374; CHECK: llvm_mips_min_s_b_test:375; CHECK: ld.b376; CHECK: ld.b377; CHECK: min_s.b378; CHECK: st.b379; CHECK: .size llvm_mips_min_s_b_test380;381@llvm_mips_min_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16382@llvm_mips_min_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16383@llvm_mips_min_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16384 385define void @llvm_mips_min_s_h_test() nounwind {386entry:387 %0 = load <8 x i16>, ptr @llvm_mips_min_s_h_ARG1388 %1 = load <8 x i16>, ptr @llvm_mips_min_s_h_ARG2389 %2 = tail call <8 x i16> @llvm.mips.min.s.h(<8 x i16> %0, <8 x i16> %1)390 store <8 x i16> %2, ptr @llvm_mips_min_s_h_RES391 ret void392}393 394declare <8 x i16> @llvm.mips.min.s.h(<8 x i16>, <8 x i16>) nounwind395 396; CHECK: llvm_mips_min_s_h_test:397; CHECK: ld.h398; CHECK: ld.h399; CHECK: min_s.h400; CHECK: st.h401; CHECK: .size llvm_mips_min_s_h_test402;403@llvm_mips_min_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16404@llvm_mips_min_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16405@llvm_mips_min_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16406 407define void @llvm_mips_min_s_w_test() nounwind {408entry:409 %0 = load <4 x i32>, ptr @llvm_mips_min_s_w_ARG1410 %1 = load <4 x i32>, ptr @llvm_mips_min_s_w_ARG2411 %2 = tail call <4 x i32> @llvm.mips.min.s.w(<4 x i32> %0, <4 x i32> %1)412 store <4 x i32> %2, ptr @llvm_mips_min_s_w_RES413 ret void414}415 416declare <4 x i32> @llvm.mips.min.s.w(<4 x i32>, <4 x i32>) nounwind417 418; CHECK: llvm_mips_min_s_w_test:419; CHECK: ld.w420; CHECK: ld.w421; CHECK: min_s.w422; CHECK: st.w423; CHECK: .size llvm_mips_min_s_w_test424;425@llvm_mips_min_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16426@llvm_mips_min_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16427@llvm_mips_min_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16428 429define void @llvm_mips_min_s_d_test() nounwind {430entry:431 %0 = load <2 x i64>, ptr @llvm_mips_min_s_d_ARG1432 %1 = load <2 x i64>, ptr @llvm_mips_min_s_d_ARG2433 %2 = tail call <2 x i64> @llvm.mips.min.s.d(<2 x i64> %0, <2 x i64> %1)434 store <2 x i64> %2, ptr @llvm_mips_min_s_d_RES435 ret void436}437 438declare <2 x i64> @llvm.mips.min.s.d(<2 x i64>, <2 x i64>) nounwind439 440; CHECK: llvm_mips_min_s_d_test:441; CHECK: ld.d442; CHECK: ld.d443; CHECK: min_s.d444; CHECK: st.d445; CHECK: .size llvm_mips_min_s_d_test446;447@llvm_mips_min_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16448@llvm_mips_min_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16449@llvm_mips_min_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16450 451define void @llvm_mips_min_u_b_test() nounwind {452entry:453 %0 = load <16 x i8>, ptr @llvm_mips_min_u_b_ARG1454 %1 = load <16 x i8>, ptr @llvm_mips_min_u_b_ARG2455 %2 = tail call <16 x i8> @llvm.mips.min.u.b(<16 x i8> %0, <16 x i8> %1)456 store <16 x i8> %2, ptr @llvm_mips_min_u_b_RES457 ret void458}459 460declare <16 x i8> @llvm.mips.min.u.b(<16 x i8>, <16 x i8>) nounwind461 462; CHECK: llvm_mips_min_u_b_test:463; CHECK: ld.b464; CHECK: ld.b465; CHECK: min_u.b466; CHECK: st.b467; CHECK: .size llvm_mips_min_u_b_test468;469@llvm_mips_min_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16470@llvm_mips_min_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16471@llvm_mips_min_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16472 473define void @llvm_mips_min_u_h_test() nounwind {474entry:475 %0 = load <8 x i16>, ptr @llvm_mips_min_u_h_ARG1476 %1 = load <8 x i16>, ptr @llvm_mips_min_u_h_ARG2477 %2 = tail call <8 x i16> @llvm.mips.min.u.h(<8 x i16> %0, <8 x i16> %1)478 store <8 x i16> %2, ptr @llvm_mips_min_u_h_RES479 ret void480}481 482declare <8 x i16> @llvm.mips.min.u.h(<8 x i16>, <8 x i16>) nounwind483 484; CHECK: llvm_mips_min_u_h_test:485; CHECK: ld.h486; CHECK: ld.h487; CHECK: min_u.h488; CHECK: st.h489; CHECK: .size llvm_mips_min_u_h_test490;491@llvm_mips_min_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16492@llvm_mips_min_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16493@llvm_mips_min_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16494 495define void @llvm_mips_min_u_w_test() nounwind {496entry:497 %0 = load <4 x i32>, ptr @llvm_mips_min_u_w_ARG1498 %1 = load <4 x i32>, ptr @llvm_mips_min_u_w_ARG2499 %2 = tail call <4 x i32> @llvm.mips.min.u.w(<4 x i32> %0, <4 x i32> %1)500 store <4 x i32> %2, ptr @llvm_mips_min_u_w_RES501 ret void502}503 504declare <4 x i32> @llvm.mips.min.u.w(<4 x i32>, <4 x i32>) nounwind505 506; CHECK: llvm_mips_min_u_w_test:507; CHECK: ld.w508; CHECK: ld.w509; CHECK: min_u.w510; CHECK: st.w511; CHECK: .size llvm_mips_min_u_w_test512;513@llvm_mips_min_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16514@llvm_mips_min_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16515@llvm_mips_min_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16516 517define void @llvm_mips_min_u_d_test() nounwind {518entry:519 %0 = load <2 x i64>, ptr @llvm_mips_min_u_d_ARG1520 %1 = load <2 x i64>, ptr @llvm_mips_min_u_d_ARG2521 %2 = tail call <2 x i64> @llvm.mips.min.u.d(<2 x i64> %0, <2 x i64> %1)522 store <2 x i64> %2, ptr @llvm_mips_min_u_d_RES523 ret void524}525 526declare <2 x i64> @llvm.mips.min.u.d(<2 x i64>, <2 x i64>) nounwind527 528; CHECK: llvm_mips_min_u_d_test:529; CHECK: ld.d530; CHECK: ld.d531; CHECK: min_u.d532; CHECK: st.d533; CHECK: .size llvm_mips_min_u_d_test534;535@llvm_mips_mod_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16536@llvm_mips_mod_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16537@llvm_mips_mod_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16538 539define void @llvm_mips_mod_s_b_test() nounwind {540entry:541 %0 = load <16 x i8>, ptr @llvm_mips_mod_s_b_ARG1542 %1 = load <16 x i8>, ptr @llvm_mips_mod_s_b_ARG2543 %2 = tail call <16 x i8> @llvm.mips.mod.s.b(<16 x i8> %0, <16 x i8> %1)544 store <16 x i8> %2, ptr @llvm_mips_mod_s_b_RES545 ret void546}547 548declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>) nounwind549 550; CHECK: llvm_mips_mod_s_b_test:551; CHECK: ld.b552; CHECK: ld.b553; CHECK: mod_s.b554; CHECK: st.b555; CHECK: .size llvm_mips_mod_s_b_test556;557@llvm_mips_mod_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16558@llvm_mips_mod_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16559@llvm_mips_mod_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16560 561define void @llvm_mips_mod_s_h_test() nounwind {562entry:563 %0 = load <8 x i16>, ptr @llvm_mips_mod_s_h_ARG1564 %1 = load <8 x i16>, ptr @llvm_mips_mod_s_h_ARG2565 %2 = tail call <8 x i16> @llvm.mips.mod.s.h(<8 x i16> %0, <8 x i16> %1)566 store <8 x i16> %2, ptr @llvm_mips_mod_s_h_RES567 ret void568}569 570declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>) nounwind571 572; CHECK: llvm_mips_mod_s_h_test:573; CHECK: ld.h574; CHECK: ld.h575; CHECK: mod_s.h576; CHECK: st.h577; CHECK: .size llvm_mips_mod_s_h_test578;579@llvm_mips_mod_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16580@llvm_mips_mod_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16581@llvm_mips_mod_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16582 583define void @llvm_mips_mod_s_w_test() nounwind {584entry:585 %0 = load <4 x i32>, ptr @llvm_mips_mod_s_w_ARG1586 %1 = load <4 x i32>, ptr @llvm_mips_mod_s_w_ARG2587 %2 = tail call <4 x i32> @llvm.mips.mod.s.w(<4 x i32> %0, <4 x i32> %1)588 store <4 x i32> %2, ptr @llvm_mips_mod_s_w_RES589 ret void590}591 592declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>) nounwind593 594; CHECK: llvm_mips_mod_s_w_test:595; CHECK: ld.w596; CHECK: ld.w597; CHECK: mod_s.w598; CHECK: st.w599; CHECK: .size llvm_mips_mod_s_w_test600;601@llvm_mips_mod_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16602@llvm_mips_mod_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16603@llvm_mips_mod_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16604 605define void @llvm_mips_mod_s_d_test() nounwind {606entry:607 %0 = load <2 x i64>, ptr @llvm_mips_mod_s_d_ARG1608 %1 = load <2 x i64>, ptr @llvm_mips_mod_s_d_ARG2609 %2 = tail call <2 x i64> @llvm.mips.mod.s.d(<2 x i64> %0, <2 x i64> %1)610 store <2 x i64> %2, ptr @llvm_mips_mod_s_d_RES611 ret void612}613 614declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>) nounwind615 616; CHECK: llvm_mips_mod_s_d_test:617; CHECK: ld.d618; CHECK: ld.d619; CHECK: mod_s.d620; CHECK: st.d621; CHECK: .size llvm_mips_mod_s_d_test622;623@llvm_mips_mod_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16624@llvm_mips_mod_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16625@llvm_mips_mod_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16626 627define void @llvm_mips_mod_u_b_test() nounwind {628entry:629 %0 = load <16 x i8>, ptr @llvm_mips_mod_u_b_ARG1630 %1 = load <16 x i8>, ptr @llvm_mips_mod_u_b_ARG2631 %2 = tail call <16 x i8> @llvm.mips.mod.u.b(<16 x i8> %0, <16 x i8> %1)632 store <16 x i8> %2, ptr @llvm_mips_mod_u_b_RES633 ret void634}635 636declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>) nounwind637 638; CHECK: llvm_mips_mod_u_b_test:639; CHECK: ld.b640; CHECK: ld.b641; CHECK: mod_u.b642; CHECK: st.b643; CHECK: .size llvm_mips_mod_u_b_test644;645@llvm_mips_mod_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16646@llvm_mips_mod_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16647@llvm_mips_mod_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16648 649define void @llvm_mips_mod_u_h_test() nounwind {650entry:651 %0 = load <8 x i16>, ptr @llvm_mips_mod_u_h_ARG1652 %1 = load <8 x i16>, ptr @llvm_mips_mod_u_h_ARG2653 %2 = tail call <8 x i16> @llvm.mips.mod.u.h(<8 x i16> %0, <8 x i16> %1)654 store <8 x i16> %2, ptr @llvm_mips_mod_u_h_RES655 ret void656}657 658declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>) nounwind659 660; CHECK: llvm_mips_mod_u_h_test:661; CHECK: ld.h662; CHECK: ld.h663; CHECK: mod_u.h664; CHECK: st.h665; CHECK: .size llvm_mips_mod_u_h_test666;667@llvm_mips_mod_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16668@llvm_mips_mod_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16669@llvm_mips_mod_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16670 671define void @llvm_mips_mod_u_w_test() nounwind {672entry:673 %0 = load <4 x i32>, ptr @llvm_mips_mod_u_w_ARG1674 %1 = load <4 x i32>, ptr @llvm_mips_mod_u_w_ARG2675 %2 = tail call <4 x i32> @llvm.mips.mod.u.w(<4 x i32> %0, <4 x i32> %1)676 store <4 x i32> %2, ptr @llvm_mips_mod_u_w_RES677 ret void678}679 680declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>) nounwind681 682; CHECK: llvm_mips_mod_u_w_test:683; CHECK: ld.w684; CHECK: ld.w685; CHECK: mod_u.w686; CHECK: st.w687; CHECK: .size llvm_mips_mod_u_w_test688;689@llvm_mips_mod_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16690@llvm_mips_mod_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16691@llvm_mips_mod_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16692 693define void @llvm_mips_mod_u_d_test() nounwind {694entry:695 %0 = load <2 x i64>, ptr @llvm_mips_mod_u_d_ARG1696 %1 = load <2 x i64>, ptr @llvm_mips_mod_u_d_ARG2697 %2 = tail call <2 x i64> @llvm.mips.mod.u.d(<2 x i64> %0, <2 x i64> %1)698 store <2 x i64> %2, ptr @llvm_mips_mod_u_d_RES699 ret void700}701 702declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>) nounwind703 704; CHECK: llvm_mips_mod_u_d_test:705; CHECK: ld.d706; CHECK: ld.d707; CHECK: mod_u.d708; CHECK: st.d709; CHECK: .size llvm_mips_mod_u_d_test710;711@llvm_mips_mulv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16712@llvm_mips_mulv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16713@llvm_mips_mulv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16714 715define void @llvm_mips_mulv_b_test() nounwind {716entry:717 %0 = load <16 x i8>, ptr @llvm_mips_mulv_b_ARG1718 %1 = load <16 x i8>, ptr @llvm_mips_mulv_b_ARG2719 %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)720 store <16 x i8> %2, ptr @llvm_mips_mulv_b_RES721 ret void722}723 724declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>) nounwind725 726; CHECK: llvm_mips_mulv_b_test:727; CHECK: ld.b728; CHECK: ld.b729; CHECK: mulv.b730; CHECK: st.b731; CHECK: .size llvm_mips_mulv_b_test732;733@llvm_mips_mulv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16734@llvm_mips_mulv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16735@llvm_mips_mulv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16736 737define void @llvm_mips_mulv_h_test() nounwind {738entry:739 %0 = load <8 x i16>, ptr @llvm_mips_mulv_h_ARG1740 %1 = load <8 x i16>, ptr @llvm_mips_mulv_h_ARG2741 %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)742 store <8 x i16> %2, ptr @llvm_mips_mulv_h_RES743 ret void744}745 746declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>) nounwind747 748; CHECK: llvm_mips_mulv_h_test:749; CHECK: ld.h750; CHECK: ld.h751; CHECK: mulv.h752; CHECK: st.h753; CHECK: .size llvm_mips_mulv_h_test754;755@llvm_mips_mulv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16756@llvm_mips_mulv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16757@llvm_mips_mulv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16758 759define void @llvm_mips_mulv_w_test() nounwind {760entry:761 %0 = load <4 x i32>, ptr @llvm_mips_mulv_w_ARG1762 %1 = load <4 x i32>, ptr @llvm_mips_mulv_w_ARG2763 %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)764 store <4 x i32> %2, ptr @llvm_mips_mulv_w_RES765 ret void766}767 768declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>) nounwind769 770; CHECK: llvm_mips_mulv_w_test:771; CHECK: ld.w772; CHECK: ld.w773; CHECK: mulv.w774; CHECK: st.w775; CHECK: .size llvm_mips_mulv_w_test776;777@llvm_mips_mulv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16778@llvm_mips_mulv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16779@llvm_mips_mulv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16780 781define void @llvm_mips_mulv_d_test() nounwind {782entry:783 %0 = load <2 x i64>, ptr @llvm_mips_mulv_d_ARG1784 %1 = load <2 x i64>, ptr @llvm_mips_mulv_d_ARG2785 %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)786 store <2 x i64> %2, ptr @llvm_mips_mulv_d_RES787 ret void788}789 790declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) nounwind791 792; CHECK: llvm_mips_mulv_d_test:793; CHECK: ld.d794; CHECK: ld.d795; CHECK: mulv.d796; CHECK: st.d797; CHECK: .size llvm_mips_mulv_d_test798 799define void @mulv_b_test() nounwind {800entry:801 %0 = load <16 x i8>, ptr @llvm_mips_mulv_b_ARG1802 %1 = load <16 x i8>, ptr @llvm_mips_mulv_b_ARG2803 %2 = mul <16 x i8> %0, %1804 store <16 x i8> %2, ptr @llvm_mips_mulv_b_RES805 ret void806}807 808; CHECK: mulv_b_test:809; CHECK: ld.b810; CHECK: ld.b811; CHECK: mulv.b812; CHECK: st.b813; CHECK: .size mulv_b_test814 815define void @mulv_h_test() nounwind {816entry:817 %0 = load <8 x i16>, ptr @llvm_mips_mulv_h_ARG1818 %1 = load <8 x i16>, ptr @llvm_mips_mulv_h_ARG2819 %2 = mul <8 x i16> %0, %1820 store <8 x i16> %2, ptr @llvm_mips_mulv_h_RES821 ret void822}823 824; CHECK: mulv_h_test:825; CHECK: ld.h826; CHECK: ld.h827; CHECK: mulv.h828; CHECK: st.h829; CHECK: .size mulv_h_test830 831define void @mulv_w_test() nounwind {832entry:833 %0 = load <4 x i32>, ptr @llvm_mips_mulv_w_ARG1834 %1 = load <4 x i32>, ptr @llvm_mips_mulv_w_ARG2835 %2 = mul <4 x i32> %0, %1836 store <4 x i32> %2, ptr @llvm_mips_mulv_w_RES837 ret void838}839 840; CHECK: mulv_w_test:841; CHECK: ld.w842; CHECK: ld.w843; CHECK: mulv.w844; CHECK: st.w845; CHECK: .size mulv_w_test846 847define void @mulv_d_test() nounwind {848entry:849 %0 = load <2 x i64>, ptr @llvm_mips_mulv_d_ARG1850 %1 = load <2 x i64>, ptr @llvm_mips_mulv_d_ARG2851 %2 = mul <2 x i64> %0, %1852 store <2 x i64> %2, ptr @llvm_mips_mulv_d_RES853 ret void854}855 856; CHECK: mulv_d_test:857; CHECK: ld.d858; CHECK: ld.d859; CHECK: mulv.d860; CHECK: st.d861; CHECK: .size mulv_d_test862;863