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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'p'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_pckev_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_pckev_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_pckev_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_pckev_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.pckev.b(<16 x i8> %0, <16 x i8> %1)16 store <16 x i8> %2, ptr @llvm_mips_pckev_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.pckev.b(<16 x i8>, <16 x i8>) nounwind21 22; CHECK: llvm_mips_pckev_b_test:23; CHECK: ld.b24; CHECK: ld.b25; CHECK: pckev.b26; CHECK: st.b27; CHECK: .size llvm_mips_pckev_b_test28;29@llvm_mips_pckev_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_pckev_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1631@llvm_mips_pckev_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1632 33define void @llvm_mips_pckev_h_test() nounwind {34entry:35 %0 = load <8 x i16>, ptr @llvm_mips_pckev_h_ARG136 %1 = load <8 x i16>, ptr @llvm_mips_pckev_h_ARG237 %2 = tail call <8 x i16> @llvm.mips.pckev.h(<8 x i16> %0, <8 x i16> %1)38 store <8 x i16> %2, ptr @llvm_mips_pckev_h_RES39 ret void40}41 42declare <8 x i16> @llvm.mips.pckev.h(<8 x i16>, <8 x i16>) nounwind43 44; CHECK: llvm_mips_pckev_h_test:45; CHECK: ld.h46; CHECK: ld.h47; CHECK: pckev.h48; CHECK: st.h49; CHECK: .size llvm_mips_pckev_h_test50;51@llvm_mips_pckev_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1652@llvm_mips_pckev_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1653@llvm_mips_pckev_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_pckev_w_test() nounwind {56entry:57 %0 = load <4 x i32>, ptr @llvm_mips_pckev_w_ARG158 %1 = load <4 x i32>, ptr @llvm_mips_pckev_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.pckev.w(<4 x i32> %0, <4 x i32> %1)60 store <4 x i32> %2, ptr @llvm_mips_pckev_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.pckev.w(<4 x i32>, <4 x i32>) nounwind65 66; CHECK: llvm_mips_pckev_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: pckev.w70; CHECK: st.w71; CHECK: .size llvm_mips_pckev_w_test72;73@llvm_mips_pckev_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1674@llvm_mips_pckev_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1675@llvm_mips_pckev_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_pckev_d_test() nounwind {78entry:79 %0 = load <2 x i64>, ptr @llvm_mips_pckev_d_ARG180 %1 = load <2 x i64>, ptr @llvm_mips_pckev_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.pckev.d(<2 x i64> %0, <2 x i64> %1)82 store <2 x i64> %2, ptr @llvm_mips_pckev_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.pckev.d(<2 x i64>, <2 x i64>) nounwind87 88; CHECK: llvm_mips_pckev_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: pckev.d92; CHECK: st.d93; CHECK: .size llvm_mips_pckev_d_test94;95@llvm_mips_pckod_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1696@llvm_mips_pckod_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1697@llvm_mips_pckod_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1698 99define void @llvm_mips_pckod_b_test() nounwind {100entry:101 %0 = load <16 x i8>, ptr @llvm_mips_pckod_b_ARG1102 %1 = load <16 x i8>, ptr @llvm_mips_pckod_b_ARG2103 %2 = tail call <16 x i8> @llvm.mips.pckod.b(<16 x i8> %0, <16 x i8> %1)104 store <16 x i8> %2, ptr @llvm_mips_pckod_b_RES105 ret void106}107 108declare <16 x i8> @llvm.mips.pckod.b(<16 x i8>, <16 x i8>) nounwind109 110; CHECK: llvm_mips_pckod_b_test:111; CHECK: ld.b112; CHECK: ld.b113; CHECK: pckod.b114; CHECK: st.b115; CHECK: .size llvm_mips_pckod_b_test116;117@llvm_mips_pckod_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16118@llvm_mips_pckod_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16119@llvm_mips_pckod_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16120 121define void @llvm_mips_pckod_h_test() nounwind {122entry:123 %0 = load <8 x i16>, ptr @llvm_mips_pckod_h_ARG1124 %1 = load <8 x i16>, ptr @llvm_mips_pckod_h_ARG2125 %2 = tail call <8 x i16> @llvm.mips.pckod.h(<8 x i16> %0, <8 x i16> %1)126 store <8 x i16> %2, ptr @llvm_mips_pckod_h_RES127 ret void128}129 130declare <8 x i16> @llvm.mips.pckod.h(<8 x i16>, <8 x i16>) nounwind131 132; CHECK: llvm_mips_pckod_h_test:133; CHECK: ld.h134; CHECK: ld.h135; CHECK: pckod.h136; CHECK: st.h137; CHECK: .size llvm_mips_pckod_h_test138;139@llvm_mips_pckod_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16140@llvm_mips_pckod_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16141@llvm_mips_pckod_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16142 143define void @llvm_mips_pckod_w_test() nounwind {144entry:145 %0 = load <4 x i32>, ptr @llvm_mips_pckod_w_ARG1146 %1 = load <4 x i32>, ptr @llvm_mips_pckod_w_ARG2147 %2 = tail call <4 x i32> @llvm.mips.pckod.w(<4 x i32> %0, <4 x i32> %1)148 store <4 x i32> %2, ptr @llvm_mips_pckod_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.pckod.w(<4 x i32>, <4 x i32>) nounwind153 154; CHECK: llvm_mips_pckod_w_test:155; CHECK: ld.w156; CHECK: ld.w157; CHECK: pckod.w158; CHECK: st.w159; CHECK: .size llvm_mips_pckod_w_test160;161@llvm_mips_pckod_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16162@llvm_mips_pckod_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16163@llvm_mips_pckod_d_RES = global <2 x i64> <i64 0, i64 0>, align 16164 165define void @llvm_mips_pckod_d_test() nounwind {166entry:167 %0 = load <2 x i64>, ptr @llvm_mips_pckod_d_ARG1168 %1 = load <2 x i64>, ptr @llvm_mips_pckod_d_ARG2169 %2 = tail call <2 x i64> @llvm.mips.pckod.d(<2 x i64> %0, <2 x i64> %1)170 store <2 x i64> %2, ptr @llvm_mips_pckod_d_RES171 ret void172}173 174declare <2 x i64> @llvm.mips.pckod.d(<2 x i64>, <2 x i64>) nounwind175 176; CHECK: llvm_mips_pckod_d_test:177; CHECK: ld.d178; CHECK: ld.d179; CHECK: pckod.d180; CHECK: st.d181; CHECK: .size llvm_mips_pckod_d_test182;183