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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 's'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6 7@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 169@llvm_mips_sld_b_ARG3 = global i32 10, align 1610@llvm_mips_sld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1611 12define void @llvm_mips_sld_b_test() nounwind {13entry:14 %0 = load <16 x i8>, ptr @llvm_mips_sld_b_ARG115 %1 = load <16 x i8>, ptr @llvm_mips_sld_b_ARG216 %2 = load i32, ptr @llvm_mips_sld_b_ARG317 %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2)18 store <16 x i8> %3, ptr @llvm_mips_sld_b_RES19 ret void20}21 22declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind23 24; CHECK: llvm_mips_sld_b_test:25; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_b_ARG1)26; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_b_ARG2)27; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_b_ARG3)28; CHECK-DAG: ld.b [[WD:\$w[0-9]+]], 0([[R1]])29; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R2]])30; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])31; CHECK-DAG: sld.b [[WD]], [[WS]][[[RT]]]32; CHECK-DAG: st.b [[WD]]33; CHECK: .size llvm_mips_sld_b_test34;35@llvm_mips_sld_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1636@llvm_mips_sld_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1637@llvm_mips_sld_h_ARG3 = global i32 10, align 1638@llvm_mips_sld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1639 40define void @llvm_mips_sld_h_test() nounwind {41entry:42 %0 = load <8 x i16>, ptr @llvm_mips_sld_h_ARG143 %1 = load <8 x i16>, ptr @llvm_mips_sld_h_ARG244 %2 = load i32, ptr @llvm_mips_sld_h_ARG345 %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2)46 store <8 x i16> %3, ptr @llvm_mips_sld_h_RES47 ret void48}49 50declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind51 52; CHECK: llvm_mips_sld_h_test:53; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_h_ARG1)54; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2)55; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_h_ARG3)56; CHECK-DAG: ld.h [[WD:\$w[0-9]+]], 0([[R1]])57; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R2]])58; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])59; CHECK-DAG: sld.h [[WD]], [[WS]][[[RT]]]60; CHECK-DAG: st.h [[WD]]61; CHECK: .size llvm_mips_sld_h_test62;63@llvm_mips_sld_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1664@llvm_mips_sld_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1665@llvm_mips_sld_w_ARG3 = global i32 10, align 1666@llvm_mips_sld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1667 68define void @llvm_mips_sld_w_test() nounwind {69entry:70 %0 = load <4 x i32>, ptr @llvm_mips_sld_w_ARG171 %1 = load <4 x i32>, ptr @llvm_mips_sld_w_ARG272 %2 = load i32, ptr @llvm_mips_sld_w_ARG373 %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2)74 store <4 x i32> %3, ptr @llvm_mips_sld_w_RES75 ret void76}77 78declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind79 80; CHECK: llvm_mips_sld_w_test:81; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_w_ARG1)82; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2)83; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_w_ARG3)84; CHECK-DAG: ld.w [[WD:\$w[0-9]+]], 0([[R1]])85; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R2]])86; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])87; CHECK-DAG: sld.w [[WD]], [[WS]][[[RT]]]88; CHECK-DAG: st.w [[WD]]89; CHECK: .size llvm_mips_sld_w_test90;91@llvm_mips_sld_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1692@llvm_mips_sld_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 1693@llvm_mips_sld_d_ARG3 = global i32 10, align 1694@llvm_mips_sld_d_RES = global <2 x i64> <i64 0, i64 0>, align 1695 96define void @llvm_mips_sld_d_test() nounwind {97entry:98 %0 = load <2 x i64>, ptr @llvm_mips_sld_d_ARG199 %1 = load <2 x i64>, ptr @llvm_mips_sld_d_ARG2100 %2 = load i32, ptr @llvm_mips_sld_d_ARG3101 %3 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1, i32 %2)102 store <2 x i64> %3, ptr @llvm_mips_sld_d_RES103 ret void104}105 106declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>, i32) nounwind107 108; CHECK: llvm_mips_sld_d_test:109; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_d_ARG1)110; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2)111; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_sld_d_ARG3)112; CHECK-DAG: ld.d [[WD:\$w[0-9]+]], 0([[R1]])113; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R2]])114; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R3]])115; CHECK-DAG: sld.d [[WD]], [[WS]][[[RT]]]116; CHECK-DAG: st.d [[WD]]117; CHECK: .size llvm_mips_sld_d_test118;119@llvm_mips_sll_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16120@llvm_mips_sll_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16121@llvm_mips_sll_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16122 123define void @llvm_mips_sll_b_test() nounwind {124entry:125 %0 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG1126 %1 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG2127 %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1)128 store <16 x i8> %2, ptr @llvm_mips_sll_b_RES129 ret void130}131 132declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind133 134; CHECK: llvm_mips_sll_b_test:135; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1)136; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2)137; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])138; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])139; CHECK-DAG: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]140; CHECK-DAG: st.b [[WD]]141; CHECK: .size llvm_mips_sll_b_test142;143@llvm_mips_sll_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16144@llvm_mips_sll_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16145@llvm_mips_sll_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16146 147define void @llvm_mips_sll_h_test() nounwind {148entry:149 %0 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG1150 %1 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG2151 %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1)152 store <8 x i16> %2, ptr @llvm_mips_sll_h_RES153 ret void154}155 156declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind157 158; CHECK: llvm_mips_sll_h_test:159; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1)160; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2)161; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])162; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])163; CHECK-DAG: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]164; CHECK-DAG: st.h [[WD]]165; CHECK: .size llvm_mips_sll_h_test166;167@llvm_mips_sll_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16168@llvm_mips_sll_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16169@llvm_mips_sll_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16170 171define void @llvm_mips_sll_w_test() nounwind {172entry:173 %0 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG1174 %1 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG2175 %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1)176 store <4 x i32> %2, ptr @llvm_mips_sll_w_RES177 ret void178}179 180declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind181 182; CHECK: llvm_mips_sll_w_test:183; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1)184; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2)185; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])186; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])187; CHECK-DAG: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]188; CHECK-DAG: st.w [[WD]]189; CHECK: .size llvm_mips_sll_w_test190;191@llvm_mips_sll_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16192@llvm_mips_sll_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16193@llvm_mips_sll_d_RES = global <2 x i64> <i64 0, i64 0>, align 16194 195define void @llvm_mips_sll_d_test() nounwind {196entry:197 %0 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG1198 %1 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG2199 %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1)200 store <2 x i64> %2, ptr @llvm_mips_sll_d_RES201 ret void202}203 204declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind205 206; CHECK: llvm_mips_sll_d_test:207; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1)208; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2)209; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])210; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])211; CHECK-DAG: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]212; CHECK-DAG: st.d [[WD]]213; CHECK: .size llvm_mips_sll_d_test214 215define void @sll_b_test() nounwind {216entry:217 %0 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG1218 %1 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG2219 %2 = shl <16 x i8> %0, %1220 store <16 x i8> %2, ptr @llvm_mips_sll_b_RES221 ret void222}223 224; CHECK: sll_b_test:225; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1)226; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2)227; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])228; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])229; CHECK-DAG: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]230; CHECK-DAG: st.b [[WD]]231; CHECK: .size sll_b_test232 233define void @sll_h_test() nounwind {234entry:235 %0 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG1236 %1 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG2237 %2 = shl <8 x i16> %0, %1238 store <8 x i16> %2, ptr @llvm_mips_sll_h_RES239 ret void240}241 242; CHECK: sll_h_test:243; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1)244; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2)245; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])246; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])247; CHECK-DAG: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]248; CHECK-DAG: st.h [[WD]]249; CHECK: .size sll_h_test250 251define void @sll_w_test() nounwind {252entry:253 %0 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG1254 %1 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG2255 %2 = shl <4 x i32> %0, %1256 store <4 x i32> %2, ptr @llvm_mips_sll_w_RES257 ret void258}259 260; CHECK: sll_w_test:261; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1)262; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2)263; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])264; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])265; CHECK-DAG: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]266; CHECK-DAG: st.w [[WD]]267; CHECK: .size sll_w_test268 269define void @sll_d_test() nounwind {270entry:271 %0 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG1272 %1 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG2273 %2 = shl <2 x i64> %0, %1274 store <2 x i64> %2, ptr @llvm_mips_sll_d_RES275 ret void276}277 278; CHECK: sll_d_test:279; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1)280; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2)281; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])282; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])283; CHECK-DAG: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]284; CHECK-DAG: st.d [[WD]]285; CHECK: .size sll_d_test286;287@llvm_mips_sra_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16288@llvm_mips_sra_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16289@llvm_mips_sra_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16290 291define void @llvm_mips_sra_b_test() nounwind {292entry:293 %0 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG1294 %1 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG2295 %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1)296 store <16 x i8> %2, ptr @llvm_mips_sra_b_RES297 ret void298}299 300declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind301 302; CHECK: llvm_mips_sra_b_test:303; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1)304; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2)305; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])306; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])307; CHECK-DAG: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]308; CHECK-DAG: st.b [[WD]]309; CHECK: .size llvm_mips_sra_b_test310;311@llvm_mips_sra_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16312@llvm_mips_sra_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16313@llvm_mips_sra_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16314 315define void @llvm_mips_sra_h_test() nounwind {316entry:317 %0 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG1318 %1 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG2319 %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1)320 store <8 x i16> %2, ptr @llvm_mips_sra_h_RES321 ret void322}323 324declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind325 326; CHECK: llvm_mips_sra_h_test:327; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1)328; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2)329; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])330; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])331; CHECK-DAG: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]332; CHECK-DAG: st.h [[WD]]333; CHECK: .size llvm_mips_sra_h_test334;335@llvm_mips_sra_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16336@llvm_mips_sra_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16337@llvm_mips_sra_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16338 339define void @llvm_mips_sra_w_test() nounwind {340entry:341 %0 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG1342 %1 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG2343 %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1)344 store <4 x i32> %2, ptr @llvm_mips_sra_w_RES345 ret void346}347 348declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind349 350; CHECK: llvm_mips_sra_w_test:351; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1)352; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2)353; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])354; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])355; CHECK-DAG: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]356; CHECK-DAG: st.w [[WD]]357; CHECK: .size llvm_mips_sra_w_test358;359@llvm_mips_sra_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16360@llvm_mips_sra_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16361@llvm_mips_sra_d_RES = global <2 x i64> <i64 0, i64 0>, align 16362 363define void @llvm_mips_sra_d_test() nounwind {364entry:365 %0 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG1366 %1 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG2367 %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1)368 store <2 x i64> %2, ptr @llvm_mips_sra_d_RES369 ret void370}371 372declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind373 374; CHECK: llvm_mips_sra_d_test:375; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1)376; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2)377; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])378; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])379; CHECK-DAG: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]380; CHECK-DAG: st.d [[WD]]381; CHECK: .size llvm_mips_sra_d_test382;383 384define void @sra_b_test() nounwind {385entry:386 %0 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG1387 %1 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG2388 %2 = ashr <16 x i8> %0, %1389 store <16 x i8> %2, ptr @llvm_mips_sra_b_RES390 ret void391}392 393; CHECK: sra_b_test:394; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1)395; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2)396; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])397; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])398; CHECK-DAG: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]399; CHECK-DAG: st.b [[WD]]400; CHECK: .size sra_b_test401 402define void @sra_h_test() nounwind {403entry:404 %0 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG1405 %1 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG2406 %2 = ashr <8 x i16> %0, %1407 store <8 x i16> %2, ptr @llvm_mips_sra_h_RES408 ret void409}410 411; CHECK: sra_h_test:412; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1)413; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2)414; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])415; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])416; CHECK-DAG: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]417; CHECK-DAG: st.h [[WD]]418; CHECK: .size sra_h_test419 420define void @sra_w_test() nounwind {421entry:422 %0 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG1423 %1 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG2424 %2 = ashr <4 x i32> %0, %1425 store <4 x i32> %2, ptr @llvm_mips_sra_w_RES426 ret void427}428 429; CHECK: sra_w_test:430; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1)431; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2)432; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])433; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])434; CHECK-DAG: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]435; CHECK-DAG: st.w [[WD]]436; CHECK: .size sra_w_test437 438define void @sra_d_test() nounwind {439entry:440 %0 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG1441 %1 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG2442 %2 = ashr <2 x i64> %0, %1443 store <2 x i64> %2, ptr @llvm_mips_sra_d_RES444 ret void445}446 447; CHECK: sra_d_test:448; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1)449; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2)450; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])451; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])452; CHECK-DAG: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]453; CHECK-DAG: st.d [[WD]]454; CHECK: .size sra_d_test455 456@llvm_mips_srar_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16457@llvm_mips_srar_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16458@llvm_mips_srar_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16459 460define void @llvm_mips_srar_b_test() nounwind {461entry:462 %0 = load <16 x i8>, ptr @llvm_mips_srar_b_ARG1463 %1 = load <16 x i8>, ptr @llvm_mips_srar_b_ARG2464 %2 = tail call <16 x i8> @llvm.mips.srar.b(<16 x i8> %0, <16 x i8> %1)465 store <16 x i8> %2, ptr @llvm_mips_srar_b_RES466 ret void467}468 469declare <16 x i8> @llvm.mips.srar.b(<16 x i8>, <16 x i8>) nounwind470 471; CHECK: llvm_mips_srar_b_test:472; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_b_ARG1)473; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_b_ARG2)474; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])475; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])476; CHECK-DAG: srar.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]477; CHECK-DAG: st.b [[WD]]478; CHECK: .size llvm_mips_srar_b_test479;480@llvm_mips_srar_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16481@llvm_mips_srar_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16482@llvm_mips_srar_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16483 484define void @llvm_mips_srar_h_test() nounwind {485entry:486 %0 = load <8 x i16>, ptr @llvm_mips_srar_h_ARG1487 %1 = load <8 x i16>, ptr @llvm_mips_srar_h_ARG2488 %2 = tail call <8 x i16> @llvm.mips.srar.h(<8 x i16> %0, <8 x i16> %1)489 store <8 x i16> %2, ptr @llvm_mips_srar_h_RES490 ret void491}492 493declare <8 x i16> @llvm.mips.srar.h(<8 x i16>, <8 x i16>) nounwind494 495; CHECK: llvm_mips_srar_h_test:496; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_h_ARG1)497; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_h_ARG2)498; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])499; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])500; CHECK-DAG: srar.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]501; CHECK-DAG: st.h [[WD]]502; CHECK: .size llvm_mips_srar_h_test503;504@llvm_mips_srar_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16505@llvm_mips_srar_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16506@llvm_mips_srar_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16507 508define void @llvm_mips_srar_w_test() nounwind {509entry:510 %0 = load <4 x i32>, ptr @llvm_mips_srar_w_ARG1511 %1 = load <4 x i32>, ptr @llvm_mips_srar_w_ARG2512 %2 = tail call <4 x i32> @llvm.mips.srar.w(<4 x i32> %0, <4 x i32> %1)513 store <4 x i32> %2, ptr @llvm_mips_srar_w_RES514 ret void515}516 517declare <4 x i32> @llvm.mips.srar.w(<4 x i32>, <4 x i32>) nounwind518 519; CHECK: llvm_mips_srar_w_test:520; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_w_ARG1)521; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_w_ARG2)522; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])523; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])524; CHECK-DAG: srar.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]525; CHECK-DAG: st.w [[WD]]526; CHECK: .size llvm_mips_srar_w_test527;528@llvm_mips_srar_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16529@llvm_mips_srar_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16530@llvm_mips_srar_d_RES = global <2 x i64> <i64 0, i64 0>, align 16531 532define void @llvm_mips_srar_d_test() nounwind {533entry:534 %0 = load <2 x i64>, ptr @llvm_mips_srar_d_ARG1535 %1 = load <2 x i64>, ptr @llvm_mips_srar_d_ARG2536 %2 = tail call <2 x i64> @llvm.mips.srar.d(<2 x i64> %0, <2 x i64> %1)537 store <2 x i64> %2, ptr @llvm_mips_srar_d_RES538 ret void539}540 541declare <2 x i64> @llvm.mips.srar.d(<2 x i64>, <2 x i64>) nounwind542 543; CHECK: llvm_mips_srar_d_test:544; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srar_d_ARG1)545; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srar_d_ARG2)546; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])547; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])548; CHECK-DAG: srar.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]549; CHECK-DAG: st.d [[WD]]550; CHECK: .size llvm_mips_srar_d_test551;552@llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16553@llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16554@llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16555 556define void @llvm_mips_srl_b_test() nounwind {557entry:558 %0 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG1559 %1 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG2560 %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1)561 store <16 x i8> %2, ptr @llvm_mips_srl_b_RES562 ret void563}564 565declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind566 567; CHECK: llvm_mips_srl_b_test:568; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1)569; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2)570; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])571; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])572; CHECK-DAG: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]573; CHECK-DAG: st.b [[WD]]574; CHECK: .size llvm_mips_srl_b_test575;576@llvm_mips_srl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16577@llvm_mips_srl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16578@llvm_mips_srl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16579 580define void @llvm_mips_srl_h_test() nounwind {581entry:582 %0 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG1583 %1 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG2584 %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1)585 store <8 x i16> %2, ptr @llvm_mips_srl_h_RES586 ret void587}588 589declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind590 591; CHECK: llvm_mips_srl_h_test:592; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1)593; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2)594; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])595; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])596; CHECK-DAG: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]597; CHECK-DAG: st.h [[WD]]598; CHECK: .size llvm_mips_srl_h_test599;600@llvm_mips_srl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16601@llvm_mips_srl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16602@llvm_mips_srl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16603 604define void @llvm_mips_srl_w_test() nounwind {605entry:606 %0 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG1607 %1 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG2608 %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1)609 store <4 x i32> %2, ptr @llvm_mips_srl_w_RES610 ret void611}612 613declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind614 615; CHECK: llvm_mips_srl_w_test:616; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1)617; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2)618; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])619; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])620; CHECK-DAG: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]621; CHECK-DAG: st.w [[WD]]622; CHECK: .size llvm_mips_srl_w_test623;624@llvm_mips_srl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16625@llvm_mips_srl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16626@llvm_mips_srl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16627 628define void @llvm_mips_srl_d_test() nounwind {629entry:630 %0 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG1631 %1 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG2632 %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1)633 store <2 x i64> %2, ptr @llvm_mips_srl_d_RES634 ret void635}636 637declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind638 639; CHECK: llvm_mips_srl_d_test:640; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1)641; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2)642; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])643; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])644; CHECK-DAG: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]645; CHECK-DAG: st.d [[WD]]646; CHECK: .size llvm_mips_srl_d_test647;648@llvm_mips_srlr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16649@llvm_mips_srlr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16650@llvm_mips_srlr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16651 652define void @llvm_mips_srlr_b_test() nounwind {653entry:654 %0 = load <16 x i8>, ptr @llvm_mips_srlr_b_ARG1655 %1 = load <16 x i8>, ptr @llvm_mips_srlr_b_ARG2656 %2 = tail call <16 x i8> @llvm.mips.srlr.b(<16 x i8> %0, <16 x i8> %1)657 store <16 x i8> %2, ptr @llvm_mips_srlr_b_RES658 ret void659}660 661declare <16 x i8> @llvm.mips.srlr.b(<16 x i8>, <16 x i8>) nounwind662 663; CHECK: llvm_mips_srlr_b_test:664; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_b_ARG1)665; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_b_ARG2)666; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])667; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])668; CHECK-DAG: srlr.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]669; CHECK-DAG: st.b [[WD]]670; CHECK: .size llvm_mips_srlr_b_test671;672@llvm_mips_srlr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16673@llvm_mips_srlr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16674@llvm_mips_srlr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16675 676define void @llvm_mips_srlr_h_test() nounwind {677entry:678 %0 = load <8 x i16>, ptr @llvm_mips_srlr_h_ARG1679 %1 = load <8 x i16>, ptr @llvm_mips_srlr_h_ARG2680 %2 = tail call <8 x i16> @llvm.mips.srlr.h(<8 x i16> %0, <8 x i16> %1)681 store <8 x i16> %2, ptr @llvm_mips_srlr_h_RES682 ret void683}684 685declare <8 x i16> @llvm.mips.srlr.h(<8 x i16>, <8 x i16>) nounwind686 687; CHECK: llvm_mips_srlr_h_test:688; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_h_ARG1)689; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_h_ARG2)690; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])691; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])692; CHECK-DAG: srlr.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]693; CHECK-DAG: st.h [[WD]]694; CHECK: .size llvm_mips_srlr_h_test695;696@llvm_mips_srlr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16697@llvm_mips_srlr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16698@llvm_mips_srlr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16699 700define void @llvm_mips_srlr_w_test() nounwind {701entry:702 %0 = load <4 x i32>, ptr @llvm_mips_srlr_w_ARG1703 %1 = load <4 x i32>, ptr @llvm_mips_srlr_w_ARG2704 %2 = tail call <4 x i32> @llvm.mips.srlr.w(<4 x i32> %0, <4 x i32> %1)705 store <4 x i32> %2, ptr @llvm_mips_srlr_w_RES706 ret void707}708 709declare <4 x i32> @llvm.mips.srlr.w(<4 x i32>, <4 x i32>) nounwind710 711; CHECK: llvm_mips_srlr_w_test:712; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_w_ARG1)713; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_w_ARG2)714; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])715; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])716; CHECK-DAG: srlr.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]717; CHECK-DAG: st.w [[WD]]718; CHECK: .size llvm_mips_srlr_w_test719;720@llvm_mips_srlr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16721@llvm_mips_srlr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16722@llvm_mips_srlr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16723 724define void @llvm_mips_srlr_d_test() nounwind {725entry:726 %0 = load <2 x i64>, ptr @llvm_mips_srlr_d_ARG1727 %1 = load <2 x i64>, ptr @llvm_mips_srlr_d_ARG2728 %2 = tail call <2 x i64> @llvm.mips.srlr.d(<2 x i64> %0, <2 x i64> %1)729 store <2 x i64> %2, ptr @llvm_mips_srlr_d_RES730 ret void731}732 733declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind734 735; CHECK: llvm_mips_srlr_d_test:736; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srlr_d_ARG1)737; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srlr_d_ARG2)738; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])739; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])740; CHECK-DAG: srlr.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]741; CHECK-DAG: st.d [[WD]]742; CHECK: .size llvm_mips_srlr_d_test743;744 745define void @srl_b_test() nounwind {746entry:747 %0 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG1748 %1 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG2749 %2 = lshr <16 x i8> %0, %1750 store <16 x i8> %2, ptr @llvm_mips_srl_b_RES751 ret void752}753 754; CHECK: srl_b_test:755; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1)756; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2)757; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])758; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])759; CHECK-DAG: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]760; CHECK-DAG: st.b [[WD]]761; CHECK: .size srl_b_test762 763define void @srl_h_test() nounwind {764entry:765 %0 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG1766 %1 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG2767 %2 = lshr <8 x i16> %0, %1768 store <8 x i16> %2, ptr @llvm_mips_srl_h_RES769 ret void770}771 772; CHECK: srl_h_test:773; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1)774; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2)775; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])776; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])777; CHECK-DAG: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]778; CHECK-DAG: st.h [[WD]]779; CHECK: .size srl_h_test780 781define void @srl_w_test() nounwind {782entry:783 %0 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG1784 %1 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG2785 %2 = lshr <4 x i32> %0, %1786 store <4 x i32> %2, ptr @llvm_mips_srl_w_RES787 ret void788}789 790; CHECK: srl_w_test:791; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1)792; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2)793; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])794; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])795; CHECK-DAG: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]796; CHECK-DAG: st.w [[WD]]797; CHECK: .size srl_w_test798 799define void @srl_d_test() nounwind {800entry:801 %0 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG1802 %1 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG2803 %2 = lshr <2 x i64> %0, %1804 store <2 x i64> %2, ptr @llvm_mips_srl_d_RES805 ret void806}807 808; CHECK: srl_d_test:809; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1)810; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2)811; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])812; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])813; CHECK-DAG: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]814; CHECK-DAG: st.d [[WD]]815; CHECK: .size srl_d_test816 817@llvm_mips_subs_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16818@llvm_mips_subs_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16819@llvm_mips_subs_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16820 821define void @llvm_mips_subs_s_b_test() nounwind {822entry:823 %0 = load <16 x i8>, ptr @llvm_mips_subs_s_b_ARG1824 %1 = load <16 x i8>, ptr @llvm_mips_subs_s_b_ARG2825 %2 = tail call <16 x i8> @llvm.mips.subs.s.b(<16 x i8> %0, <16 x i8> %1)826 store <16 x i8> %2, ptr @llvm_mips_subs_s_b_RES827 ret void828}829 830declare <16 x i8> @llvm.mips.subs.s.b(<16 x i8>, <16 x i8>) nounwind831 832; CHECK: llvm_mips_subs_s_b_test:833; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_b_ARG1)834; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_b_ARG2)835; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])836; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])837; CHECK-DAG: subs_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]838; CHECK-DAG: st.b [[WD]]839; CHECK: .size llvm_mips_subs_s_b_test840;841@llvm_mips_subs_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16842@llvm_mips_subs_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16843@llvm_mips_subs_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16844 845define void @llvm_mips_subs_s_h_test() nounwind {846entry:847 %0 = load <8 x i16>, ptr @llvm_mips_subs_s_h_ARG1848 %1 = load <8 x i16>, ptr @llvm_mips_subs_s_h_ARG2849 %2 = tail call <8 x i16> @llvm.mips.subs.s.h(<8 x i16> %0, <8 x i16> %1)850 store <8 x i16> %2, ptr @llvm_mips_subs_s_h_RES851 ret void852}853 854declare <8 x i16> @llvm.mips.subs.s.h(<8 x i16>, <8 x i16>) nounwind855 856; CHECK: llvm_mips_subs_s_h_test:857; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_h_ARG1)858; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_h_ARG2)859; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])860; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])861; CHECK-DAG: subs_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]862; CHECK-DAG: st.h [[WD]]863; CHECK: .size llvm_mips_subs_s_h_test864;865@llvm_mips_subs_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16866@llvm_mips_subs_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16867@llvm_mips_subs_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16868 869define void @llvm_mips_subs_s_w_test() nounwind {870entry:871 %0 = load <4 x i32>, ptr @llvm_mips_subs_s_w_ARG1872 %1 = load <4 x i32>, ptr @llvm_mips_subs_s_w_ARG2873 %2 = tail call <4 x i32> @llvm.mips.subs.s.w(<4 x i32> %0, <4 x i32> %1)874 store <4 x i32> %2, ptr @llvm_mips_subs_s_w_RES875 ret void876}877 878declare <4 x i32> @llvm.mips.subs.s.w(<4 x i32>, <4 x i32>) nounwind879 880; CHECK: llvm_mips_subs_s_w_test:881; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_w_ARG1)882; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_w_ARG2)883; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])884; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])885; CHECK-DAG: subs_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]886; CHECK-DAG: st.w [[WD]]887; CHECK: .size llvm_mips_subs_s_w_test888;889@llvm_mips_subs_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16890@llvm_mips_subs_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16891@llvm_mips_subs_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16892 893define void @llvm_mips_subs_s_d_test() nounwind {894entry:895 %0 = load <2 x i64>, ptr @llvm_mips_subs_s_d_ARG1896 %1 = load <2 x i64>, ptr @llvm_mips_subs_s_d_ARG2897 %2 = tail call <2 x i64> @llvm.mips.subs.s.d(<2 x i64> %0, <2 x i64> %1)898 store <2 x i64> %2, ptr @llvm_mips_subs_s_d_RES899 ret void900}901 902declare <2 x i64> @llvm.mips.subs.s.d(<2 x i64>, <2 x i64>) nounwind903 904; CHECK: llvm_mips_subs_s_d_test:905; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_s_d_ARG1)906; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_s_d_ARG2)907; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])908; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])909; CHECK-DAG: subs_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]910; CHECK-DAG: st.d [[WD]]911; CHECK: .size llvm_mips_subs_s_d_test912;913@llvm_mips_subs_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16914@llvm_mips_subs_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16915@llvm_mips_subs_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16916 917define void @llvm_mips_subs_u_b_test() nounwind {918entry:919 %0 = load <16 x i8>, ptr @llvm_mips_subs_u_b_ARG1920 %1 = load <16 x i8>, ptr @llvm_mips_subs_u_b_ARG2921 %2 = tail call <16 x i8> @llvm.mips.subs.u.b(<16 x i8> %0, <16 x i8> %1)922 store <16 x i8> %2, ptr @llvm_mips_subs_u_b_RES923 ret void924}925 926declare <16 x i8> @llvm.mips.subs.u.b(<16 x i8>, <16 x i8>) nounwind927 928; CHECK: llvm_mips_subs_u_b_test:929; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_b_ARG1)930; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_b_ARG2)931; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])932; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])933; CHECK-DAG: subs_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]934; CHECK-DAG: st.b [[WD]]935; CHECK: .size llvm_mips_subs_u_b_test936;937@llvm_mips_subs_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16938@llvm_mips_subs_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16939@llvm_mips_subs_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16940 941define void @llvm_mips_subs_u_h_test() nounwind {942entry:943 %0 = load <8 x i16>, ptr @llvm_mips_subs_u_h_ARG1944 %1 = load <8 x i16>, ptr @llvm_mips_subs_u_h_ARG2945 %2 = tail call <8 x i16> @llvm.mips.subs.u.h(<8 x i16> %0, <8 x i16> %1)946 store <8 x i16> %2, ptr @llvm_mips_subs_u_h_RES947 ret void948}949 950declare <8 x i16> @llvm.mips.subs.u.h(<8 x i16>, <8 x i16>) nounwind951 952; CHECK: llvm_mips_subs_u_h_test:953; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_h_ARG1)954; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_h_ARG2)955; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])956; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])957; CHECK-DAG: subs_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]958; CHECK-DAG: st.h [[WD]]959; CHECK: .size llvm_mips_subs_u_h_test960;961@llvm_mips_subs_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16962@llvm_mips_subs_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16963@llvm_mips_subs_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16964 965define void @llvm_mips_subs_u_w_test() nounwind {966entry:967 %0 = load <4 x i32>, ptr @llvm_mips_subs_u_w_ARG1968 %1 = load <4 x i32>, ptr @llvm_mips_subs_u_w_ARG2969 %2 = tail call <4 x i32> @llvm.mips.subs.u.w(<4 x i32> %0, <4 x i32> %1)970 store <4 x i32> %2, ptr @llvm_mips_subs_u_w_RES971 ret void972}973 974declare <4 x i32> @llvm.mips.subs.u.w(<4 x i32>, <4 x i32>) nounwind975 976; CHECK: llvm_mips_subs_u_w_test:977; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_w_ARG1)978; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_w_ARG2)979; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])980; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])981; CHECK-DAG: subs_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]982; CHECK-DAG: st.w [[WD]]983; CHECK: .size llvm_mips_subs_u_w_test984;985@llvm_mips_subs_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16986@llvm_mips_subs_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16987@llvm_mips_subs_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16988 989define void @llvm_mips_subs_u_d_test() nounwind {990entry:991 %0 = load <2 x i64>, ptr @llvm_mips_subs_u_d_ARG1992 %1 = load <2 x i64>, ptr @llvm_mips_subs_u_d_ARG2993 %2 = tail call <2 x i64> @llvm.mips.subs.u.d(<2 x i64> %0, <2 x i64> %1)994 store <2 x i64> %2, ptr @llvm_mips_subs_u_d_RES995 ret void996}997 998declare <2 x i64> @llvm.mips.subs.u.d(<2 x i64>, <2 x i64>) nounwind999 1000; CHECK: llvm_mips_subs_u_d_test:1001; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subs_u_d_ARG1)1002; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subs_u_d_ARG2)1003; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1004; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1005; CHECK-DAG: subs_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1006; CHECK-DAG: st.d [[WD]]1007; CHECK: .size llvm_mips_subs_u_d_test1008;1009@llvm_mips_subsus_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 161010@llvm_mips_subsus_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 161011@llvm_mips_subsus_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 161012 1013define void @llvm_mips_subsus_u_b_test() nounwind {1014entry:1015 %0 = load <16 x i8>, ptr @llvm_mips_subsus_u_b_ARG11016 %1 = load <16 x i8>, ptr @llvm_mips_subsus_u_b_ARG21017 %2 = tail call <16 x i8> @llvm.mips.subsus.u.b(<16 x i8> %0, <16 x i8> %1)1018 store <16 x i8> %2, ptr @llvm_mips_subsus_u_b_RES1019 ret void1020}1021 1022declare <16 x i8> @llvm.mips.subsus.u.b(<16 x i8>, <16 x i8>) nounwind1023 1024; CHECK: llvm_mips_subsus_u_b_test:1025; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_b_ARG1)1026; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_b_ARG2)1027; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1028; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1029; CHECK-DAG: subsus_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1030; CHECK-DAG: st.b [[WD]]1031; CHECK: .size llvm_mips_subsus_u_b_test1032;1033@llvm_mips_subsus_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 161034@llvm_mips_subsus_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 161035@llvm_mips_subsus_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 161036 1037define void @llvm_mips_subsus_u_h_test() nounwind {1038entry:1039 %0 = load <8 x i16>, ptr @llvm_mips_subsus_u_h_ARG11040 %1 = load <8 x i16>, ptr @llvm_mips_subsus_u_h_ARG21041 %2 = tail call <8 x i16> @llvm.mips.subsus.u.h(<8 x i16> %0, <8 x i16> %1)1042 store <8 x i16> %2, ptr @llvm_mips_subsus_u_h_RES1043 ret void1044}1045 1046declare <8 x i16> @llvm.mips.subsus.u.h(<8 x i16>, <8 x i16>) nounwind1047 1048; CHECK: llvm_mips_subsus_u_h_test:1049; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_h_ARG1)1050; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_h_ARG2)1051; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1052; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1053; CHECK-DAG: subsus_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1054; CHECK-DAG: st.h [[WD]]1055; CHECK: .size llvm_mips_subsus_u_h_test1056;1057@llvm_mips_subsus_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 161058@llvm_mips_subsus_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 161059@llvm_mips_subsus_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 161060 1061define void @llvm_mips_subsus_u_w_test() nounwind {1062entry:1063 %0 = load <4 x i32>, ptr @llvm_mips_subsus_u_w_ARG11064 %1 = load <4 x i32>, ptr @llvm_mips_subsus_u_w_ARG21065 %2 = tail call <4 x i32> @llvm.mips.subsus.u.w(<4 x i32> %0, <4 x i32> %1)1066 store <4 x i32> %2, ptr @llvm_mips_subsus_u_w_RES1067 ret void1068}1069 1070declare <4 x i32> @llvm.mips.subsus.u.w(<4 x i32>, <4 x i32>) nounwind1071 1072; CHECK: llvm_mips_subsus_u_w_test:1073; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_w_ARG1)1074; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_w_ARG2)1075; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1076; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1077; CHECK-DAG: subsus_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1078; CHECK-DAG: st.w [[WD]]1079; CHECK: .size llvm_mips_subsus_u_w_test1080;1081@llvm_mips_subsus_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 161082@llvm_mips_subsus_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 161083@llvm_mips_subsus_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 161084 1085define void @llvm_mips_subsus_u_d_test() nounwind {1086entry:1087 %0 = load <2 x i64>, ptr @llvm_mips_subsus_u_d_ARG11088 %1 = load <2 x i64>, ptr @llvm_mips_subsus_u_d_ARG21089 %2 = tail call <2 x i64> @llvm.mips.subsus.u.d(<2 x i64> %0, <2 x i64> %1)1090 store <2 x i64> %2, ptr @llvm_mips_subsus_u_d_RES1091 ret void1092}1093 1094declare <2 x i64> @llvm.mips.subsus.u.d(<2 x i64>, <2 x i64>) nounwind1095 1096; CHECK: llvm_mips_subsus_u_d_test:1097; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsus_u_d_ARG1)1098; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsus_u_d_ARG2)1099; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1100; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1101; CHECK-DAG: subsus_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1102; CHECK-DAG: st.d [[WD]]1103; CHECK: .size llvm_mips_subsus_u_d_test1104;1105@llvm_mips_subsuu_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 161106@llvm_mips_subsuu_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 161107@llvm_mips_subsuu_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 161108 1109define void @llvm_mips_subsuu_s_b_test() nounwind {1110entry:1111 %0 = load <16 x i8>, ptr @llvm_mips_subsuu_s_b_ARG11112 %1 = load <16 x i8>, ptr @llvm_mips_subsuu_s_b_ARG21113 %2 = tail call <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8> %0, <16 x i8> %1)1114 store <16 x i8> %2, ptr @llvm_mips_subsuu_s_b_RES1115 ret void1116}1117 1118declare <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8>, <16 x i8>) nounwind1119 1120; CHECK: llvm_mips_subsuu_s_b_test:1121; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_b_ARG1)1122; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_b_ARG2)1123; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1124; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1125; CHECK-DAG: subsuu_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1126; CHECK-DAG: st.b [[WD]]1127; CHECK: .size llvm_mips_subsuu_s_b_test1128;1129@llvm_mips_subsuu_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 161130@llvm_mips_subsuu_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 161131@llvm_mips_subsuu_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 161132 1133define void @llvm_mips_subsuu_s_h_test() nounwind {1134entry:1135 %0 = load <8 x i16>, ptr @llvm_mips_subsuu_s_h_ARG11136 %1 = load <8 x i16>, ptr @llvm_mips_subsuu_s_h_ARG21137 %2 = tail call <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16> %0, <8 x i16> %1)1138 store <8 x i16> %2, ptr @llvm_mips_subsuu_s_h_RES1139 ret void1140}1141 1142declare <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16>, <8 x i16>) nounwind1143 1144; CHECK: llvm_mips_subsuu_s_h_test:1145; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_h_ARG1)1146; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_h_ARG2)1147; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1148; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1149; CHECK-DAG: subsuu_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1150; CHECK-DAG: st.h [[WD]]1151; CHECK: .size llvm_mips_subsuu_s_h_test1152;1153@llvm_mips_subsuu_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 161154@llvm_mips_subsuu_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 161155@llvm_mips_subsuu_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 161156 1157define void @llvm_mips_subsuu_s_w_test() nounwind {1158entry:1159 %0 = load <4 x i32>, ptr @llvm_mips_subsuu_s_w_ARG11160 %1 = load <4 x i32>, ptr @llvm_mips_subsuu_s_w_ARG21161 %2 = tail call <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32> %0, <4 x i32> %1)1162 store <4 x i32> %2, ptr @llvm_mips_subsuu_s_w_RES1163 ret void1164}1165 1166declare <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32>, <4 x i32>) nounwind1167 1168; CHECK: llvm_mips_subsuu_s_w_test:1169; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_w_ARG1)1170; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_w_ARG2)1171; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1172; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1173; CHECK-DAG: subsuu_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1174; CHECK-DAG: st.w [[WD]]1175; CHECK: .size llvm_mips_subsuu_s_w_test1176;1177@llvm_mips_subsuu_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 161178@llvm_mips_subsuu_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 161179@llvm_mips_subsuu_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 161180 1181define void @llvm_mips_subsuu_s_d_test() nounwind {1182entry:1183 %0 = load <2 x i64>, ptr @llvm_mips_subsuu_s_d_ARG11184 %1 = load <2 x i64>, ptr @llvm_mips_subsuu_s_d_ARG21185 %2 = tail call <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64> %0, <2 x i64> %1)1186 store <2 x i64> %2, ptr @llvm_mips_subsuu_s_d_RES1187 ret void1188}1189 1190declare <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64>, <2 x i64>) nounwind1191 1192; CHECK: llvm_mips_subsuu_s_d_test:1193; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subsuu_s_d_ARG1)1194; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subsuu_s_d_ARG2)1195; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1196; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1197; CHECK-DAG: subsuu_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1198; CHECK-DAG: st.d [[WD]]1199; CHECK: .size llvm_mips_subsuu_s_d_test1200;1201@llvm_mips_subv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 161202@llvm_mips_subv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 161203@llvm_mips_subv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 161204 1205define void @llvm_mips_subv_b_test() nounwind {1206entry:1207 %0 = load <16 x i8>, ptr @llvm_mips_subv_b_ARG11208 %1 = load <16 x i8>, ptr @llvm_mips_subv_b_ARG21209 %2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1)1210 store <16 x i8> %2, ptr @llvm_mips_subv_b_RES1211 ret void1212}1213 1214declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>) nounwind1215 1216; CHECK: llvm_mips_subv_b_test:1217; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_b_ARG1)1218; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_b_ARG2)1219; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1220; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1221; CHECK-DAG: subv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1222; CHECK-DAG: st.b [[WD]]1223; CHECK: .size llvm_mips_subv_b_test1224;1225@llvm_mips_subv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 161226@llvm_mips_subv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 161227@llvm_mips_subv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 161228 1229define void @llvm_mips_subv_h_test() nounwind {1230entry:1231 %0 = load <8 x i16>, ptr @llvm_mips_subv_h_ARG11232 %1 = load <8 x i16>, ptr @llvm_mips_subv_h_ARG21233 %2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1)1234 store <8 x i16> %2, ptr @llvm_mips_subv_h_RES1235 ret void1236}1237 1238declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>) nounwind1239 1240; CHECK: llvm_mips_subv_h_test:1241; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_h_ARG1)1242; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_h_ARG2)1243; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1244; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1245; CHECK-DAG: subv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1246; CHECK-DAG: st.h [[WD]]1247; CHECK: .size llvm_mips_subv_h_test1248;1249@llvm_mips_subv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 161250@llvm_mips_subv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 161251@llvm_mips_subv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 161252 1253define void @llvm_mips_subv_w_test() nounwind {1254entry:1255 %0 = load <4 x i32>, ptr @llvm_mips_subv_w_ARG11256 %1 = load <4 x i32>, ptr @llvm_mips_subv_w_ARG21257 %2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1)1258 store <4 x i32> %2, ptr @llvm_mips_subv_w_RES1259 ret void1260}1261 1262declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>) nounwind1263 1264; CHECK: llvm_mips_subv_w_test:1265; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_w_ARG1)1266; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_w_ARG2)1267; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1268; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1269; CHECK-DAG: subv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1270; CHECK-DAG: st.w [[WD]]1271; CHECK: .size llvm_mips_subv_w_test1272;1273@llvm_mips_subv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 161274@llvm_mips_subv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 161275@llvm_mips_subv_d_RES = global <2 x i64> <i64 0, i64 0>, align 161276 1277define void @llvm_mips_subv_d_test() nounwind {1278entry:1279 %0 = load <2 x i64>, ptr @llvm_mips_subv_d_ARG11280 %1 = load <2 x i64>, ptr @llvm_mips_subv_d_ARG21281 %2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1)1282 store <2 x i64> %2, ptr @llvm_mips_subv_d_RES1283 ret void1284}1285 1286declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>) nounwind1287 1288; CHECK: llvm_mips_subv_d_test:1289; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_d_ARG1)1290; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_d_ARG2)1291; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1292; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1293; CHECK-DAG: subv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1294; CHECK-DAG: st.d [[WD]]1295; CHECK: .size llvm_mips_subv_d_test1296;1297 1298define void @subv_b_test() nounwind {1299entry:1300 %0 = load <16 x i8>, ptr @llvm_mips_subv_b_ARG11301 %1 = load <16 x i8>, ptr @llvm_mips_subv_b_ARG21302 %2 = sub <16 x i8> %0, %11303 store <16 x i8> %2, ptr @llvm_mips_subv_b_RES1304 ret void1305}1306 1307; CHECK: subv_b_test:1308; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_b_ARG1)1309; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_b_ARG2)1310; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])1311; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])1312; CHECK-DAG: subv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]1313; CHECK-DAG: st.b [[WD]]1314; CHECK: .size subv_b_test1315 1316define void @subv_h_test() nounwind {1317entry:1318 %0 = load <8 x i16>, ptr @llvm_mips_subv_h_ARG11319 %1 = load <8 x i16>, ptr @llvm_mips_subv_h_ARG21320 %2 = sub <8 x i16> %0, %11321 store <8 x i16> %2, ptr @llvm_mips_subv_h_RES1322 ret void1323}1324 1325; CHECK: subv_h_test:1326; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_h_ARG1)1327; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_h_ARG2)1328; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])1329; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])1330; CHECK-DAG: subv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]1331; CHECK-DAG: st.h [[WD]]1332; CHECK: .size subv_h_test1333 1334define void @subv_w_test() nounwind {1335entry:1336 %0 = load <4 x i32>, ptr @llvm_mips_subv_w_ARG11337 %1 = load <4 x i32>, ptr @llvm_mips_subv_w_ARG21338 %2 = sub <4 x i32> %0, %11339 store <4 x i32> %2, ptr @llvm_mips_subv_w_RES1340 ret void1341}1342 1343; CHECK: subv_w_test:1344; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_w_ARG1)1345; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_w_ARG2)1346; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])1347; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])1348; CHECK-DAG: subv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]1349; CHECK-DAG: st.w [[WD]]1350; CHECK: .size subv_w_test1351 1352define void @subv_d_test() nounwind {1353entry:1354 %0 = load <2 x i64>, ptr @llvm_mips_subv_d_ARG11355 %1 = load <2 x i64>, ptr @llvm_mips_subv_d_ARG21356 %2 = sub <2 x i64> %0, %11357 store <2 x i64> %2, ptr @llvm_mips_subv_d_RES1358 ret void1359}1360 1361; CHECK: subv_d_test:1362; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_subv_d_ARG1)1363; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_subv_d_ARG2)1364; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])1365; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])1366; CHECK-DAG: subv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]1367; CHECK-DAG: st.d [[WD]]1368; CHECK: .size subv_d_test1369;1370