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1; Test the MSA intrinsics that are encoded with the 3R instruction format.2; There are lots of these so this covers those beginning with 'v'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_vshf_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1610@llvm_mips_vshf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1611 12define void @llvm_mips_vshf_b_test() nounwind {13entry:14 %0 = load <16 x i8>, ptr @llvm_mips_vshf_b_ARG115 %1 = load <16 x i8>, ptr @llvm_mips_vshf_b_ARG216 %2 = load <16 x i8>, ptr @llvm_mips_vshf_b_ARG317 %3 = tail call <16 x i8> @llvm.mips.vshf.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)18 store <16 x i8> %3, ptr @llvm_mips_vshf_b_RES19 ret void20}21 22declare <16 x i8> @llvm.mips.vshf.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind23 24; CHECK: llvm_mips_vshf_b_test:25; CHECK: ld.b26; CHECK: ld.b27; CHECK: ld.b28; CHECK: vshf.b29; CHECK: st.b30; CHECK: .size llvm_mips_vshf_b_test31;32@llvm_mips_vshf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1633@llvm_mips_vshf_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1634@llvm_mips_vshf_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1635@llvm_mips_vshf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1636 37define void @llvm_mips_vshf_h_test() nounwind {38entry:39 %0 = load <8 x i16>, ptr @llvm_mips_vshf_h_ARG140 %1 = load <8 x i16>, ptr @llvm_mips_vshf_h_ARG241 %2 = load <8 x i16>, ptr @llvm_mips_vshf_h_ARG342 %3 = tail call <8 x i16> @llvm.mips.vshf.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)43 store <8 x i16> %3, ptr @llvm_mips_vshf_h_RES44 ret void45}46 47declare <8 x i16> @llvm.mips.vshf.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind48 49; CHECK: llvm_mips_vshf_h_test:50; CHECK: ld.h51; CHECK: ld.h52; CHECK: ld.h53; CHECK: vshf.h54; CHECK: st.h55; CHECK: .size llvm_mips_vshf_h_test56;57@llvm_mips_vshf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1658@llvm_mips_vshf_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1659@llvm_mips_vshf_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1660@llvm_mips_vshf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1661 62define void @llvm_mips_vshf_w_test() nounwind {63entry:64 %0 = load <4 x i32>, ptr @llvm_mips_vshf_w_ARG165 %1 = load <4 x i32>, ptr @llvm_mips_vshf_w_ARG266 %2 = load <4 x i32>, ptr @llvm_mips_vshf_w_ARG367 %3 = tail call <4 x i32> @llvm.mips.vshf.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)68 store <4 x i32> %3, ptr @llvm_mips_vshf_w_RES69 ret void70}71 72declare <4 x i32> @llvm.mips.vshf.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind73 74; CHECK: llvm_mips_vshf_w_test:75; CHECK: ld.w76; CHECK: ld.w77; CHECK: ld.w78; CHECK: vshf.w79; CHECK: st.w80; CHECK: .size llvm_mips_vshf_w_test81;82@llvm_mips_vshf_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1683@llvm_mips_vshf_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1684@llvm_mips_vshf_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 1685@llvm_mips_vshf_d_RES = global <2 x i64> <i64 0, i64 0>, align 1686 87define void @llvm_mips_vshf_d_test() nounwind {88entry:89 %0 = load <2 x i64>, ptr @llvm_mips_vshf_d_ARG190 %1 = load <2 x i64>, ptr @llvm_mips_vshf_d_ARG291 %2 = load <2 x i64>, ptr @llvm_mips_vshf_d_ARG392 %3 = tail call <2 x i64> @llvm.mips.vshf.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)93 store <2 x i64> %3, ptr @llvm_mips_vshf_d_RES94 ret void95}96 97declare <2 x i64> @llvm.mips.vshf.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind98 99; CHECK: llvm_mips_vshf_d_test:100; CHECK: ld.d101; CHECK: ld.d102; CHECK: vshf.d103; CHECK: st.d104; CHECK: .size llvm_mips_vshf_d_test105;106