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1; Test the MSA intrinsics that are encoded with the 3R instruction format and2; use the result as a third operand.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 169@llvm_mips_maddv_b_ARG3 = global <16 x i8> <i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47>, align 1610@llvm_mips_maddv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1611 12define void @llvm_mips_maddv_b_test() nounwind {13entry:14 %0 = load <16 x i8>, ptr @llvm_mips_maddv_b_ARG115 %1 = load <16 x i8>, ptr @llvm_mips_maddv_b_ARG216 %2 = load <16 x i8>, ptr @llvm_mips_maddv_b_ARG317 %3 = tail call <16 x i8> @llvm.mips.maddv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)18 store <16 x i8> %3, ptr @llvm_mips_maddv_b_RES19 ret void20}21 22declare <16 x i8> @llvm.mips.maddv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind23 24; CHECK: llvm_mips_maddv_b_test:25; CHECK: ld.b26; CHECK: ld.b27; CHECK: ld.b28; CHECK: maddv.b29; CHECK: st.b30; CHECK: .size llvm_mips_maddv_b_test31;32@llvm_mips_maddv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1633@llvm_mips_maddv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1634@llvm_mips_maddv_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 1635@llvm_mips_maddv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1636 37define void @llvm_mips_maddv_h_test() nounwind {38entry:39 %0 = load <8 x i16>, ptr @llvm_mips_maddv_h_ARG140 %1 = load <8 x i16>, ptr @llvm_mips_maddv_h_ARG241 %2 = load <8 x i16>, ptr @llvm_mips_maddv_h_ARG342 %3 = tail call <8 x i16> @llvm.mips.maddv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)43 store <8 x i16> %3, ptr @llvm_mips_maddv_h_RES44 ret void45}46 47declare <8 x i16> @llvm.mips.maddv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind48 49; CHECK: llvm_mips_maddv_h_test:50; CHECK: ld.h51; CHECK: ld.h52; CHECK: ld.h53; CHECK: maddv.h54; CHECK: st.h55; CHECK: .size llvm_mips_maddv_h_test56;57@llvm_mips_maddv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1658@llvm_mips_maddv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1659@llvm_mips_maddv_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 1660@llvm_mips_maddv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1661 62define void @llvm_mips_maddv_w_test() nounwind {63entry:64 %0 = load <4 x i32>, ptr @llvm_mips_maddv_w_ARG165 %1 = load <4 x i32>, ptr @llvm_mips_maddv_w_ARG266 %2 = load <4 x i32>, ptr @llvm_mips_maddv_w_ARG367 %3 = tail call <4 x i32> @llvm.mips.maddv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)68 store <4 x i32> %3, ptr @llvm_mips_maddv_w_RES69 ret void70}71 72declare <4 x i32> @llvm.mips.maddv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind73 74; CHECK: llvm_mips_maddv_w_test:75; CHECK: ld.w76; CHECK: ld.w77; CHECK: ld.w78; CHECK: maddv.w79; CHECK: st.w80; CHECK: .size llvm_mips_maddv_w_test81;82@llvm_mips_maddv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1683@llvm_mips_maddv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1684@llvm_mips_maddv_d_ARG3 = global <2 x i64> <i64 4, i64 5>, align 1685@llvm_mips_maddv_d_RES = global <2 x i64> <i64 0, i64 0>, align 1686 87define void @llvm_mips_maddv_d_test() nounwind {88entry:89 %0 = load <2 x i64>, ptr @llvm_mips_maddv_d_ARG190 %1 = load <2 x i64>, ptr @llvm_mips_maddv_d_ARG291 %2 = load <2 x i64>, ptr @llvm_mips_maddv_d_ARG392 %3 = tail call <2 x i64> @llvm.mips.maddv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)93 store <2 x i64> %3, ptr @llvm_mips_maddv_d_RES94 ret void95}96 97declare <2 x i64> @llvm.mips.maddv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind98 99; CHECK: llvm_mips_maddv_d_test:100; CHECK: ld.d101; CHECK: ld.d102; CHECK: ld.d103; CHECK: maddv.d104; CHECK: st.d105; CHECK: .size llvm_mips_maddv_d_test106;107@llvm_mips_msubv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16108@llvm_mips_msubv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16109@llvm_mips_msubv_b_ARG3 = global <16 x i8> <i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47>, align 16110@llvm_mips_msubv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16111 112define void @llvm_mips_msubv_b_test() nounwind {113entry:114 %0 = load <16 x i8>, ptr @llvm_mips_msubv_b_ARG1115 %1 = load <16 x i8>, ptr @llvm_mips_msubv_b_ARG2116 %2 = load <16 x i8>, ptr @llvm_mips_msubv_b_ARG3117 %3 = tail call <16 x i8> @llvm.mips.msubv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)118 store <16 x i8> %3, ptr @llvm_mips_msubv_b_RES119 ret void120}121 122declare <16 x i8> @llvm.mips.msubv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind123 124; CHECK: llvm_mips_msubv_b_test:125; CHECK: ld.b126; CHECK: ld.b127; CHECK: ld.b128; CHECK: msubv.b129; CHECK: st.b130; CHECK: .size llvm_mips_msubv_b_test131;132@llvm_mips_msubv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16133@llvm_mips_msubv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16134@llvm_mips_msubv_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16135@llvm_mips_msubv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16136 137define void @llvm_mips_msubv_h_test() nounwind {138entry:139 %0 = load <8 x i16>, ptr @llvm_mips_msubv_h_ARG1140 %1 = load <8 x i16>, ptr @llvm_mips_msubv_h_ARG2141 %2 = load <8 x i16>, ptr @llvm_mips_msubv_h_ARG3142 %3 = tail call <8 x i16> @llvm.mips.msubv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)143 store <8 x i16> %3, ptr @llvm_mips_msubv_h_RES144 ret void145}146 147declare <8 x i16> @llvm.mips.msubv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind148 149; CHECK: llvm_mips_msubv_h_test:150; CHECK: ld.h151; CHECK: ld.h152; CHECK: ld.h153; CHECK: msubv.h154; CHECK: st.h155; CHECK: .size llvm_mips_msubv_h_test156;157@llvm_mips_msubv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16158@llvm_mips_msubv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16159@llvm_mips_msubv_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16160@llvm_mips_msubv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16161 162define void @llvm_mips_msubv_w_test() nounwind {163entry:164 %0 = load <4 x i32>, ptr @llvm_mips_msubv_w_ARG1165 %1 = load <4 x i32>, ptr @llvm_mips_msubv_w_ARG2166 %2 = load <4 x i32>, ptr @llvm_mips_msubv_w_ARG3167 %3 = tail call <4 x i32> @llvm.mips.msubv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)168 store <4 x i32> %3, ptr @llvm_mips_msubv_w_RES169 ret void170}171 172declare <4 x i32> @llvm.mips.msubv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind173 174; CHECK: llvm_mips_msubv_w_test:175; CHECK: ld.w176; CHECK: ld.w177; CHECK: ld.w178; CHECK: msubv.w179; CHECK: st.w180; CHECK: .size llvm_mips_msubv_w_test181;182@llvm_mips_msubv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16183@llvm_mips_msubv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16184@llvm_mips_msubv_d_ARG3 = global <2 x i64> <i64 4, i64 5>, align 16185@llvm_mips_msubv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16186 187define void @llvm_mips_msubv_d_test() nounwind {188entry:189 %0 = load <2 x i64>, ptr @llvm_mips_msubv_d_ARG1190 %1 = load <2 x i64>, ptr @llvm_mips_msubv_d_ARG2191 %2 = load <2 x i64>, ptr @llvm_mips_msubv_d_ARG3192 %3 = tail call <2 x i64> @llvm.mips.msubv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)193 store <2 x i64> %3, ptr @llvm_mips_msubv_d_RES194 ret void195}196 197declare <2 x i64> @llvm.mips.msubv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind198 199; CHECK: llvm_mips_msubv_d_test:200; CHECK: ld.d201; CHECK: ld.d202; CHECK: ld.d203; CHECK: msubv.d204; CHECK: st.d205; CHECK: .size llvm_mips_msubv_d_test206;207