296 lines · plain
1; Test the MSA intrinsics that are encoded with the 3R instruction format and2; use the result as a third operand and results in wider elements than the3; operands had.4 5; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s7 8@llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 169@llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 1610@llvm_mips_dpadd_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1611 12define void @llvm_mips_dpadd_s_h_test() nounwind {13entry:14 %0 = load <16 x i8>, ptr @llvm_mips_dpadd_s_h_ARG215 %1 = load <16 x i8>, ptr @llvm_mips_dpadd_s_h_ARG316 %2 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>, <16 x i8> %0, <16 x i8> %1)17 store <8 x i16> %2, ptr @llvm_mips_dpadd_s_h_RES18 ret void19}20 21declare <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind22 23; CHECK: llvm_mips_dpadd_s_h_test:24; CHECK: ld.b25; CHECK: ld.b26; CHECK: ldi.h [[R1:\$w[0-9]+]],27; CHECK: dpadd_s.h [[R1]],28; CHECK: st.h29; CHECK: .size llvm_mips_dpadd_s_h_test30;31@llvm_mips_dpadd_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 1632@llvm_mips_dpadd_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 1633@llvm_mips_dpadd_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1634 35define void @llvm_mips_dpadd_s_w_test() nounwind {36entry:37 %0 = load <8 x i16>, ptr @llvm_mips_dpadd_s_w_ARG238 %1 = load <8 x i16>, ptr @llvm_mips_dpadd_s_w_ARG339 %2 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> <i32 4, i32 4, i32 4, i32 4>, <8 x i16> %0, <8 x i16> %1)40 store <4 x i32> %2, ptr @llvm_mips_dpadd_s_w_RES41 ret void42}43 44declare <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind45 46; CHECK: llvm_mips_dpadd_s_w_test:47; CHECK: ld.h48; CHECK: ld.h49; CHECK: ldi.w [[R1:\$w[0-9]+]],50; CHECK: dpadd_s.w [[R1]],51; CHECK: st.w52; CHECK: .size llvm_mips_dpadd_s_w_test53;54@llvm_mips_dpadd_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 1655@llvm_mips_dpadd_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 1656@llvm_mips_dpadd_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 1657 58define void @llvm_mips_dpadd_s_d_test() nounwind {59entry:60 %0 = load <4 x i32>, ptr @llvm_mips_dpadd_s_d_ARG261 %1 = load <4 x i32>, ptr @llvm_mips_dpadd_s_d_ARG362 %2 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> <i64 4, i64 4>, <4 x i32> %0, <4 x i32> %1)63 store <2 x i64> %2, ptr @llvm_mips_dpadd_s_d_RES64 ret void65}66 67declare <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind68 69; CHECK: llvm_mips_dpadd_s_d_test:70; CHECK: ldi.d [[R1:\$w[0-9]+]],71; CHECK: ld.w72; CHECK: ld.w73; CHECK: dpadd_s.d [[R1]],74; CHECK: st.d75; CHECK: .size llvm_mips_dpadd_s_d_test76;77@llvm_mips_dpadd_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 1678@llvm_mips_dpadd_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 1679@llvm_mips_dpadd_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1680 81define void @llvm_mips_dpadd_u_h_test() nounwind {82entry:83 %0 = load <16 x i8>, ptr @llvm_mips_dpadd_u_h_ARG284 %1 = load <16 x i8>, ptr @llvm_mips_dpadd_u_h_ARG385 %2 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>, <16 x i8> %0, <16 x i8> %1)86 store <8 x i16> %2, ptr @llvm_mips_dpadd_u_h_RES87 ret void88}89 90declare <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind91 92; CHECK: llvm_mips_dpadd_u_h_test:93; CHECK: ld.b94; CHECK: ld.b95; CHECK: ldi.h [[R1:\$w[0-9]+]],96; CHECK: dpadd_u.h [[R1]],97; CHECK: st.h98; CHECK: .size llvm_mips_dpadd_u_h_test99;100@llvm_mips_dpadd_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16101@llvm_mips_dpadd_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16102@llvm_mips_dpadd_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16103 104define void @llvm_mips_dpadd_u_w_test() nounwind {105entry:106 %0 = load <8 x i16>, ptr @llvm_mips_dpadd_u_w_ARG2107 %1 = load <8 x i16>, ptr @llvm_mips_dpadd_u_w_ARG3108 %2 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> <i32 4, i32 4, i32 4, i32 4>, <8 x i16> %0, <8 x i16> %1)109 store <4 x i32> %2, ptr @llvm_mips_dpadd_u_w_RES110 ret void111}112 113declare <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind114 115; CHECK: llvm_mips_dpadd_u_w_test:116; CHECK: ld.h117; CHECK: ld.h118; CHECK: ldi.w [[R1:\$w[0-9]+]],119; CHECK: dpadd_u.w [[R1]],120; CHECK: st.w121; CHECK: .size llvm_mips_dpadd_u_w_test122;123@llvm_mips_dpadd_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16124@llvm_mips_dpadd_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16125@llvm_mips_dpadd_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16126 127define void @llvm_mips_dpadd_u_d_test() nounwind {128entry:129 %0 = load <4 x i32>, ptr @llvm_mips_dpadd_u_d_ARG2130 %1 = load <4 x i32>, ptr @llvm_mips_dpadd_u_d_ARG3131 %2 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> <i64 4, i64 4>, <4 x i32> %0, <4 x i32> %1)132 store <2 x i64> %2, ptr @llvm_mips_dpadd_u_d_RES133 ret void134}135 136declare <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind137 138; CHECK: llvm_mips_dpadd_u_d_test:139; CHECK: ldi.d [[R1:\$w[0-9]+]],140; CHECK: ld.w141; CHECK: ld.w142; CHECK: dpadd_u.d [[R1]],143; CHECK: st.d144; CHECK: .size llvm_mips_dpadd_u_d_test145;146@llvm_mips_dpsub_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16147@llvm_mips_dpsub_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16148@llvm_mips_dpsub_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16149@llvm_mips_dpsub_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16150 151define void @llvm_mips_dpsub_s_h_test() nounwind {152entry:153 %0 = load <8 x i16>, ptr @llvm_mips_dpsub_s_h_ARG1154 %1 = load <16 x i8>, ptr @llvm_mips_dpsub_s_h_ARG2155 %2 = load <16 x i8>, ptr @llvm_mips_dpsub_s_h_ARG3156 %3 = tail call <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)157 store <8 x i16> %3, ptr @llvm_mips_dpsub_s_h_RES158 ret void159}160 161declare <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind162 163; CHECK: llvm_mips_dpsub_s_h_test:164; CHECK: ld.b165; CHECK: ld.b166; CHECK: ld.h167; CHECK: dpsub_s.h168; CHECK: st.h169; CHECK: .size llvm_mips_dpsub_s_h_test170;171@llvm_mips_dpsub_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16172@llvm_mips_dpsub_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16173@llvm_mips_dpsub_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16174@llvm_mips_dpsub_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16175 176define void @llvm_mips_dpsub_s_w_test() nounwind {177entry:178 %0 = load <4 x i32>, ptr @llvm_mips_dpsub_s_w_ARG1179 %1 = load <8 x i16>, ptr @llvm_mips_dpsub_s_w_ARG2180 %2 = load <8 x i16>, ptr @llvm_mips_dpsub_s_w_ARG3181 %3 = tail call <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)182 store <4 x i32> %3, ptr @llvm_mips_dpsub_s_w_RES183 ret void184}185 186declare <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind187 188; CHECK: llvm_mips_dpsub_s_w_test:189; CHECK: ld.h190; CHECK: ld.h191; CHECK: ld.w192; CHECK: dpsub_s.w193; CHECK: st.w194; CHECK: .size llvm_mips_dpsub_s_w_test195;196@llvm_mips_dpsub_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16197@llvm_mips_dpsub_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16198@llvm_mips_dpsub_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16199@llvm_mips_dpsub_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16200 201define void @llvm_mips_dpsub_s_d_test() nounwind {202entry:203 %0 = load <2 x i64>, ptr @llvm_mips_dpsub_s_d_ARG1204 %1 = load <4 x i32>, ptr @llvm_mips_dpsub_s_d_ARG2205 %2 = load <4 x i32>, ptr @llvm_mips_dpsub_s_d_ARG3206 %3 = tail call <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)207 store <2 x i64> %3, ptr @llvm_mips_dpsub_s_d_RES208 ret void209}210 211declare <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind212 213; CHECK: llvm_mips_dpsub_s_d_test:214; CHECK: ld.w215; CHECK: ld.w216; CHECK: ld.d217; CHECK: dpsub_s.d218; CHECK: st.d219; CHECK: .size llvm_mips_dpsub_s_d_test220;221@llvm_mips_dpsub_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16222@llvm_mips_dpsub_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16223@llvm_mips_dpsub_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16224@llvm_mips_dpsub_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16225 226define void @llvm_mips_dpsub_u_h_test() nounwind {227entry:228 %0 = load <8 x i16>, ptr @llvm_mips_dpsub_u_h_ARG1229 %1 = load <16 x i8>, ptr @llvm_mips_dpsub_u_h_ARG2230 %2 = load <16 x i8>, ptr @llvm_mips_dpsub_u_h_ARG3231 %3 = tail call <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)232 store <8 x i16> %3, ptr @llvm_mips_dpsub_u_h_RES233 ret void234}235 236declare <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind237 238; CHECK: llvm_mips_dpsub_u_h_test:239; CHECK: ld.b240; CHECK: ld.b241; CHECK: ld.h242; CHECK: dpsub_u.h243; CHECK: st.h244; CHECK: .size llvm_mips_dpsub_u_h_test245;246@llvm_mips_dpsub_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16247@llvm_mips_dpsub_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16248@llvm_mips_dpsub_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16249@llvm_mips_dpsub_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16250 251define void @llvm_mips_dpsub_u_w_test() nounwind {252entry:253 %0 = load <4 x i32>, ptr @llvm_mips_dpsub_u_w_ARG1254 %1 = load <8 x i16>, ptr @llvm_mips_dpsub_u_w_ARG2255 %2 = load <8 x i16>, ptr @llvm_mips_dpsub_u_w_ARG3256 %3 = tail call <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)257 store <4 x i32> %3, ptr @llvm_mips_dpsub_u_w_RES258 ret void259}260 261declare <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind262 263; CHECK: llvm_mips_dpsub_u_w_test:264; CHECK: ld.h265; CHECK: ld.h266; CHECK: ld.w267; CHECK: dpsub_u.w268; CHECK: st.w269; CHECK: .size llvm_mips_dpsub_u_w_test270;271@llvm_mips_dpsub_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16272@llvm_mips_dpsub_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16273@llvm_mips_dpsub_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16274@llvm_mips_dpsub_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16275 276define void @llvm_mips_dpsub_u_d_test() nounwind {277entry:278 %0 = load <2 x i64>, ptr @llvm_mips_dpsub_u_d_ARG1279 %1 = load <4 x i32>, ptr @llvm_mips_dpsub_u_d_ARG2280 %2 = load <4 x i32>, ptr @llvm_mips_dpsub_u_d_ARG3281 %3 = tail call <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)282 store <2 x i64> %3, ptr @llvm_mips_dpsub_u_d_RES283 ret void284}285 286declare <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind287 288; CHECK: llvm_mips_dpsub_u_d_test:289; CHECK: ld.w290; CHECK: ld.w291; CHECK: ld.d292; CHECK: dpsub_u.d293; CHECK: st.d294; CHECK: .size llvm_mips_dpsub_u_d_test295;296