486 lines · plain
1; Test the MSA intrinsics that are encoded with the 3RF instruction format.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s4; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5 6@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 167@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 168@llvm_mips_fadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 169 10define void @llvm_mips_fadd_w_test() nounwind {11entry:12 %0 = load <4 x float>, ptr @llvm_mips_fadd_w_ARG113 %1 = load <4 x float>, ptr @llvm_mips_fadd_w_ARG214 %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)15 store <4 x float> %2, ptr @llvm_mips_fadd_w_RES16 ret void17}18 19declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind20 21; CHECK: llvm_mips_fadd_w_test:22; CHECK: ld.w23; CHECK: ld.w24; CHECK: fadd.w25; CHECK: st.w26; CHECK: .size llvm_mips_fadd_w_test27;28@llvm_mips_fadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1629@llvm_mips_fadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1630@llvm_mips_fadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1631 32define void @llvm_mips_fadd_d_test() nounwind {33entry:34 %0 = load <2 x double>, ptr @llvm_mips_fadd_d_ARG135 %1 = load <2 x double>, ptr @llvm_mips_fadd_d_ARG236 %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)37 store <2 x double> %2, ptr @llvm_mips_fadd_d_RES38 ret void39}40 41declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind42 43; CHECK: llvm_mips_fadd_d_test:44; CHECK: ld.d45; CHECK: ld.d46; CHECK: fadd.d47; CHECK: st.d48; CHECK: .size llvm_mips_fadd_d_test49 50define void @fadd_w_test() nounwind {51entry:52 %0 = load <4 x float>, ptr @llvm_mips_fadd_w_ARG153 %1 = load <4 x float>, ptr @llvm_mips_fadd_w_ARG254 %2 = fadd <4 x float> %0, %155 store <4 x float> %2, ptr @llvm_mips_fadd_w_RES56 ret void57}58 59; CHECK: fadd_w_test:60; CHECK: ld.w61; CHECK: ld.w62; CHECK: fadd.w63; CHECK: st.w64; CHECK: .size fadd_w_test65 66define void @fadd_d_test() nounwind {67entry:68 %0 = load <2 x double>, ptr @llvm_mips_fadd_d_ARG169 %1 = load <2 x double>, ptr @llvm_mips_fadd_d_ARG270 %2 = fadd <2 x double> %0, %171 store <2 x double> %2, ptr @llvm_mips_fadd_d_RES72 ret void73}74 75; CHECK: fadd_d_test:76; CHECK: ld.d77; CHECK: ld.d78; CHECK: fadd.d79; CHECK: st.d80; CHECK: .size fadd_d_test81;82@llvm_mips_fdiv_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1683@llvm_mips_fdiv_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 1684@llvm_mips_fdiv_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1685 86define void @llvm_mips_fdiv_w_test() nounwind {87entry:88 %0 = load <4 x float>, ptr @llvm_mips_fdiv_w_ARG189 %1 = load <4 x float>, ptr @llvm_mips_fdiv_w_ARG290 %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)91 store <4 x float> %2, ptr @llvm_mips_fdiv_w_RES92 ret void93}94 95declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind96 97; CHECK: llvm_mips_fdiv_w_test:98; CHECK: ld.w99; CHECK: ld.w100; CHECK: fdiv.w101; CHECK: st.w102; CHECK: .size llvm_mips_fdiv_w_test103;104@llvm_mips_fdiv_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16105@llvm_mips_fdiv_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16106@llvm_mips_fdiv_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16107 108define void @llvm_mips_fdiv_d_test() nounwind {109entry:110 %0 = load <2 x double>, ptr @llvm_mips_fdiv_d_ARG1111 %1 = load <2 x double>, ptr @llvm_mips_fdiv_d_ARG2112 %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)113 store <2 x double> %2, ptr @llvm_mips_fdiv_d_RES114 ret void115}116 117declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind118 119; CHECK: llvm_mips_fdiv_d_test:120; CHECK: ld.d121; CHECK: ld.d122; CHECK: fdiv.d123; CHECK: st.d124; CHECK: .size llvm_mips_fdiv_d_test125 126define void @fdiv_w_test() nounwind {127entry:128 %0 = load <4 x float>, ptr @llvm_mips_fdiv_w_ARG1129 %1 = load <4 x float>, ptr @llvm_mips_fdiv_w_ARG2130 %2 = fdiv <4 x float> %0, %1131 store <4 x float> %2, ptr @llvm_mips_fdiv_w_RES132 ret void133}134 135; CHECK: fdiv_w_test:136; CHECK: ld.w137; CHECK: ld.w138; CHECK: fdiv.w139; CHECK: st.w140; CHECK: .size fdiv_w_test141 142define void @fdiv_d_test() nounwind {143entry:144 %0 = load <2 x double>, ptr @llvm_mips_fdiv_d_ARG1145 %1 = load <2 x double>, ptr @llvm_mips_fdiv_d_ARG2146 %2 = fdiv <2 x double> %0, %1147 store <2 x double> %2, ptr @llvm_mips_fdiv_d_RES148 ret void149}150 151; CHECK: fdiv_d_test:152; CHECK: ld.d153; CHECK: ld.d154; CHECK: fdiv.d155; CHECK: st.d156; CHECK: .size fdiv_d_test157;158@llvm_mips_fmin_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16159@llvm_mips_fmin_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16160@llvm_mips_fmin_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16161 162define void @llvm_mips_fmin_w_test() nounwind {163entry:164 %0 = load <4 x float>, ptr @llvm_mips_fmin_w_ARG1165 %1 = load <4 x float>, ptr @llvm_mips_fmin_w_ARG2166 %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1)167 store <4 x float> %2, ptr @llvm_mips_fmin_w_RES168 ret void169}170 171declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind172 173; CHECK: llvm_mips_fmin_w_test:174; CHECK: ld.w175; CHECK: ld.w176; CHECK: fmin.w177; CHECK: st.w178; CHECK: .size llvm_mips_fmin_w_test179;180@llvm_mips_fmin_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16181@llvm_mips_fmin_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16182@llvm_mips_fmin_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16183 184define void @llvm_mips_fmin_d_test() nounwind {185entry:186 %0 = load <2 x double>, ptr @llvm_mips_fmin_d_ARG1187 %1 = load <2 x double>, ptr @llvm_mips_fmin_d_ARG2188 %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1)189 store <2 x double> %2, ptr @llvm_mips_fmin_d_RES190 ret void191}192 193declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind194 195; CHECK: llvm_mips_fmin_d_test:196; CHECK: ld.d197; CHECK: ld.d198; CHECK: fmin.d199; CHECK: st.d200; CHECK: .size llvm_mips_fmin_d_test201;202@llvm_mips_fmin_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16203@llvm_mips_fmin_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16204@llvm_mips_fmin_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16205 206define void @llvm_mips_fmin_a_w_test() nounwind {207entry:208 %0 = load <4 x float>, ptr @llvm_mips_fmin_a_w_ARG1209 %1 = load <4 x float>, ptr @llvm_mips_fmin_a_w_ARG2210 %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1)211 store <4 x float> %2, ptr @llvm_mips_fmin_a_w_RES212 ret void213}214 215declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind216 217; CHECK: llvm_mips_fmin_a_w_test:218; CHECK: ld.w219; CHECK: ld.w220; CHECK: fmin_a.w221; CHECK: st.w222; CHECK: .size llvm_mips_fmin_a_w_test223;224@llvm_mips_fmin_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16225@llvm_mips_fmin_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16226@llvm_mips_fmin_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16227 228define void @llvm_mips_fmin_a_d_test() nounwind {229entry:230 %0 = load <2 x double>, ptr @llvm_mips_fmin_a_d_ARG1231 %1 = load <2 x double>, ptr @llvm_mips_fmin_a_d_ARG2232 %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1)233 store <2 x double> %2, ptr @llvm_mips_fmin_a_d_RES234 ret void235}236 237declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind238 239; CHECK: llvm_mips_fmin_a_d_test:240; CHECK: ld.d241; CHECK: ld.d242; CHECK: fmin_a.d243; CHECK: st.d244; CHECK: .size llvm_mips_fmin_a_d_test245;246@llvm_mips_fmax_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16247@llvm_mips_fmax_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16248@llvm_mips_fmax_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16249 250define void @llvm_mips_fmax_w_test() nounwind {251entry:252 %0 = load <4 x float>, ptr @llvm_mips_fmax_w_ARG1253 %1 = load <4 x float>, ptr @llvm_mips_fmax_w_ARG2254 %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1)255 store <4 x float> %2, ptr @llvm_mips_fmax_w_RES256 ret void257}258 259declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind260 261; CHECK: llvm_mips_fmax_w_test:262; CHECK: ld.w263; CHECK: ld.w264; CHECK: fmax.w265; CHECK: st.w266; CHECK: .size llvm_mips_fmax_w_test267;268@llvm_mips_fmax_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16269@llvm_mips_fmax_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16270@llvm_mips_fmax_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16271 272define void @llvm_mips_fmax_d_test() nounwind {273entry:274 %0 = load <2 x double>, ptr @llvm_mips_fmax_d_ARG1275 %1 = load <2 x double>, ptr @llvm_mips_fmax_d_ARG2276 %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1)277 store <2 x double> %2, ptr @llvm_mips_fmax_d_RES278 ret void279}280 281declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind282 283; CHECK: llvm_mips_fmax_d_test:284; CHECK: ld.d285; CHECK: ld.d286; CHECK: fmax.d287; CHECK: st.d288; CHECK: .size llvm_mips_fmax_d_test289;290@llvm_mips_fmax_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16291@llvm_mips_fmax_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16292@llvm_mips_fmax_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16293 294define void @llvm_mips_fmax_a_w_test() nounwind {295entry:296 %0 = load <4 x float>, ptr @llvm_mips_fmax_a_w_ARG1297 %1 = load <4 x float>, ptr @llvm_mips_fmax_a_w_ARG2298 %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1)299 store <4 x float> %2, ptr @llvm_mips_fmax_a_w_RES300 ret void301}302 303declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind304 305; CHECK: llvm_mips_fmax_a_w_test:306; CHECK: ld.w307; CHECK: ld.w308; CHECK: fmax_a.w309; CHECK: st.w310; CHECK: .size llvm_mips_fmax_a_w_test311;312@llvm_mips_fmax_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16313@llvm_mips_fmax_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16314@llvm_mips_fmax_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16315 316define void @llvm_mips_fmax_a_d_test() nounwind {317entry:318 %0 = load <2 x double>, ptr @llvm_mips_fmax_a_d_ARG1319 %1 = load <2 x double>, ptr @llvm_mips_fmax_a_d_ARG2320 %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1)321 store <2 x double> %2, ptr @llvm_mips_fmax_a_d_RES322 ret void323}324 325declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind326 327; CHECK: llvm_mips_fmax_a_d_test:328; CHECK: ld.d329; CHECK: ld.d330; CHECK: fmax_a.d331; CHECK: st.d332; CHECK: .size llvm_mips_fmax_a_d_test333;334@llvm_mips_fmul_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16335@llvm_mips_fmul_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16336@llvm_mips_fmul_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16337 338define void @llvm_mips_fmul_w_test() nounwind {339entry:340 %0 = load <4 x float>, ptr @llvm_mips_fmul_w_ARG1341 %1 = load <4 x float>, ptr @llvm_mips_fmul_w_ARG2342 %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)343 store <4 x float> %2, ptr @llvm_mips_fmul_w_RES344 ret void345}346 347declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind348 349; CHECK: llvm_mips_fmul_w_test:350; CHECK: ld.w351; CHECK: ld.w352; CHECK: fmul.w353; CHECK: st.w354; CHECK: .size llvm_mips_fmul_w_test355;356@llvm_mips_fmul_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16357@llvm_mips_fmul_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16358@llvm_mips_fmul_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16359 360define void @llvm_mips_fmul_d_test() nounwind {361entry:362 %0 = load <2 x double>, ptr @llvm_mips_fmul_d_ARG1363 %1 = load <2 x double>, ptr @llvm_mips_fmul_d_ARG2364 %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)365 store <2 x double> %2, ptr @llvm_mips_fmul_d_RES366 ret void367}368 369declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind370 371; CHECK: llvm_mips_fmul_d_test:372; CHECK: ld.d373; CHECK: ld.d374; CHECK: fmul.d375; CHECK: st.d376; CHECK: .size llvm_mips_fmul_d_test377 378define void @fmul_w_test() nounwind {379entry:380 %0 = load <4 x float>, ptr @llvm_mips_fmul_w_ARG1381 %1 = load <4 x float>, ptr @llvm_mips_fmul_w_ARG2382 %2 = fmul <4 x float> %0, %1383 store <4 x float> %2, ptr @llvm_mips_fmul_w_RES384 ret void385}386 387; CHECK: fmul_w_test:388; CHECK: ld.w389; CHECK: ld.w390; CHECK: fmul.w391; CHECK: st.w392; CHECK: .size fmul_w_test393 394define void @fmul_d_test() nounwind {395entry:396 %0 = load <2 x double>, ptr @llvm_mips_fmul_d_ARG1397 %1 = load <2 x double>, ptr @llvm_mips_fmul_d_ARG2398 %2 = fmul <2 x double> %0, %1399 store <2 x double> %2, ptr @llvm_mips_fmul_d_RES400 ret void401}402 403; CHECK: fmul_d_test:404; CHECK: ld.d405; CHECK: ld.d406; CHECK: fmul.d407; CHECK: st.d408; CHECK: .size fmul_d_test409;410@llvm_mips_fsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16411@llvm_mips_fsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16412@llvm_mips_fsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16413 414define void @llvm_mips_fsub_w_test() nounwind {415entry:416 %0 = load <4 x float>, ptr @llvm_mips_fsub_w_ARG1417 %1 = load <4 x float>, ptr @llvm_mips_fsub_w_ARG2418 %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)419 store <4 x float> %2, ptr @llvm_mips_fsub_w_RES420 ret void421}422 423declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind424 425; CHECK: llvm_mips_fsub_w_test:426; CHECK: ld.w427; CHECK: ld.w428; CHECK: fsub.w429; CHECK: st.w430; CHECK: .size llvm_mips_fsub_w_test431;432@llvm_mips_fsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16433@llvm_mips_fsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16434@llvm_mips_fsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16435 436define void @llvm_mips_fsub_d_test() nounwind {437entry:438 %0 = load <2 x double>, ptr @llvm_mips_fsub_d_ARG1439 %1 = load <2 x double>, ptr @llvm_mips_fsub_d_ARG2440 %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)441 store <2 x double> %2, ptr @llvm_mips_fsub_d_RES442 ret void443}444 445declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind446 447; CHECK: llvm_mips_fsub_d_test:448; CHECK: ld.d449; CHECK: ld.d450; CHECK: fsub.d451; CHECK: st.d452; CHECK: .size llvm_mips_fsub_d_test453;454 455define void @fsub_w_test() nounwind {456entry:457 %0 = load <4 x float>, ptr @llvm_mips_fsub_w_ARG1458 %1 = load <4 x float>, ptr @llvm_mips_fsub_w_ARG2459 %2 = fsub <4 x float> %0, %1460 store <4 x float> %2, ptr @llvm_mips_fsub_w_RES461 ret void462}463 464; CHECK: fsub_w_test:465; CHECK: ld.w466; CHECK: ld.w467; CHECK: fsub.w468; CHECK: st.w469; CHECK: .size fsub_w_test470 471define void @fsub_d_test() nounwind {472entry:473 %0 = load <2 x double>, ptr @llvm_mips_fsub_d_ARG1474 %1 = load <2 x double>, ptr @llvm_mips_fsub_d_ARG2475 %2 = fsub <2 x double> %0, %1476 store <2 x double> %2, ptr @llvm_mips_fsub_d_RES477 ret void478}479 480; CHECK: fsub_d_test:481; CHECK: ld.d482; CHECK: ld.d483; CHECK: fsub.d484; CHECK: st.d485; CHECK: .size fsub_d_test486