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1; Test the MSA intrinsics that are encoded with the 3RF instruction format and2; use the result as a third operand.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 168@llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 169@llvm_mips_fmadd_w_ARG3 = global <4 x float> <float 8.000000e+00, float 9.000000e+00, float 1.000000e+01, float 1.100000e+01>, align 1610@llvm_mips_fmadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1611 12define void @llvm_mips_fmadd_w_test() nounwind {13entry:14 %0 = load <4 x float>, ptr @llvm_mips_fmadd_w_ARG115 %1 = load <4 x float>, ptr @llvm_mips_fmadd_w_ARG216 %2 = load <4 x float>, ptr @llvm_mips_fmadd_w_ARG317 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)18 store <4 x float> %3, ptr @llvm_mips_fmadd_w_RES19 ret void20}21 22declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind23 24; CHECK: llvm_mips_fmadd_w_test:25; CHECK: ld.w26; CHECK: ld.w27; CHECK: ld.w28; CHECK: fmadd.w29; CHECK: st.w30; CHECK: .size llvm_mips_fmadd_w_test31;32@llvm_mips_fmadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1633@llvm_mips_fmadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1634@llvm_mips_fmadd_d_ARG3 = global <2 x double> <double 4.000000e+00, double 5.000000e+00>, align 1635@llvm_mips_fmadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1636 37define void @llvm_mips_fmadd_d_test() nounwind {38entry:39 %0 = load <2 x double>, ptr @llvm_mips_fmadd_d_ARG140 %1 = load <2 x double>, ptr @llvm_mips_fmadd_d_ARG241 %2 = load <2 x double>, ptr @llvm_mips_fmadd_d_ARG342 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)43 store <2 x double> %3, ptr @llvm_mips_fmadd_d_RES44 ret void45}46 47declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind48 49; CHECK: llvm_mips_fmadd_d_test:50; CHECK: ld.d51; CHECK: ld.d52; CHECK: ld.d53; CHECK: fmadd.d54; CHECK: st.d55; CHECK: .size llvm_mips_fmadd_d_test56;57@llvm_mips_fmsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1658@llvm_mips_fmsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 1659@llvm_mips_fmsub_w_ARG3 = global <4 x float> <float 8.000000e+00, float 9.000000e+00, float 1.000000e+01, float 1.100000e+01>, align 1660@llvm_mips_fmsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1661 62define void @llvm_mips_fmsub_w_test() nounwind {63entry:64 %0 = load <4 x float>, ptr @llvm_mips_fmsub_w_ARG165 %1 = load <4 x float>, ptr @llvm_mips_fmsub_w_ARG266 %2 = load <4 x float>, ptr @llvm_mips_fmsub_w_ARG367 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)68 store <4 x float> %3, ptr @llvm_mips_fmsub_w_RES69 ret void70}71 72declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind73 74; CHECK: llvm_mips_fmsub_w_test:75; CHECK: ld.w76; CHECK: ld.w77; CHECK: ld.w78; CHECK: fmsub.w79; CHECK: st.w80; CHECK: .size llvm_mips_fmsub_w_test81;82@llvm_mips_fmsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1683@llvm_mips_fmsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1684@llvm_mips_fmsub_d_ARG3 = global <2 x double> <double 4.000000e+00, double 5.000000e+00>, align 1685@llvm_mips_fmsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1686 87define void @llvm_mips_fmsub_d_test() nounwind {88entry:89 %0 = load <2 x double>, ptr @llvm_mips_fmsub_d_ARG190 %1 = load <2 x double>, ptr @llvm_mips_fmsub_d_ARG291 %2 = load <2 x double>, ptr @llvm_mips_fmsub_d_ARG392 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)93 store <2 x double> %3, ptr @llvm_mips_fmsub_d_RES94 ret void95}96 97declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind98 99; CHECK: llvm_mips_fmsub_d_test:100; CHECK: ld.d101; CHECK: ld.d102; CHECK: ld.d103; CHECK: fmsub.d104; CHECK: st.d105; CHECK: .size llvm_mips_fmsub_d_test106;107