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1; Test the MSA intrinsics that are encoded with the 3RF instruction format and2; use the result as a third operand and perform fixed-point operations.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 168@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 169@llvm_mips_madd_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 1610@llvm_mips_madd_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1611 12define void @llvm_mips_madd_q_h_test() nounwind {13entry:14 %0 = load <8 x i16>, ptr @llvm_mips_madd_q_h_ARG115 %1 = load <8 x i16>, ptr @llvm_mips_madd_q_h_ARG216 %2 = load <8 x i16>, ptr @llvm_mips_madd_q_h_ARG317 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)18 store <8 x i16> %3, ptr @llvm_mips_madd_q_h_RES19 ret void20}21 22declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind23 24; CHECK: llvm_mips_madd_q_h_test:25; CHECK: ld.h26; CHECK: ld.h27; CHECK: ld.h28; CHECK: madd_q.h29; CHECK: st.h30; CHECK: .size llvm_mips_madd_q_h_test31;32@llvm_mips_madd_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1633@llvm_mips_madd_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1634@llvm_mips_madd_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 1635@llvm_mips_madd_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1636 37define void @llvm_mips_madd_q_w_test() nounwind {38entry:39 %0 = load <4 x i32>, ptr @llvm_mips_madd_q_w_ARG140 %1 = load <4 x i32>, ptr @llvm_mips_madd_q_w_ARG241 %2 = load <4 x i32>, ptr @llvm_mips_madd_q_w_ARG342 %3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)43 store <4 x i32> %3, ptr @llvm_mips_madd_q_w_RES44 ret void45}46 47declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind48 49; CHECK: llvm_mips_madd_q_w_test:50; CHECK: ld.w51; CHECK: ld.w52; CHECK: ld.w53; CHECK: madd_q.w54; CHECK: st.w55; CHECK: .size llvm_mips_madd_q_w_test56;57@llvm_mips_maddr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1658@llvm_mips_maddr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1659@llvm_mips_maddr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 1660@llvm_mips_maddr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1661 62define void @llvm_mips_maddr_q_h_test() nounwind {63entry:64 %0 = load <8 x i16>, ptr @llvm_mips_maddr_q_h_ARG165 %1 = load <8 x i16>, ptr @llvm_mips_maddr_q_h_ARG266 %2 = load <8 x i16>, ptr @llvm_mips_maddr_q_h_ARG367 %3 = tail call <8 x i16> @llvm.mips.maddr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)68 store <8 x i16> %3, ptr @llvm_mips_maddr_q_h_RES69 ret void70}71 72declare <8 x i16> @llvm.mips.maddr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind73 74; CHECK: llvm_mips_maddr_q_h_test:75; CHECK: ld.h76; CHECK: ld.h77; CHECK: ld.h78; CHECK: maddr_q.h79; CHECK: st.h80; CHECK: .size llvm_mips_maddr_q_h_test81;82@llvm_mips_maddr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1683@llvm_mips_maddr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1684@llvm_mips_maddr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 1685@llvm_mips_maddr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1686 87define void @llvm_mips_maddr_q_w_test() nounwind {88entry:89 %0 = load <4 x i32>, ptr @llvm_mips_maddr_q_w_ARG190 %1 = load <4 x i32>, ptr @llvm_mips_maddr_q_w_ARG291 %2 = load <4 x i32>, ptr @llvm_mips_maddr_q_w_ARG392 %3 = tail call <4 x i32> @llvm.mips.maddr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)93 store <4 x i32> %3, ptr @llvm_mips_maddr_q_w_RES94 ret void95}96 97declare <4 x i32> @llvm.mips.maddr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind98 99; CHECK: llvm_mips_maddr_q_w_test:100; CHECK: ld.w101; CHECK: ld.w102; CHECK: ld.w103; CHECK: maddr_q.w104; CHECK: st.w105; CHECK: .size llvm_mips_maddr_q_w_test106;107@llvm_mips_msub_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16108@llvm_mips_msub_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16109@llvm_mips_msub_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16110@llvm_mips_msub_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16111 112define void @llvm_mips_msub_q_h_test() nounwind {113entry:114 %0 = load <8 x i16>, ptr @llvm_mips_msub_q_h_ARG1115 %1 = load <8 x i16>, ptr @llvm_mips_msub_q_h_ARG2116 %2 = load <8 x i16>, ptr @llvm_mips_msub_q_h_ARG3117 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)118 store <8 x i16> %3, ptr @llvm_mips_msub_q_h_RES119 ret void120}121 122declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind123 124; CHECK: llvm_mips_msub_q_h_test:125; CHECK: ld.h126; CHECK: ld.h127; CHECK: ld.h128; CHECK: msub_q.h129; CHECK: st.h130; CHECK: .size llvm_mips_msub_q_h_test131;132@llvm_mips_msub_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16133@llvm_mips_msub_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16134@llvm_mips_msub_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16135@llvm_mips_msub_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16136 137define void @llvm_mips_msub_q_w_test() nounwind {138entry:139 %0 = load <4 x i32>, ptr @llvm_mips_msub_q_w_ARG1140 %1 = load <4 x i32>, ptr @llvm_mips_msub_q_w_ARG2141 %2 = load <4 x i32>, ptr @llvm_mips_msub_q_w_ARG3142 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)143 store <4 x i32> %3, ptr @llvm_mips_msub_q_w_RES144 ret void145}146 147declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind148 149; CHECK: llvm_mips_msub_q_w_test:150; CHECK: ld.w151; CHECK: ld.w152; CHECK: ld.w153; CHECK: msub_q.w154; CHECK: st.w155; CHECK: .size llvm_mips_msub_q_w_test156;157@llvm_mips_msubr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16158@llvm_mips_msubr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16159@llvm_mips_msubr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16160@llvm_mips_msubr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16161 162define void @llvm_mips_msubr_q_h_test() nounwind {163entry:164 %0 = load <8 x i16>, ptr @llvm_mips_msubr_q_h_ARG1165 %1 = load <8 x i16>, ptr @llvm_mips_msubr_q_h_ARG2166 %2 = load <8 x i16>, ptr @llvm_mips_msubr_q_h_ARG3167 %3 = tail call <8 x i16> @llvm.mips.msubr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)168 store <8 x i16> %3, ptr @llvm_mips_msubr_q_h_RES169 ret void170}171 172declare <8 x i16> @llvm.mips.msubr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind173 174; CHECK: llvm_mips_msubr_q_h_test:175; CHECK: ld.h176; CHECK: ld.h177; CHECK: ld.h178; CHECK: msubr_q.h179; CHECK: st.h180; CHECK: .size llvm_mips_msubr_q_h_test181;182@llvm_mips_msubr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16183@llvm_mips_msubr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16184@llvm_mips_msubr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16185@llvm_mips_msubr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16186 187define void @llvm_mips_msubr_q_w_test() nounwind {188entry:189 %0 = load <4 x i32>, ptr @llvm_mips_msubr_q_w_ARG1190 %1 = load <4 x i32>, ptr @llvm_mips_msubr_q_w_ARG2191 %2 = load <4 x i32>, ptr @llvm_mips_msubr_q_w_ARG3192 %3 = tail call <4 x i32> @llvm.mips.msubr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)193 store <4 x i32> %3, ptr @llvm_mips_msubr_q_w_RES194 ret void195}196 197declare <4 x i32> @llvm.mips.msubr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind198 199; CHECK: llvm_mips_msubr_q_w_test:200; CHECK: ld.w201; CHECK: ld.w202; CHECK: ld.w203; CHECK: msubr_q.w204; CHECK: st.w205; CHECK: .size llvm_mips_msubr_q_w_test206;207