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1; Test the MSA floating-point conversion intrinsics that are encoded with the2; 3RF instruction format.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 168@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 169@llvm_mips_fexdo_h_RES = global <8 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, align 1610 11define void @llvm_mips_fexdo_h_test() nounwind {12entry:13 %0 = load <4 x float>, ptr @llvm_mips_fexdo_h_ARG114 %1 = load <4 x float>, ptr @llvm_mips_fexdo_h_ARG215 %2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1)16 store <8 x half> %2, ptr @llvm_mips_fexdo_h_RES17 ret void18}19 20declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind21 22; CHECK: llvm_mips_fexdo_h_test:23; CHECK: ld.w24; CHECK: ld.w25; CHECK: fexdo.h26; CHECK: st.h27; CHECK: .size llvm_mips_fexdo_h_test28;29@llvm_mips_fexdo_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1630@llvm_mips_fexdo_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1631@llvm_mips_fexdo_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1632 33define void @llvm_mips_fexdo_w_test() nounwind {34entry:35 %0 = load <2 x double>, ptr @llvm_mips_fexdo_w_ARG136 %1 = load <2 x double>, ptr @llvm_mips_fexdo_w_ARG237 %2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1)38 store <4 x float> %2, ptr @llvm_mips_fexdo_w_RES39 ret void40}41 42declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind43 44; CHECK: llvm_mips_fexdo_w_test:45; CHECK: ld.d46; CHECK: ld.d47; CHECK: fexdo.w48; CHECK: st.w49; CHECK: .size llvm_mips_fexdo_w_test50;51