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1; Test the MSA intrinsics that are encoded with the 3RF instruction format and2; take an integer as an operand.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 168@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 169@llvm_mips_fexp2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1610 11define void @llvm_mips_fexp2_w_test() nounwind {12entry:13 %0 = load <4 x float>, ptr @llvm_mips_fexp2_w_ARG114 %1 = load <4 x i32>, ptr @llvm_mips_fexp2_w_ARG215 %2 = tail call <4 x float> @llvm.mips.fexp2.w(<4 x float> %0, <4 x i32> %1)16 store <4 x float> %2, ptr @llvm_mips_fexp2_w_RES17 ret void18}19 20declare <4 x float> @llvm.mips.fexp2.w(<4 x float>, <4 x i32>) nounwind21 22; CHECK: llvm_mips_fexp2_w_test:23; CHECK: ld.w24; CHECK: ld.w25; CHECK: fexp2.w26; CHECK: st.w27; CHECK: .size llvm_mips_fexp2_w_test28;29@llvm_mips_fexp2_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1630@llvm_mips_fexp2_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1631@llvm_mips_fexp2_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1632 33define void @llvm_mips_fexp2_d_test() nounwind {34entry:35 %0 = load <2 x double>, ptr @llvm_mips_fexp2_d_ARG136 %1 = load <2 x i64>, ptr @llvm_mips_fexp2_d_ARG237 %2 = tail call <2 x double> @llvm.mips.fexp2.d(<2 x double> %0, <2 x i64> %1)38 store <2 x double> %2, ptr @llvm_mips_fexp2_d_RES39 ret void40}41 42declare <2 x double> @llvm.mips.fexp2.d(<2 x double>, <2 x i64>) nounwind43 44; CHECK: llvm_mips_fexp2_d_test:45; CHECK: ld.d46; CHECK: ld.d47; CHECK: fexp2.d48; CHECK: st.d49; CHECK: .size llvm_mips_fexp2_d_test50;51