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1; Test the MSA intrinsics that are encoded with the 3RF instruction format and2; produce an integer as a result.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 168@llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 169@llvm_mips_fcaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1610 11define void @llvm_mips_fcaf_w_test() nounwind {12entry:13 %0 = load <4 x float>, ptr @llvm_mips_fcaf_w_ARG114 %1 = load <4 x float>, ptr @llvm_mips_fcaf_w_ARG215 %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)16 store <4 x i32> %2, ptr @llvm_mips_fcaf_w_RES17 ret void18}19 20declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind21 22; CHECK: llvm_mips_fcaf_w_test:23; CHECK: ld.w24; CHECK: ld.w25; CHECK: fcaf.w26; CHECK: st.w27; CHECK: .size llvm_mips_fcaf_w_test28;29@llvm_mips_fcaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1630@llvm_mips_fcaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1631@llvm_mips_fcaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 1632 33define void @llvm_mips_fcaf_d_test() nounwind {34entry:35 %0 = load <2 x double>, ptr @llvm_mips_fcaf_d_ARG136 %1 = load <2 x double>, ptr @llvm_mips_fcaf_d_ARG237 %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1)38 store <2 x i64> %2, ptr @llvm_mips_fcaf_d_RES39 ret void40}41 42declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind43 44; CHECK: llvm_mips_fcaf_d_test:45; CHECK: ld.d46; CHECK: ld.d47; CHECK: fcaf.d48; CHECK: st.d49; CHECK: .size llvm_mips_fcaf_d_test50;51@llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1652@llvm_mips_fceq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 1653@llvm_mips_fceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1654 55define void @llvm_mips_fceq_w_test() nounwind {56entry:57 %0 = load <4 x float>, ptr @llvm_mips_fceq_w_ARG158 %1 = load <4 x float>, ptr @llvm_mips_fceq_w_ARG259 %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1)60 store <4 x i32> %2, ptr @llvm_mips_fceq_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind65 66; CHECK: llvm_mips_fceq_w_test:67; CHECK: ld.w68; CHECK: ld.w69; CHECK: fceq.w70; CHECK: st.w71; CHECK: .size llvm_mips_fceq_w_test72;73@llvm_mips_fceq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1674@llvm_mips_fceq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 1675@llvm_mips_fceq_d_RES = global <2 x i64> <i64 0, i64 0>, align 1676 77define void @llvm_mips_fceq_d_test() nounwind {78entry:79 %0 = load <2 x double>, ptr @llvm_mips_fceq_d_ARG180 %1 = load <2 x double>, ptr @llvm_mips_fceq_d_ARG281 %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1)82 store <2 x i64> %2, ptr @llvm_mips_fceq_d_RES83 ret void84}85 86declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind87 88; CHECK: llvm_mips_fceq_d_test:89; CHECK: ld.d90; CHECK: ld.d91; CHECK: fceq.d92; CHECK: st.d93; CHECK: .size llvm_mips_fceq_d_test94;95@llvm_mips_fcle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1696@llvm_mips_fcle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 1697@llvm_mips_fcle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1698 99define void @llvm_mips_fcle_w_test() nounwind {100entry:101 %0 = load <4 x float>, ptr @llvm_mips_fcle_w_ARG1102 %1 = load <4 x float>, ptr @llvm_mips_fcle_w_ARG2103 %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1)104 store <4 x i32> %2, ptr @llvm_mips_fcle_w_RES105 ret void106}107 108declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind109 110; CHECK: llvm_mips_fcle_w_test:111; CHECK: ld.w112; CHECK: ld.w113; CHECK: fcle.w114; CHECK: st.w115; CHECK: .size llvm_mips_fcle_w_test116;117@llvm_mips_fcle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16118@llvm_mips_fcle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16119@llvm_mips_fcle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16120 121define void @llvm_mips_fcle_d_test() nounwind {122entry:123 %0 = load <2 x double>, ptr @llvm_mips_fcle_d_ARG1124 %1 = load <2 x double>, ptr @llvm_mips_fcle_d_ARG2125 %2 = tail call <2 x i64> @llvm.mips.fcle.d(<2 x double> %0, <2 x double> %1)126 store <2 x i64> %2, ptr @llvm_mips_fcle_d_RES127 ret void128}129 130declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind131 132; CHECK: llvm_mips_fcle_d_test:133; CHECK: ld.d134; CHECK: ld.d135; CHECK: fcle.d136; CHECK: st.d137; CHECK: .size llvm_mips_fcle_d_test138;139@llvm_mips_fclt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16140@llvm_mips_fclt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16141@llvm_mips_fclt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16142 143define void @llvm_mips_fclt_w_test() nounwind {144entry:145 %0 = load <4 x float>, ptr @llvm_mips_fclt_w_ARG1146 %1 = load <4 x float>, ptr @llvm_mips_fclt_w_ARG2147 %2 = tail call <4 x i32> @llvm.mips.fclt.w(<4 x float> %0, <4 x float> %1)148 store <4 x i32> %2, ptr @llvm_mips_fclt_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind153 154; CHECK: llvm_mips_fclt_w_test:155; CHECK: ld.w156; CHECK: ld.w157; CHECK: fclt.w158; CHECK: st.w159; CHECK: .size llvm_mips_fclt_w_test160;161@llvm_mips_fclt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16162@llvm_mips_fclt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16163@llvm_mips_fclt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16164 165define void @llvm_mips_fclt_d_test() nounwind {166entry:167 %0 = load <2 x double>, ptr @llvm_mips_fclt_d_ARG1168 %1 = load <2 x double>, ptr @llvm_mips_fclt_d_ARG2169 %2 = tail call <2 x i64> @llvm.mips.fclt.d(<2 x double> %0, <2 x double> %1)170 store <2 x i64> %2, ptr @llvm_mips_fclt_d_RES171 ret void172}173 174declare <2 x i64> @llvm.mips.fclt.d(<2 x double>, <2 x double>) nounwind175 176; CHECK: llvm_mips_fclt_d_test:177; CHECK: ld.d178; CHECK: ld.d179; CHECK: fclt.d180; CHECK: st.d181; CHECK: .size llvm_mips_fclt_d_test182;183@llvm_mips_fcor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16184@llvm_mips_fcor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16185@llvm_mips_fcor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16186 187define void @llvm_mips_fcor_w_test() nounwind {188entry:189 %0 = load <4 x float>, ptr @llvm_mips_fcor_w_ARG1190 %1 = load <4 x float>, ptr @llvm_mips_fcor_w_ARG2191 %2 = tail call <4 x i32> @llvm.mips.fcor.w(<4 x float> %0, <4 x float> %1)192 store <4 x i32> %2, ptr @llvm_mips_fcor_w_RES193 ret void194}195 196declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind197 198; CHECK: llvm_mips_fcor_w_test:199; CHECK: ld.w200; CHECK: ld.w201; CHECK: fcor.w202; CHECK: st.w203; CHECK: .size llvm_mips_fcor_w_test204;205@llvm_mips_fcor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16206@llvm_mips_fcor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16207@llvm_mips_fcor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16208 209define void @llvm_mips_fcor_d_test() nounwind {210entry:211 %0 = load <2 x double>, ptr @llvm_mips_fcor_d_ARG1212 %1 = load <2 x double>, ptr @llvm_mips_fcor_d_ARG2213 %2 = tail call <2 x i64> @llvm.mips.fcor.d(<2 x double> %0, <2 x double> %1)214 store <2 x i64> %2, ptr @llvm_mips_fcor_d_RES215 ret void216}217 218declare <2 x i64> @llvm.mips.fcor.d(<2 x double>, <2 x double>) nounwind219 220; CHECK: llvm_mips_fcor_d_test:221; CHECK: ld.d222; CHECK: ld.d223; CHECK: fcor.d224; CHECK: st.d225; CHECK: .size llvm_mips_fcor_d_test226;227@llvm_mips_fcne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16228@llvm_mips_fcne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16229@llvm_mips_fcne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16230 231define void @llvm_mips_fcne_w_test() nounwind {232entry:233 %0 = load <4 x float>, ptr @llvm_mips_fcne_w_ARG1234 %1 = load <4 x float>, ptr @llvm_mips_fcne_w_ARG2235 %2 = tail call <4 x i32> @llvm.mips.fcne.w(<4 x float> %0, <4 x float> %1)236 store <4 x i32> %2, ptr @llvm_mips_fcne_w_RES237 ret void238}239 240declare <4 x i32> @llvm.mips.fcne.w(<4 x float>, <4 x float>) nounwind241 242; CHECK: llvm_mips_fcne_w_test:243; CHECK: ld.w244; CHECK: ld.w245; CHECK: fcne.w246; CHECK: st.w247; CHECK: .size llvm_mips_fcne_w_test248;249@llvm_mips_fcne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16250@llvm_mips_fcne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16251@llvm_mips_fcne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16252 253define void @llvm_mips_fcne_d_test() nounwind {254entry:255 %0 = load <2 x double>, ptr @llvm_mips_fcne_d_ARG1256 %1 = load <2 x double>, ptr @llvm_mips_fcne_d_ARG2257 %2 = tail call <2 x i64> @llvm.mips.fcne.d(<2 x double> %0, <2 x double> %1)258 store <2 x i64> %2, ptr @llvm_mips_fcne_d_RES259 ret void260}261 262declare <2 x i64> @llvm.mips.fcne.d(<2 x double>, <2 x double>) nounwind263 264; CHECK: llvm_mips_fcne_d_test:265; CHECK: ld.d266; CHECK: ld.d267; CHECK: fcne.d268; CHECK: st.d269; CHECK: .size llvm_mips_fcne_d_test270;271@llvm_mips_fcueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16272@llvm_mips_fcueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16273@llvm_mips_fcueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16274 275define void @llvm_mips_fcueq_w_test() nounwind {276entry:277 %0 = load <4 x float>, ptr @llvm_mips_fcueq_w_ARG1278 %1 = load <4 x float>, ptr @llvm_mips_fcueq_w_ARG2279 %2 = tail call <4 x i32> @llvm.mips.fcueq.w(<4 x float> %0, <4 x float> %1)280 store <4 x i32> %2, ptr @llvm_mips_fcueq_w_RES281 ret void282}283 284declare <4 x i32> @llvm.mips.fcueq.w(<4 x float>, <4 x float>) nounwind285 286; CHECK: llvm_mips_fcueq_w_test:287; CHECK: ld.w288; CHECK: ld.w289; CHECK: fcueq.w290; CHECK: st.w291; CHECK: .size llvm_mips_fcueq_w_test292;293@llvm_mips_fcueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16294@llvm_mips_fcueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16295@llvm_mips_fcueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16296 297define void @llvm_mips_fcueq_d_test() nounwind {298entry:299 %0 = load <2 x double>, ptr @llvm_mips_fcueq_d_ARG1300 %1 = load <2 x double>, ptr @llvm_mips_fcueq_d_ARG2301 %2 = tail call <2 x i64> @llvm.mips.fcueq.d(<2 x double> %0, <2 x double> %1)302 store <2 x i64> %2, ptr @llvm_mips_fcueq_d_RES303 ret void304}305 306declare <2 x i64> @llvm.mips.fcueq.d(<2 x double>, <2 x double>) nounwind307 308; CHECK: llvm_mips_fcueq_d_test:309; CHECK: ld.d310; CHECK: ld.d311; CHECK: fcueq.d312; CHECK: st.d313; CHECK: .size llvm_mips_fcueq_d_test314;315@llvm_mips_fcult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16316@llvm_mips_fcult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16317@llvm_mips_fcult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16318 319define void @llvm_mips_fcult_w_test() nounwind {320entry:321 %0 = load <4 x float>, ptr @llvm_mips_fcult_w_ARG1322 %1 = load <4 x float>, ptr @llvm_mips_fcult_w_ARG2323 %2 = tail call <4 x i32> @llvm.mips.fcult.w(<4 x float> %0, <4 x float> %1)324 store <4 x i32> %2, ptr @llvm_mips_fcult_w_RES325 ret void326}327 328declare <4 x i32> @llvm.mips.fcult.w(<4 x float>, <4 x float>) nounwind329 330; CHECK: llvm_mips_fcult_w_test:331; CHECK: ld.w332; CHECK: ld.w333; CHECK: fcult.w334; CHECK: st.w335; CHECK: .size llvm_mips_fcult_w_test336;337@llvm_mips_fcult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16338@llvm_mips_fcult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16339@llvm_mips_fcult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16340 341define void @llvm_mips_fcult_d_test() nounwind {342entry:343 %0 = load <2 x double>, ptr @llvm_mips_fcult_d_ARG1344 %1 = load <2 x double>, ptr @llvm_mips_fcult_d_ARG2345 %2 = tail call <2 x i64> @llvm.mips.fcult.d(<2 x double> %0, <2 x double> %1)346 store <2 x i64> %2, ptr @llvm_mips_fcult_d_RES347 ret void348}349 350declare <2 x i64> @llvm.mips.fcult.d(<2 x double>, <2 x double>) nounwind351 352; CHECK: llvm_mips_fcult_d_test:353; CHECK: ld.d354; CHECK: ld.d355; CHECK: fcult.d356; CHECK: st.d357; CHECK: .size llvm_mips_fcult_d_test358;359@llvm_mips_fcule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16360@llvm_mips_fcule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16361@llvm_mips_fcule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16362 363define void @llvm_mips_fcule_w_test() nounwind {364entry:365 %0 = load <4 x float>, ptr @llvm_mips_fcule_w_ARG1366 %1 = load <4 x float>, ptr @llvm_mips_fcule_w_ARG2367 %2 = tail call <4 x i32> @llvm.mips.fcule.w(<4 x float> %0, <4 x float> %1)368 store <4 x i32> %2, ptr @llvm_mips_fcule_w_RES369 ret void370}371 372declare <4 x i32> @llvm.mips.fcule.w(<4 x float>, <4 x float>) nounwind373 374; CHECK: llvm_mips_fcule_w_test:375; CHECK: ld.w376; CHECK: ld.w377; CHECK: fcule.w378; CHECK: st.w379; CHECK: .size llvm_mips_fcule_w_test380;381@llvm_mips_fcule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16382@llvm_mips_fcule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16383@llvm_mips_fcule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16384 385define void @llvm_mips_fcule_d_test() nounwind {386entry:387 %0 = load <2 x double>, ptr @llvm_mips_fcule_d_ARG1388 %1 = load <2 x double>, ptr @llvm_mips_fcule_d_ARG2389 %2 = tail call <2 x i64> @llvm.mips.fcule.d(<2 x double> %0, <2 x double> %1)390 store <2 x i64> %2, ptr @llvm_mips_fcule_d_RES391 ret void392}393 394declare <2 x i64> @llvm.mips.fcule.d(<2 x double>, <2 x double>) nounwind395 396; CHECK: llvm_mips_fcule_d_test:397; CHECK: ld.d398; CHECK: ld.d399; CHECK: fcule.d400; CHECK: st.d401; CHECK: .size llvm_mips_fcule_d_test402;403@llvm_mips_fcun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16404@llvm_mips_fcun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16405@llvm_mips_fcun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16406 407define void @llvm_mips_fcun_w_test() nounwind {408entry:409 %0 = load <4 x float>, ptr @llvm_mips_fcun_w_ARG1410 %1 = load <4 x float>, ptr @llvm_mips_fcun_w_ARG2411 %2 = tail call <4 x i32> @llvm.mips.fcun.w(<4 x float> %0, <4 x float> %1)412 store <4 x i32> %2, ptr @llvm_mips_fcun_w_RES413 ret void414}415 416declare <4 x i32> @llvm.mips.fcun.w(<4 x float>, <4 x float>) nounwind417 418; CHECK: llvm_mips_fcun_w_test:419; CHECK: ld.w420; CHECK: ld.w421; CHECK: fcun.w422; CHECK: st.w423; CHECK: .size llvm_mips_fcun_w_test424;425@llvm_mips_fcun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16426@llvm_mips_fcun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16427@llvm_mips_fcun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16428 429define void @llvm_mips_fcun_d_test() nounwind {430entry:431 %0 = load <2 x double>, ptr @llvm_mips_fcun_d_ARG1432 %1 = load <2 x double>, ptr @llvm_mips_fcun_d_ARG2433 %2 = tail call <2 x i64> @llvm.mips.fcun.d(<2 x double> %0, <2 x double> %1)434 store <2 x i64> %2, ptr @llvm_mips_fcun_d_RES435 ret void436}437 438declare <2 x i64> @llvm.mips.fcun.d(<2 x double>, <2 x double>) nounwind439 440; CHECK: llvm_mips_fcun_d_test:441; CHECK: ld.d442; CHECK: ld.d443; CHECK: fcun.d444; CHECK: st.d445; CHECK: .size llvm_mips_fcun_d_test446;447@llvm_mips_fcune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16448@llvm_mips_fcune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16449@llvm_mips_fcune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16450 451define void @llvm_mips_fcune_w_test() nounwind {452entry:453 %0 = load <4 x float>, ptr @llvm_mips_fcune_w_ARG1454 %1 = load <4 x float>, ptr @llvm_mips_fcune_w_ARG2455 %2 = tail call <4 x i32> @llvm.mips.fcune.w(<4 x float> %0, <4 x float> %1)456 store <4 x i32> %2, ptr @llvm_mips_fcune_w_RES457 ret void458}459 460declare <4 x i32> @llvm.mips.fcune.w(<4 x float>, <4 x float>) nounwind461 462; CHECK: llvm_mips_fcune_w_test:463; CHECK: ld.w464; CHECK: ld.w465; CHECK: fcune.w466; CHECK: st.w467; CHECK: .size llvm_mips_fcune_w_test468;469@llvm_mips_fcune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16470@llvm_mips_fcune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16471@llvm_mips_fcune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16472 473define void @llvm_mips_fcune_d_test() nounwind {474entry:475 %0 = load <2 x double>, ptr @llvm_mips_fcune_d_ARG1476 %1 = load <2 x double>, ptr @llvm_mips_fcune_d_ARG2477 %2 = tail call <2 x i64> @llvm.mips.fcune.d(<2 x double> %0, <2 x double> %1)478 store <2 x i64> %2, ptr @llvm_mips_fcune_d_RES479 ret void480}481 482declare <2 x i64> @llvm.mips.fcune.d(<2 x double>, <2 x double>) nounwind483 484; CHECK: llvm_mips_fcune_d_test:485; CHECK: ld.d486; CHECK: ld.d487; CHECK: fcune.d488; CHECK: st.d489; CHECK: .size llvm_mips_fcune_d_test490;491@llvm_mips_fsaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16492@llvm_mips_fsaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16493@llvm_mips_fsaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16494 495define void @llvm_mips_fsaf_w_test() nounwind {496entry:497 %0 = load <4 x float>, ptr @llvm_mips_fsaf_w_ARG1498 %1 = load <4 x float>, ptr @llvm_mips_fsaf_w_ARG2499 %2 = tail call <4 x i32> @llvm.mips.fsaf.w(<4 x float> %0, <4 x float> %1)500 store <4 x i32> %2, ptr @llvm_mips_fsaf_w_RES501 ret void502}503 504declare <4 x i32> @llvm.mips.fsaf.w(<4 x float>, <4 x float>) nounwind505 506; CHECK: llvm_mips_fsaf_w_test:507; CHECK: ld.w508; CHECK: ld.w509; CHECK: fsaf.w510; CHECK: st.w511; CHECK: .size llvm_mips_fsaf_w_test512;513@llvm_mips_fsaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16514@llvm_mips_fsaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16515@llvm_mips_fsaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16516 517define void @llvm_mips_fsaf_d_test() nounwind {518entry:519 %0 = load <2 x double>, ptr @llvm_mips_fsaf_d_ARG1520 %1 = load <2 x double>, ptr @llvm_mips_fsaf_d_ARG2521 %2 = tail call <2 x i64> @llvm.mips.fsaf.d(<2 x double> %0, <2 x double> %1)522 store <2 x i64> %2, ptr @llvm_mips_fsaf_d_RES523 ret void524}525 526declare <2 x i64> @llvm.mips.fsaf.d(<2 x double>, <2 x double>) nounwind527 528; CHECK: llvm_mips_fsaf_d_test:529; CHECK: ld.d530; CHECK: ld.d531; CHECK: fsaf.d532; CHECK: st.d533; CHECK: .size llvm_mips_fsaf_d_test534;535@llvm_mips_fseq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16536@llvm_mips_fseq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16537@llvm_mips_fseq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16538 539define void @llvm_mips_fseq_w_test() nounwind {540entry:541 %0 = load <4 x float>, ptr @llvm_mips_fseq_w_ARG1542 %1 = load <4 x float>, ptr @llvm_mips_fseq_w_ARG2543 %2 = tail call <4 x i32> @llvm.mips.fseq.w(<4 x float> %0, <4 x float> %1)544 store <4 x i32> %2, ptr @llvm_mips_fseq_w_RES545 ret void546}547 548declare <4 x i32> @llvm.mips.fseq.w(<4 x float>, <4 x float>) nounwind549 550; CHECK: llvm_mips_fseq_w_test:551; CHECK: ld.w552; CHECK: ld.w553; CHECK: fseq.w554; CHECK: st.w555; CHECK: .size llvm_mips_fseq_w_test556;557@llvm_mips_fseq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16558@llvm_mips_fseq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16559@llvm_mips_fseq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16560 561define void @llvm_mips_fseq_d_test() nounwind {562entry:563 %0 = load <2 x double>, ptr @llvm_mips_fseq_d_ARG1564 %1 = load <2 x double>, ptr @llvm_mips_fseq_d_ARG2565 %2 = tail call <2 x i64> @llvm.mips.fseq.d(<2 x double> %0, <2 x double> %1)566 store <2 x i64> %2, ptr @llvm_mips_fseq_d_RES567 ret void568}569 570declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind571 572; CHECK: llvm_mips_fseq_d_test:573; CHECK: ld.d574; CHECK: ld.d575; CHECK: fseq.d576; CHECK: st.d577; CHECK: .size llvm_mips_fseq_d_test578;579@llvm_mips_fsle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16580@llvm_mips_fsle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16581@llvm_mips_fsle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16582 583define void @llvm_mips_fsle_w_test() nounwind {584entry:585 %0 = load <4 x float>, ptr @llvm_mips_fsle_w_ARG1586 %1 = load <4 x float>, ptr @llvm_mips_fsle_w_ARG2587 %2 = tail call <4 x i32> @llvm.mips.fsle.w(<4 x float> %0, <4 x float> %1)588 store <4 x i32> %2, ptr @llvm_mips_fsle_w_RES589 ret void590}591 592declare <4 x i32> @llvm.mips.fsle.w(<4 x float>, <4 x float>) nounwind593 594; CHECK: llvm_mips_fsle_w_test:595; CHECK: ld.w596; CHECK: ld.w597; CHECK: fsle.w598; CHECK: st.w599; CHECK: .size llvm_mips_fsle_w_test600;601@llvm_mips_fsle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16602@llvm_mips_fsle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16603@llvm_mips_fsle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16604 605define void @llvm_mips_fsle_d_test() nounwind {606entry:607 %0 = load <2 x double>, ptr @llvm_mips_fsle_d_ARG1608 %1 = load <2 x double>, ptr @llvm_mips_fsle_d_ARG2609 %2 = tail call <2 x i64> @llvm.mips.fsle.d(<2 x double> %0, <2 x double> %1)610 store <2 x i64> %2, ptr @llvm_mips_fsle_d_RES611 ret void612}613 614declare <2 x i64> @llvm.mips.fsle.d(<2 x double>, <2 x double>) nounwind615 616; CHECK: llvm_mips_fsle_d_test:617; CHECK: ld.d618; CHECK: ld.d619; CHECK: fsle.d620; CHECK: st.d621; CHECK: .size llvm_mips_fsle_d_test622;623@llvm_mips_fslt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16624@llvm_mips_fslt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16625@llvm_mips_fslt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16626 627define void @llvm_mips_fslt_w_test() nounwind {628entry:629 %0 = load <4 x float>, ptr @llvm_mips_fslt_w_ARG1630 %1 = load <4 x float>, ptr @llvm_mips_fslt_w_ARG2631 %2 = tail call <4 x i32> @llvm.mips.fslt.w(<4 x float> %0, <4 x float> %1)632 store <4 x i32> %2, ptr @llvm_mips_fslt_w_RES633 ret void634}635 636declare <4 x i32> @llvm.mips.fslt.w(<4 x float>, <4 x float>) nounwind637 638; CHECK: llvm_mips_fslt_w_test:639; CHECK: ld.w640; CHECK: ld.w641; CHECK: fslt.w642; CHECK: st.w643; CHECK: .size llvm_mips_fslt_w_test644;645@llvm_mips_fslt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16646@llvm_mips_fslt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16647@llvm_mips_fslt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16648 649define void @llvm_mips_fslt_d_test() nounwind {650entry:651 %0 = load <2 x double>, ptr @llvm_mips_fslt_d_ARG1652 %1 = load <2 x double>, ptr @llvm_mips_fslt_d_ARG2653 %2 = tail call <2 x i64> @llvm.mips.fslt.d(<2 x double> %0, <2 x double> %1)654 store <2 x i64> %2, ptr @llvm_mips_fslt_d_RES655 ret void656}657 658declare <2 x i64> @llvm.mips.fslt.d(<2 x double>, <2 x double>) nounwind659 660; CHECK: llvm_mips_fslt_d_test:661; CHECK: ld.d662; CHECK: ld.d663; CHECK: fslt.d664; CHECK: st.d665; CHECK: .size llvm_mips_fslt_d_test666;667@llvm_mips_fsor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16668@llvm_mips_fsor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16669@llvm_mips_fsor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16670 671define void @llvm_mips_fsor_w_test() nounwind {672entry:673 %0 = load <4 x float>, ptr @llvm_mips_fsor_w_ARG1674 %1 = load <4 x float>, ptr @llvm_mips_fsor_w_ARG2675 %2 = tail call <4 x i32> @llvm.mips.fsor.w(<4 x float> %0, <4 x float> %1)676 store <4 x i32> %2, ptr @llvm_mips_fsor_w_RES677 ret void678}679 680declare <4 x i32> @llvm.mips.fsor.w(<4 x float>, <4 x float>) nounwind681 682; CHECK: llvm_mips_fsor_w_test:683; CHECK: ld.w684; CHECK: ld.w685; CHECK: fsor.w686; CHECK: st.w687; CHECK: .size llvm_mips_fsor_w_test688;689@llvm_mips_fsor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16690@llvm_mips_fsor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16691@llvm_mips_fsor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16692 693define void @llvm_mips_fsor_d_test() nounwind {694entry:695 %0 = load <2 x double>, ptr @llvm_mips_fsor_d_ARG1696 %1 = load <2 x double>, ptr @llvm_mips_fsor_d_ARG2697 %2 = tail call <2 x i64> @llvm.mips.fsor.d(<2 x double> %0, <2 x double> %1)698 store <2 x i64> %2, ptr @llvm_mips_fsor_d_RES699 ret void700}701 702declare <2 x i64> @llvm.mips.fsor.d(<2 x double>, <2 x double>) nounwind703 704; CHECK: llvm_mips_fsor_d_test:705; CHECK: ld.d706; CHECK: ld.d707; CHECK: fsor.d708; CHECK: st.d709; CHECK: .size llvm_mips_fsor_d_test710;711@llvm_mips_fsne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16712@llvm_mips_fsne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16713@llvm_mips_fsne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16714 715define void @llvm_mips_fsne_w_test() nounwind {716entry:717 %0 = load <4 x float>, ptr @llvm_mips_fsne_w_ARG1718 %1 = load <4 x float>, ptr @llvm_mips_fsne_w_ARG2719 %2 = tail call <4 x i32> @llvm.mips.fsne.w(<4 x float> %0, <4 x float> %1)720 store <4 x i32> %2, ptr @llvm_mips_fsne_w_RES721 ret void722}723 724declare <4 x i32> @llvm.mips.fsne.w(<4 x float>, <4 x float>) nounwind725 726; CHECK: llvm_mips_fsne_w_test:727; CHECK: ld.w728; CHECK: ld.w729; CHECK: fsne.w730; CHECK: st.w731; CHECK: .size llvm_mips_fsne_w_test732;733@llvm_mips_fsne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16734@llvm_mips_fsne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16735@llvm_mips_fsne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16736 737define void @llvm_mips_fsne_d_test() nounwind {738entry:739 %0 = load <2 x double>, ptr @llvm_mips_fsne_d_ARG1740 %1 = load <2 x double>, ptr @llvm_mips_fsne_d_ARG2741 %2 = tail call <2 x i64> @llvm.mips.fsne.d(<2 x double> %0, <2 x double> %1)742 store <2 x i64> %2, ptr @llvm_mips_fsne_d_RES743 ret void744}745 746declare <2 x i64> @llvm.mips.fsne.d(<2 x double>, <2 x double>) nounwind747 748; CHECK: llvm_mips_fsne_d_test:749; CHECK: ld.d750; CHECK: ld.d751; CHECK: fsne.d752; CHECK: st.d753; CHECK: .size llvm_mips_fsne_d_test754;755@llvm_mips_fsueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16756@llvm_mips_fsueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16757@llvm_mips_fsueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16758 759define void @llvm_mips_fsueq_w_test() nounwind {760entry:761 %0 = load <4 x float>, ptr @llvm_mips_fsueq_w_ARG1762 %1 = load <4 x float>, ptr @llvm_mips_fsueq_w_ARG2763 %2 = tail call <4 x i32> @llvm.mips.fsueq.w(<4 x float> %0, <4 x float> %1)764 store <4 x i32> %2, ptr @llvm_mips_fsueq_w_RES765 ret void766}767 768declare <4 x i32> @llvm.mips.fsueq.w(<4 x float>, <4 x float>) nounwind769 770; CHECK: llvm_mips_fsueq_w_test:771; CHECK: ld.w772; CHECK: ld.w773; CHECK: fsueq.w774; CHECK: st.w775; CHECK: .size llvm_mips_fsueq_w_test776;777@llvm_mips_fsueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16778@llvm_mips_fsueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16779@llvm_mips_fsueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16780 781define void @llvm_mips_fsueq_d_test() nounwind {782entry:783 %0 = load <2 x double>, ptr @llvm_mips_fsueq_d_ARG1784 %1 = load <2 x double>, ptr @llvm_mips_fsueq_d_ARG2785 %2 = tail call <2 x i64> @llvm.mips.fsueq.d(<2 x double> %0, <2 x double> %1)786 store <2 x i64> %2, ptr @llvm_mips_fsueq_d_RES787 ret void788}789 790declare <2 x i64> @llvm.mips.fsueq.d(<2 x double>, <2 x double>) nounwind791 792; CHECK: llvm_mips_fsueq_d_test:793; CHECK: ld.d794; CHECK: ld.d795; CHECK: fsueq.d796; CHECK: st.d797; CHECK: .size llvm_mips_fsueq_d_test798;799@llvm_mips_fsult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16800@llvm_mips_fsult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16801@llvm_mips_fsult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16802 803define void @llvm_mips_fsult_w_test() nounwind {804entry:805 %0 = load <4 x float>, ptr @llvm_mips_fsult_w_ARG1806 %1 = load <4 x float>, ptr @llvm_mips_fsult_w_ARG2807 %2 = tail call <4 x i32> @llvm.mips.fsult.w(<4 x float> %0, <4 x float> %1)808 store <4 x i32> %2, ptr @llvm_mips_fsult_w_RES809 ret void810}811 812declare <4 x i32> @llvm.mips.fsult.w(<4 x float>, <4 x float>) nounwind813 814; CHECK: llvm_mips_fsult_w_test:815; CHECK: ld.w816; CHECK: ld.w817; CHECK: fsult.w818; CHECK: st.w819; CHECK: .size llvm_mips_fsult_w_test820;821@llvm_mips_fsult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16822@llvm_mips_fsult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16823@llvm_mips_fsult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16824 825define void @llvm_mips_fsult_d_test() nounwind {826entry:827 %0 = load <2 x double>, ptr @llvm_mips_fsult_d_ARG1828 %1 = load <2 x double>, ptr @llvm_mips_fsult_d_ARG2829 %2 = tail call <2 x i64> @llvm.mips.fsult.d(<2 x double> %0, <2 x double> %1)830 store <2 x i64> %2, ptr @llvm_mips_fsult_d_RES831 ret void832}833 834declare <2 x i64> @llvm.mips.fsult.d(<2 x double>, <2 x double>) nounwind835 836; CHECK: llvm_mips_fsult_d_test:837; CHECK: ld.d838; CHECK: ld.d839; CHECK: fsult.d840; CHECK: st.d841; CHECK: .size llvm_mips_fsult_d_test842;843@llvm_mips_fsule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16844@llvm_mips_fsule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16845@llvm_mips_fsule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16846 847define void @llvm_mips_fsule_w_test() nounwind {848entry:849 %0 = load <4 x float>, ptr @llvm_mips_fsule_w_ARG1850 %1 = load <4 x float>, ptr @llvm_mips_fsule_w_ARG2851 %2 = tail call <4 x i32> @llvm.mips.fsule.w(<4 x float> %0, <4 x float> %1)852 store <4 x i32> %2, ptr @llvm_mips_fsule_w_RES853 ret void854}855 856declare <4 x i32> @llvm.mips.fsule.w(<4 x float>, <4 x float>) nounwind857 858; CHECK: llvm_mips_fsule_w_test:859; CHECK: ld.w860; CHECK: ld.w861; CHECK: fsule.w862; CHECK: st.w863; CHECK: .size llvm_mips_fsule_w_test864;865@llvm_mips_fsule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16866@llvm_mips_fsule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16867@llvm_mips_fsule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16868 869define void @llvm_mips_fsule_d_test() nounwind {870entry:871 %0 = load <2 x double>, ptr @llvm_mips_fsule_d_ARG1872 %1 = load <2 x double>, ptr @llvm_mips_fsule_d_ARG2873 %2 = tail call <2 x i64> @llvm.mips.fsule.d(<2 x double> %0, <2 x double> %1)874 store <2 x i64> %2, ptr @llvm_mips_fsule_d_RES875 ret void876}877 878declare <2 x i64> @llvm.mips.fsule.d(<2 x double>, <2 x double>) nounwind879 880; CHECK: llvm_mips_fsule_d_test:881; CHECK: ld.d882; CHECK: ld.d883; CHECK: fsule.d884; CHECK: st.d885; CHECK: .size llvm_mips_fsule_d_test886;887@llvm_mips_fsun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16888@llvm_mips_fsun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16889@llvm_mips_fsun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16890 891define void @llvm_mips_fsun_w_test() nounwind {892entry:893 %0 = load <4 x float>, ptr @llvm_mips_fsun_w_ARG1894 %1 = load <4 x float>, ptr @llvm_mips_fsun_w_ARG2895 %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)896 store <4 x i32> %2, ptr @llvm_mips_fsun_w_RES897 ret void898}899 900declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind901 902; CHECK: llvm_mips_fsun_w_test:903; CHECK: ld.w904; CHECK: ld.w905; CHECK: fsun.w906; CHECK: st.w907; CHECK: .size llvm_mips_fsun_w_test908;909@llvm_mips_fsun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16910@llvm_mips_fsun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16911@llvm_mips_fsun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16912 913define void @llvm_mips_fsun_d_test() nounwind {914entry:915 %0 = load <2 x double>, ptr @llvm_mips_fsun_d_ARG1916 %1 = load <2 x double>, ptr @llvm_mips_fsun_d_ARG2917 %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)918 store <2 x i64> %2, ptr @llvm_mips_fsun_d_RES919 ret void920}921 922declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind923 924; CHECK: llvm_mips_fsun_d_test:925; CHECK: ld.d926; CHECK: ld.d927; CHECK: fsun.d928; CHECK: st.d929; CHECK: .size llvm_mips_fsun_d_test930;931@llvm_mips_fsune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16932@llvm_mips_fsune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16933@llvm_mips_fsune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16934 935define void @llvm_mips_fsune_w_test() nounwind {936entry:937 %0 = load <4 x float>, ptr @llvm_mips_fsune_w_ARG1938 %1 = load <4 x float>, ptr @llvm_mips_fsune_w_ARG2939 %2 = tail call <4 x i32> @llvm.mips.fsune.w(<4 x float> %0, <4 x float> %1)940 store <4 x i32> %2, ptr @llvm_mips_fsune_w_RES941 ret void942}943 944declare <4 x i32> @llvm.mips.fsune.w(<4 x float>, <4 x float>) nounwind945 946; CHECK: llvm_mips_fsune_w_test:947; CHECK: ld.w948; CHECK: ld.w949; CHECK: fsune.w950; CHECK: st.w951; CHECK: .size llvm_mips_fsune_w_test952;953@llvm_mips_fsune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16954@llvm_mips_fsune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16955@llvm_mips_fsune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16956 957define void @llvm_mips_fsune_d_test() nounwind {958entry:959 %0 = load <2 x double>, ptr @llvm_mips_fsune_d_ARG1960 %1 = load <2 x double>, ptr @llvm_mips_fsune_d_ARG2961 %2 = tail call <2 x i64> @llvm.mips.fsune.d(<2 x double> %0, <2 x double> %1)962 store <2 x i64> %2, ptr @llvm_mips_fsune_d_RES963 ret void964}965 966declare <2 x i64> @llvm.mips.fsune.d(<2 x double>, <2 x double>) nounwind967 968; CHECK: llvm_mips_fsune_d_test:969; CHECK: ld.d970; CHECK: ld.d971; CHECK: fsune.d972; CHECK: st.d973; CHECK: .size llvm_mips_fsune_d_test974;975