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1; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction2; format.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 168@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 169@llvm_mips_mul_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1610 11define void @llvm_mips_mul_q_h_test() nounwind {12entry:13 %0 = load <8 x i16>, ptr @llvm_mips_mul_q_h_ARG114 %1 = load <8 x i16>, ptr @llvm_mips_mul_q_h_ARG215 %2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)16 store <8 x i16> %2, ptr @llvm_mips_mul_q_h_RES17 ret void18}19 20declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind21 22; CHECK: llvm_mips_mul_q_h_test:23; CHECK: ld.h24; CHECK: ld.h25; CHECK: mul_q.h26; CHECK: st.h27; CHECK: .size llvm_mips_mul_q_h_test28;29@llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1630@llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1631@llvm_mips_mul_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1632 33define void @llvm_mips_mul_q_w_test() nounwind {34entry:35 %0 = load <4 x i32>, ptr @llvm_mips_mul_q_w_ARG136 %1 = load <4 x i32>, ptr @llvm_mips_mul_q_w_ARG237 %2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)38 store <4 x i32> %2, ptr @llvm_mips_mul_q_w_RES39 ret void40}41 42declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind43 44; CHECK: llvm_mips_mul_q_w_test:45; CHECK: ld.w46; CHECK: ld.w47; CHECK: mul_q.w48; CHECK: st.w49; CHECK: .size llvm_mips_mul_q_w_test50;51@llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1652@llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1653@llvm_mips_mulr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1654 55define void @llvm_mips_mulr_q_h_test() nounwind {56entry:57 %0 = load <8 x i16>, ptr @llvm_mips_mulr_q_h_ARG158 %1 = load <8 x i16>, ptr @llvm_mips_mulr_q_h_ARG259 %2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)60 store <8 x i16> %2, ptr @llvm_mips_mulr_q_h_RES61 ret void62}63 64declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind65 66; CHECK: llvm_mips_mulr_q_h_test:67; CHECK: ld.h68; CHECK: ld.h69; CHECK: mulr_q.h70; CHECK: st.h71; CHECK: .size llvm_mips_mulr_q_h_test72;73@llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1674@llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1675@llvm_mips_mulr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1676 77define void @llvm_mips_mulr_q_w_test() nounwind {78entry:79 %0 = load <4 x i32>, ptr @llvm_mips_mulr_q_w_ARG180 %1 = load <4 x i32>, ptr @llvm_mips_mulr_q_w_ARG281 %2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)82 store <4 x i32> %2, ptr @llvm_mips_mulr_q_w_RES83 ret void84}85 86declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind87 88; CHECK: llvm_mips_mulr_q_w_test:89; CHECK: ld.w90; CHECK: ld.w91; CHECK: mulr_q.w92; CHECK: st.w93; CHECK: .size llvm_mips_mulr_q_w_test94;95