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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS3; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL4; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL5; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL6 7define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind {8; ALL-LABEL: add_v16i8:9; ALL: # %bb.0:10; ALL-NEXT: ld.b $w0, 0($6)11; ALL-NEXT: ld.b $w1, 0($5)12; ALL-NEXT: addv.b $w0, $w1, $w013; ALL-NEXT: jr $ra14; ALL-NEXT: st.b $w0, 0($4)15 %1 = load <16 x i8>, ptr %a16 %2 = load <16 x i8>, ptr %b17 %3 = add <16 x i8> %1, %218 store <16 x i8> %3, ptr %c19 ret void20}21 22define void @add_v8i16(ptr %c, ptr %a, ptr %b) nounwind {23; ALL-LABEL: add_v8i16:24; ALL: # %bb.0:25; ALL-NEXT: ld.h $w0, 0($6)26; ALL-NEXT: ld.h $w1, 0($5)27; ALL-NEXT: addv.h $w0, $w1, $w028; ALL-NEXT: jr $ra29; ALL-NEXT: st.h $w0, 0($4)30 %1 = load <8 x i16>, ptr %a31 %2 = load <8 x i16>, ptr %b32 %3 = add <8 x i16> %1, %233 store <8 x i16> %3, ptr %c34 ret void35}36 37define void @add_v4i32(ptr %c, ptr %a, ptr %b) nounwind {38; ALL-LABEL: add_v4i32:39; ALL: # %bb.0:40; ALL-NEXT: ld.w $w0, 0($6)41; ALL-NEXT: ld.w $w1, 0($5)42; ALL-NEXT: addv.w $w0, $w1, $w043; ALL-NEXT: jr $ra44; ALL-NEXT: st.w $w0, 0($4)45 %1 = load <4 x i32>, ptr %a46 %2 = load <4 x i32>, ptr %b47 %3 = add <4 x i32> %1, %248 store <4 x i32> %3, ptr %c49 ret void50}51 52define void @add_v2i64(ptr %c, ptr %a, ptr %b) nounwind {53; ALL-LABEL: add_v2i64:54; ALL: # %bb.0:55; ALL-NEXT: ld.d $w0, 0($6)56; ALL-NEXT: ld.d $w1, 0($5)57; ALL-NEXT: addv.d $w0, $w1, $w058; ALL-NEXT: jr $ra59; ALL-NEXT: st.d $w0, 0($4)60 %1 = load <2 x i64>, ptr %a61 %2 = load <2 x i64>, ptr %b62 %3 = add <2 x i64> %1, %263 store <2 x i64> %3, ptr %c64 ret void65}66 67define void @add_v16i8_i(ptr %c, ptr %a) nounwind {68; ALL-LABEL: add_v16i8_i:69; ALL: # %bb.0:70; ALL-NEXT: ld.b $w0, 0($5)71; ALL-NEXT: addvi.b $w0, $w0, 172; ALL-NEXT: jr $ra73; ALL-NEXT: st.b $w0, 0($4)74 %1 = load <16 x i8>, ptr %a75 %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,76 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>77 store <16 x i8> %2, ptr %c78 ret void79}80 81define void @add_v8i16_i(ptr %c, ptr %a) nounwind {82; ALL-LABEL: add_v8i16_i:83; ALL: # %bb.0:84; ALL-NEXT: ld.h $w0, 0($5)85; ALL-NEXT: addvi.h $w0, $w0, 186; ALL-NEXT: jr $ra87; ALL-NEXT: st.h $w0, 0($4)88 %1 = load <8 x i16>, ptr %a89 %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,90 i16 1, i16 1, i16 1, i16 1>91 store <8 x i16> %2, ptr %c92 ret void93}94 95define void @add_v4i32_i(ptr %c, ptr %a) nounwind {96; ALL-LABEL: add_v4i32_i:97; ALL: # %bb.0:98; ALL-NEXT: ld.w $w0, 0($5)99; ALL-NEXT: addvi.w $w0, $w0, 1100; ALL-NEXT: jr $ra101; ALL-NEXT: st.w $w0, 0($4)102 %1 = load <4 x i32>, ptr %a103 %2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>104 store <4 x i32> %2, ptr %c105 ret void106}107 108define void @add_v2i64_i(ptr %c, ptr %a) nounwind {109; ALL-LABEL: add_v2i64_i:110; ALL: # %bb.0:111; ALL-NEXT: ld.d $w0, 0($5)112; ALL-NEXT: addvi.d $w0, $w0, 1113; ALL-NEXT: jr $ra114; ALL-NEXT: st.d $w0, 0($4)115 %1 = load <2 x i64>, ptr %a116 %2 = add <2 x i64> %1, <i64 1, i64 1>117 store <2 x i64> %2, ptr %c118 ret void119}120 121define void @sub_v16i8(ptr %c, ptr %a, ptr %b) nounwind {122; ALL-LABEL: sub_v16i8:123; ALL: # %bb.0:124; ALL-NEXT: ld.b $w0, 0($6)125; ALL-NEXT: ld.b $w1, 0($5)126; ALL-NEXT: subv.b $w0, $w1, $w0127; ALL-NEXT: jr $ra128; ALL-NEXT: st.b $w0, 0($4)129 %1 = load <16 x i8>, ptr %a130 %2 = load <16 x i8>, ptr %b131 %3 = sub <16 x i8> %1, %2132 store <16 x i8> %3, ptr %c133 ret void134}135 136define void @sub_v8i16(ptr %c, ptr %a, ptr %b) nounwind {137; ALL-LABEL: sub_v8i16:138; ALL: # %bb.0:139; ALL-NEXT: ld.h $w0, 0($6)140; ALL-NEXT: ld.h $w1, 0($5)141; ALL-NEXT: subv.h $w0, $w1, $w0142; ALL-NEXT: jr $ra143; ALL-NEXT: st.h $w0, 0($4)144 %1 = load <8 x i16>, ptr %a145 %2 = load <8 x i16>, ptr %b146 %3 = sub <8 x i16> %1, %2147 store <8 x i16> %3, ptr %c148 ret void149}150 151define void @sub_v4i32(ptr %c, ptr %a, ptr %b) nounwind {152; ALL-LABEL: sub_v4i32:153; ALL: # %bb.0:154; ALL-NEXT: ld.w $w0, 0($6)155; ALL-NEXT: ld.w $w1, 0($5)156; ALL-NEXT: subv.w $w0, $w1, $w0157; ALL-NEXT: jr $ra158; ALL-NEXT: st.w $w0, 0($4)159 %1 = load <4 x i32>, ptr %a160 %2 = load <4 x i32>, ptr %b161 %3 = sub <4 x i32> %1, %2162 store <4 x i32> %3, ptr %c163 ret void164}165 166define void @sub_v2i64(ptr %c, ptr %a, ptr %b) nounwind {167; ALL-LABEL: sub_v2i64:168; ALL: # %bb.0:169; ALL-NEXT: ld.d $w0, 0($6)170; ALL-NEXT: ld.d $w1, 0($5)171; ALL-NEXT: subv.d $w0, $w1, $w0172; ALL-NEXT: jr $ra173; ALL-NEXT: st.d $w0, 0($4)174 %1 = load <2 x i64>, ptr %a175 %2 = load <2 x i64>, ptr %b176 %3 = sub <2 x i64> %1, %2177 store <2 x i64> %3, ptr %c178 ret void179}180 181define void @sub_v16i8_i(ptr %c, ptr %a) nounwind {182; ALL-LABEL: sub_v16i8_i:183; ALL: # %bb.0:184; ALL-NEXT: ld.b $w0, 0($5)185; ALL-NEXT: subvi.b $w0, $w0, 1186; ALL-NEXT: jr $ra187; ALL-NEXT: st.b $w0, 0($4)188 %1 = load <16 x i8>, ptr %a189 %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,190 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>191 store <16 x i8> %2, ptr %c192 ret void193}194 195define void @sub_v16i8_i_negated(ptr %c, ptr %a) nounwind {196; ALL-LABEL: sub_v16i8_i_negated:197; ALL: # %bb.0:198; ALL-NEXT: ld.b $w0, 0($5)199; ALL-NEXT: subvi.b $w0, $w0, 1200; ALL-NEXT: jr $ra201; ALL-NEXT: st.b $w0, 0($4)202 %1 = load <16 x i8>, ptr %a203 %2 = add <16 x i8> %1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,204 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>205 store <16 x i8> %2, ptr %c206 ret void207}208 209define void @sub_v8i16_i(ptr %c, ptr %a) nounwind {210; ALL-LABEL: sub_v8i16_i:211; ALL: # %bb.0:212; ALL-NEXT: ld.h $w0, 0($5)213; ALL-NEXT: subvi.h $w0, $w0, 1214; ALL-NEXT: jr $ra215; ALL-NEXT: st.h $w0, 0($4)216 %1 = load <8 x i16>, ptr %a217 %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,218 i16 1, i16 1, i16 1, i16 1>219 store <8 x i16> %2, ptr %c220 ret void221}222 223define void @sub_v8i16_i_negated(ptr %c, ptr %a) nounwind {224; ALL-LABEL: sub_v8i16_i_negated:225; ALL: # %bb.0:226; ALL-NEXT: ld.h $w0, 0($5)227; ALL-NEXT: subvi.h $w0, $w0, 1228; ALL-NEXT: jr $ra229; ALL-NEXT: st.h $w0, 0($4)230 %1 = load <8 x i16>, ptr %a231 %2 = add <8 x i16> %1, <i16 -1, i16 -1, i16 -1, i16 -1,232 i16 -1, i16 -1, i16 -1, i16 -1>233 store <8 x i16> %2, ptr %c234 ret void235}236 237define void @sub_v4i32_i(ptr %c, ptr %a) nounwind {238; ALL-LABEL: sub_v4i32_i:239; ALL: # %bb.0:240; ALL-NEXT: ld.w $w0, 0($5)241; ALL-NEXT: subvi.w $w0, $w0, 1242; ALL-NEXT: jr $ra243; ALL-NEXT: st.w $w0, 0($4)244 %1 = load <4 x i32>, ptr %a245 %2 = sub <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>246 store <4 x i32> %2, ptr %c247 ret void248}249 250define void @sub_v4i32_i_negated(ptr %c, ptr %a) nounwind {251; ALL-LABEL: sub_v4i32_i_negated:252; ALL: # %bb.0:253; ALL-NEXT: ld.w $w0, 0($5)254; ALL-NEXT: subvi.w $w0, $w0, 1255; ALL-NEXT: jr $ra256; ALL-NEXT: st.w $w0, 0($4)257 %1 = load <4 x i32>, ptr %a258 %2 = add <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>259 store <4 x i32> %2, ptr %c260 ret void261}262 263define void @sub_v2i64_i(ptr %c, ptr %a) nounwind {264; ALL-LABEL: sub_v2i64_i:265; ALL: # %bb.0:266; ALL-NEXT: ld.d $w0, 0($5)267; ALL-NEXT: subvi.d $w0, $w0, 1268; ALL-NEXT: jr $ra269; ALL-NEXT: st.d $w0, 0($4)270 %1 = load <2 x i64>, ptr %a271 %2 = sub <2 x i64> %1, <i64 1, i64 1>272 store <2 x i64> %2, ptr %c273 ret void274}275 276define void @sub_v2i64_i_negated(ptr %c, ptr %a) nounwind {277; MIPS-LABEL: sub_v2i64_i_negated:278; MIPS: # %bb.0:279; MIPS-NEXT: ldi.b $w0, -1280; MIPS-NEXT: shf.w $w0, $w0, 177281; MIPS-NEXT: ld.d $w1, 0($5)282; MIPS-NEXT: addv.d $w0, $w1, $w0283; MIPS-NEXT: jr $ra284; MIPS-NEXT: st.d $w0, 0($4)285;286; MIPSEL-LABEL: sub_v2i64_i_negated:287; MIPSEL: # %bb.0:288; MIPSEL-NEXT: ldi.b $w0, -1289; MIPSEL-NEXT: ld.d $w1, 0($5)290; MIPSEL-NEXT: addv.d $w0, $w1, $w0291; MIPSEL-NEXT: jr $ra292; MIPSEL-NEXT: st.d $w0, 0($4)293 %1 = load <2 x i64>, ptr %a294 %2 = add <2 x i64> %1, <i64 -1, i64 -1>295 store <2 x i64> %2, ptr %c296 ret void297}298 299define void @mul_v16i8(ptr %c, ptr %a, ptr %b) nounwind {300; ALL-LABEL: mul_v16i8:301; ALL: # %bb.0:302; ALL-NEXT: ld.b $w0, 0($6)303; ALL-NEXT: ld.b $w1, 0($5)304; ALL-NEXT: mulv.b $w0, $w1, $w0305; ALL-NEXT: jr $ra306; ALL-NEXT: st.b $w0, 0($4)307 %1 = load <16 x i8>, ptr %a308 %2 = load <16 x i8>, ptr %b309 %3 = mul <16 x i8> %1, %2310 store <16 x i8> %3, ptr %c311 ret void312}313 314define void @mul_v8i16(ptr %c, ptr %a, ptr %b) nounwind {315; ALL-LABEL: mul_v8i16:316; ALL: # %bb.0:317; ALL-NEXT: ld.h $w0, 0($6)318; ALL-NEXT: ld.h $w1, 0($5)319; ALL-NEXT: mulv.h $w0, $w1, $w0320; ALL-NEXT: jr $ra321; ALL-NEXT: st.h $w0, 0($4)322 %1 = load <8 x i16>, ptr %a323 %2 = load <8 x i16>, ptr %b324 %3 = mul <8 x i16> %1, %2325 store <8 x i16> %3, ptr %c326 ret void327}328 329define void @mul_v4i32(ptr %c, ptr %a, ptr %b) nounwind {330; ALL-LABEL: mul_v4i32:331; ALL: # %bb.0:332; ALL-NEXT: ld.w $w0, 0($6)333; ALL-NEXT: ld.w $w1, 0($5)334; ALL-NEXT: mulv.w $w0, $w1, $w0335; ALL-NEXT: jr $ra336; ALL-NEXT: st.w $w0, 0($4)337 %1 = load <4 x i32>, ptr %a338 %2 = load <4 x i32>, ptr %b339 %3 = mul <4 x i32> %1, %2340 store <4 x i32> %3, ptr %c341 ret void342}343 344define void @mul_v2i64(ptr %c, ptr %a, ptr %b) nounwind {345; ALL-LABEL: mul_v2i64:346; ALL: # %bb.0:347; ALL-NEXT: ld.d $w0, 0($6)348; ALL-NEXT: ld.d $w1, 0($5)349; ALL-NEXT: mulv.d $w0, $w1, $w0350; ALL-NEXT: jr $ra351; ALL-NEXT: st.d $w0, 0($4)352 %1 = load <2 x i64>, ptr %a353 %2 = load <2 x i64>, ptr %b354 %3 = mul <2 x i64> %1, %2355 store <2 x i64> %3, ptr %c356 ret void357}358 359define void @maddv_v16i8(ptr %d, ptr %a, ptr %b,360; ALL-LABEL: maddv_v16i8:361; ALL: # %bb.0:362; ALL-NEXT: ld.b $w0, 0($7)363; ALL-NEXT: ld.b $w1, 0($6)364; ALL-NEXT: ld.b $w2, 0($5)365; ALL-NEXT: maddv.b $w2, $w1, $w0366; ALL-NEXT: jr $ra367; ALL-NEXT: st.b $w2, 0($4)368 ptr %c) nounwind {369 %1 = load <16 x i8>, ptr %a370 %2 = load <16 x i8>, ptr %b371 %3 = load <16 x i8>, ptr %c372 %4 = mul <16 x i8> %2, %3373 %5 = add <16 x i8> %4, %1374 store <16 x i8> %5, ptr %d375 ret void376}377 378define void @maddv_v8i16(ptr %d, ptr %a, ptr %b,379; ALL-LABEL: maddv_v8i16:380; ALL: # %bb.0:381; ALL-NEXT: ld.h $w0, 0($7)382; ALL-NEXT: ld.h $w1, 0($6)383; ALL-NEXT: ld.h $w2, 0($5)384; ALL-NEXT: maddv.h $w2, $w1, $w0385; ALL-NEXT: jr $ra386; ALL-NEXT: st.h $w2, 0($4)387 ptr %c) nounwind {388 %1 = load <8 x i16>, ptr %a389 %2 = load <8 x i16>, ptr %b390 %3 = load <8 x i16>, ptr %c391 %4 = mul <8 x i16> %2, %3392 %5 = add <8 x i16> %4, %1393 store <8 x i16> %5, ptr %d394 ret void395}396 397define void @maddv_v4i32(ptr %d, ptr %a, ptr %b,398; ALL-LABEL: maddv_v4i32:399; ALL: # %bb.0:400; ALL-NEXT: ld.w $w0, 0($7)401; ALL-NEXT: ld.w $w1, 0($6)402; ALL-NEXT: ld.w $w2, 0($5)403; ALL-NEXT: maddv.w $w2, $w1, $w0404; ALL-NEXT: jr $ra405; ALL-NEXT: st.w $w2, 0($4)406 ptr %c) nounwind {407 %1 = load <4 x i32>, ptr %a408 %2 = load <4 x i32>, ptr %b409 %3 = load <4 x i32>, ptr %c410 %4 = mul <4 x i32> %2, %3411 %5 = add <4 x i32> %4, %1412 store <4 x i32> %5, ptr %d413 ret void414}415 416define void @maddv_v2i64(ptr %d, ptr %a, ptr %b,417; ALL-LABEL: maddv_v2i64:418; ALL: # %bb.0:419; ALL-NEXT: ld.d $w0, 0($7)420; ALL-NEXT: ld.d $w1, 0($6)421; ALL-NEXT: ld.d $w2, 0($5)422; ALL-NEXT: maddv.d $w2, $w1, $w0423; ALL-NEXT: jr $ra424; ALL-NEXT: st.d $w2, 0($4)425 ptr %c) nounwind {426 %1 = load <2 x i64>, ptr %a427 %2 = load <2 x i64>, ptr %b428 %3 = load <2 x i64>, ptr %c429 %4 = mul <2 x i64> %2, %3430 %5 = add <2 x i64> %4, %1431 store <2 x i64> %5, ptr %d432 ret void433}434 435define void @msubv_v16i8(ptr %d, ptr %a, ptr %b,436; ALL-LABEL: msubv_v16i8:437; ALL: # %bb.0:438; ALL-NEXT: ld.b $w0, 0($7)439; ALL-NEXT: ld.b $w1, 0($6)440; ALL-NEXT: ld.b $w2, 0($5)441; ALL-NEXT: msubv.b $w2, $w1, $w0442; ALL-NEXT: jr $ra443; ALL-NEXT: st.b $w2, 0($4)444 ptr %c) nounwind {445 %1 = load <16 x i8>, ptr %a446 %2 = load <16 x i8>, ptr %b447 %3 = load <16 x i8>, ptr %c448 %4 = mul <16 x i8> %2, %3449 %5 = sub <16 x i8> %1, %4450 store <16 x i8> %5, ptr %d451 ret void452}453 454define void @msubv_v8i16(ptr %d, ptr %a, ptr %b,455; ALL-LABEL: msubv_v8i16:456; ALL: # %bb.0:457; ALL-NEXT: ld.h $w0, 0($7)458; ALL-NEXT: ld.h $w1, 0($6)459; ALL-NEXT: ld.h $w2, 0($5)460; ALL-NEXT: msubv.h $w2, $w1, $w0461; ALL-NEXT: jr $ra462; ALL-NEXT: st.h $w2, 0($4)463 ptr %c) nounwind {464 %1 = load <8 x i16>, ptr %a465 %2 = load <8 x i16>, ptr %b466 %3 = load <8 x i16>, ptr %c467 %4 = mul <8 x i16> %2, %3468 %5 = sub <8 x i16> %1, %4469 store <8 x i16> %5, ptr %d470 ret void471}472 473define void @msubv_v4i32(ptr %d, ptr %a, ptr %b,474; ALL-LABEL: msubv_v4i32:475; ALL: # %bb.0:476; ALL-NEXT: ld.w $w0, 0($7)477; ALL-NEXT: ld.w $w1, 0($6)478; ALL-NEXT: ld.w $w2, 0($5)479; ALL-NEXT: msubv.w $w2, $w1, $w0480; ALL-NEXT: jr $ra481; ALL-NEXT: st.w $w2, 0($4)482 ptr %c) nounwind {483 %1 = load <4 x i32>, ptr %a484 %2 = load <4 x i32>, ptr %b485 %3 = load <4 x i32>, ptr %c486 %4 = mul <4 x i32> %2, %3487 %5 = sub <4 x i32> %1, %4488 store <4 x i32> %5, ptr %d489 ret void490}491 492define void @msubv_v2i64(ptr %d, ptr %a, ptr %b,493; ALL-LABEL: msubv_v2i64:494; ALL: # %bb.0:495; ALL-NEXT: ld.d $w0, 0($7)496; ALL-NEXT: ld.d $w1, 0($6)497; ALL-NEXT: ld.d $w2, 0($5)498; ALL-NEXT: msubv.d $w2, $w1, $w0499; ALL-NEXT: jr $ra500; ALL-NEXT: st.d $w2, 0($4)501 ptr %c) nounwind {502 %1 = load <2 x i64>, ptr %a503 %2 = load <2 x i64>, ptr %b504 %3 = load <2 x i64>, ptr %c505 %4 = mul <2 x i64> %2, %3506 %5 = sub <2 x i64> %1, %4507 store <2 x i64> %5, ptr %d508 ret void509}510 511define void @div_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {512; ALL-LABEL: div_s_v16i8:513; ALL: # %bb.0:514; ALL-NEXT: ld.b $w0, 0($6)515; ALL-NEXT: ld.b $w1, 0($5)516; ALL-NEXT: div_s.b $w0, $w1, $w0517; ALL-NEXT: jr $ra518; ALL-NEXT: st.b $w0, 0($4)519 %1 = load <16 x i8>, ptr %a520 %2 = load <16 x i8>, ptr %b521 %3 = sdiv <16 x i8> %1, %2522 store <16 x i8> %3, ptr %c523 ret void524}525 526define void @div_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {527; ALL-LABEL: div_s_v8i16:528; ALL: # %bb.0:529; ALL-NEXT: ld.h $w0, 0($6)530; ALL-NEXT: ld.h $w1, 0($5)531; ALL-NEXT: div_s.h $w0, $w1, $w0532; ALL-NEXT: jr $ra533; ALL-NEXT: st.h $w0, 0($4)534 %1 = load <8 x i16>, ptr %a535 %2 = load <8 x i16>, ptr %b536 %3 = sdiv <8 x i16> %1, %2537 store <8 x i16> %3, ptr %c538 ret void539}540 541define void @div_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {542; ALL-LABEL: div_s_v4i32:543; ALL: # %bb.0:544; ALL-NEXT: ld.w $w0, 0($6)545; ALL-NEXT: ld.w $w1, 0($5)546; ALL-NEXT: div_s.w $w0, $w1, $w0547; ALL-NEXT: jr $ra548; ALL-NEXT: st.w $w0, 0($4)549 %1 = load <4 x i32>, ptr %a550 %2 = load <4 x i32>, ptr %b551 %3 = sdiv <4 x i32> %1, %2552 store <4 x i32> %3, ptr %c553 ret void554}555 556define void @div_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {557; ALL-LABEL: div_s_v2i64:558; ALL: # %bb.0:559; ALL-NEXT: ld.d $w0, 0($6)560; ALL-NEXT: ld.d $w1, 0($5)561; ALL-NEXT: div_s.d $w0, $w1, $w0562; ALL-NEXT: jr $ra563; ALL-NEXT: st.d $w0, 0($4)564 %1 = load <2 x i64>, ptr %a565 %2 = load <2 x i64>, ptr %b566 %3 = sdiv <2 x i64> %1, %2567 store <2 x i64> %3, ptr %c568 ret void569}570 571define void @div_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {572; ALL-LABEL: div_u_v16i8:573; ALL: # %bb.0:574; ALL-NEXT: ld.b $w0, 0($6)575; ALL-NEXT: ld.b $w1, 0($5)576; ALL-NEXT: div_u.b $w0, $w1, $w0577; ALL-NEXT: jr $ra578; ALL-NEXT: st.b $w0, 0($4)579 %1 = load <16 x i8>, ptr %a580 %2 = load <16 x i8>, ptr %b581 %3 = udiv <16 x i8> %1, %2582 store <16 x i8> %3, ptr %c583 ret void584}585 586define void @div_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {587; ALL-LABEL: div_u_v8i16:588; ALL: # %bb.0:589; ALL-NEXT: ld.h $w0, 0($6)590; ALL-NEXT: ld.h $w1, 0($5)591; ALL-NEXT: div_u.h $w0, $w1, $w0592; ALL-NEXT: jr $ra593; ALL-NEXT: st.h $w0, 0($4)594 %1 = load <8 x i16>, ptr %a595 %2 = load <8 x i16>, ptr %b596 %3 = udiv <8 x i16> %1, %2597 store <8 x i16> %3, ptr %c598 ret void599}600 601define void @div_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {602; ALL-LABEL: div_u_v4i32:603; ALL: # %bb.0:604; ALL-NEXT: ld.w $w0, 0($6)605; ALL-NEXT: ld.w $w1, 0($5)606; ALL-NEXT: div_u.w $w0, $w1, $w0607; ALL-NEXT: jr $ra608; ALL-NEXT: st.w $w0, 0($4)609 %1 = load <4 x i32>, ptr %a610 %2 = load <4 x i32>, ptr %b611 %3 = udiv <4 x i32> %1, %2612 store <4 x i32> %3, ptr %c613 ret void614}615 616define void @div_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {617; ALL-LABEL: div_u_v2i64:618; ALL: # %bb.0:619; ALL-NEXT: ld.d $w0, 0($6)620; ALL-NEXT: ld.d $w1, 0($5)621; ALL-NEXT: div_u.d $w0, $w1, $w0622; ALL-NEXT: jr $ra623; ALL-NEXT: st.d $w0, 0($4)624 %1 = load <2 x i64>, ptr %a625 %2 = load <2 x i64>, ptr %b626 %3 = udiv <2 x i64> %1, %2627 store <2 x i64> %3, ptr %c628 ret void629}630 631define void @mod_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {632; ALL-LABEL: mod_s_v16i8:633; ALL: # %bb.0:634; ALL-NEXT: ld.b $w0, 0($6)635; ALL-NEXT: ld.b $w1, 0($5)636; ALL-NEXT: mod_s.b $w0, $w1, $w0637; ALL-NEXT: jr $ra638; ALL-NEXT: st.b $w0, 0($4)639 %1 = load <16 x i8>, ptr %a640 %2 = load <16 x i8>, ptr %b641 %3 = srem <16 x i8> %1, %2642 store <16 x i8> %3, ptr %c643 ret void644}645 646define void @mod_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {647; ALL-LABEL: mod_s_v8i16:648; ALL: # %bb.0:649; ALL-NEXT: ld.h $w0, 0($6)650; ALL-NEXT: ld.h $w1, 0($5)651; ALL-NEXT: mod_s.h $w0, $w1, $w0652; ALL-NEXT: jr $ra653; ALL-NEXT: st.h $w0, 0($4)654 %1 = load <8 x i16>, ptr %a655 %2 = load <8 x i16>, ptr %b656 %3 = srem <8 x i16> %1, %2657 store <8 x i16> %3, ptr %c658 ret void659}660 661define void @mod_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {662; ALL-LABEL: mod_s_v4i32:663; ALL: # %bb.0:664; ALL-NEXT: ld.w $w0, 0($6)665; ALL-NEXT: ld.w $w1, 0($5)666; ALL-NEXT: mod_s.w $w0, $w1, $w0667; ALL-NEXT: jr $ra668; ALL-NEXT: st.w $w0, 0($4)669 %1 = load <4 x i32>, ptr %a670 %2 = load <4 x i32>, ptr %b671 %3 = srem <4 x i32> %1, %2672 store <4 x i32> %3, ptr %c673 ret void674}675 676define void @mod_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {677; ALL-LABEL: mod_s_v2i64:678; ALL: # %bb.0:679; ALL-NEXT: ld.d $w0, 0($6)680; ALL-NEXT: ld.d $w1, 0($5)681; ALL-NEXT: mod_s.d $w0, $w1, $w0682; ALL-NEXT: jr $ra683; ALL-NEXT: st.d $w0, 0($4)684 %1 = load <2 x i64>, ptr %a685 %2 = load <2 x i64>, ptr %b686 %3 = srem <2 x i64> %1, %2687 store <2 x i64> %3, ptr %c688 ret void689}690 691define void @mod_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {692; ALL-LABEL: mod_u_v16i8:693; ALL: # %bb.0:694; ALL-NEXT: ld.b $w0, 0($6)695; ALL-NEXT: ld.b $w1, 0($5)696; ALL-NEXT: mod_u.b $w0, $w1, $w0697; ALL-NEXT: jr $ra698; ALL-NEXT: st.b $w0, 0($4)699 %1 = load <16 x i8>, ptr %a700 %2 = load <16 x i8>, ptr %b701 %3 = urem <16 x i8> %1, %2702 store <16 x i8> %3, ptr %c703 ret void704}705 706define void @mod_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {707; ALL-LABEL: mod_u_v8i16:708; ALL: # %bb.0:709; ALL-NEXT: ld.h $w0, 0($6)710; ALL-NEXT: ld.h $w1, 0($5)711; ALL-NEXT: mod_u.h $w0, $w1, $w0712; ALL-NEXT: jr $ra713; ALL-NEXT: st.h $w0, 0($4)714 %1 = load <8 x i16>, ptr %a715 %2 = load <8 x i16>, ptr %b716 %3 = urem <8 x i16> %1, %2717 store <8 x i16> %3, ptr %c718 ret void719}720 721define void @mod_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {722; ALL-LABEL: mod_u_v4i32:723; ALL: # %bb.0:724; ALL-NEXT: ld.w $w0, 0($6)725; ALL-NEXT: ld.w $w1, 0($5)726; ALL-NEXT: mod_u.w $w0, $w1, $w0727; ALL-NEXT: jr $ra728; ALL-NEXT: st.w $w0, 0($4)729 %1 = load <4 x i32>, ptr %a730 %2 = load <4 x i32>, ptr %b731 %3 = urem <4 x i32> %1, %2732 store <4 x i32> %3, ptr %c733 ret void734}735 736define void @mod_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {737; ALL-LABEL: mod_u_v2i64:738; ALL: # %bb.0:739; ALL-NEXT: ld.d $w0, 0($6)740; ALL-NEXT: ld.d $w1, 0($5)741; ALL-NEXT: mod_u.d $w0, $w1, $w0742; ALL-NEXT: jr $ra743; ALL-NEXT: st.d $w0, 0($4)744 %1 = load <2 x i64>, ptr %a745 %2 = load <2 x i64>, ptr %b746 %3 = urem <2 x i64> %1, %2747 store <2 x i64> %3, ptr %c748 ret void749}750