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1; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s2; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s3 4define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind {5 ; CHECK: add_v4f32:6 7 %1 = load <4 x float>, ptr %a8 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)9 %2 = load <4 x float>, ptr %b10 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)11 %3 = fadd <4 x float> %1, %212 ; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]13 store <4 x float> %3, ptr %c14 ; CHECK-DAG: st.w [[R3]], 0($4)15 16 ret void17 ; CHECK: .size add_v4f3218}19 20define void @add_v2f64(ptr %c, ptr %a, ptr %b) nounwind {21 ; CHECK: add_v2f64:22 23 %1 = load <2 x double>, ptr %a24 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)25 %2 = load <2 x double>, ptr %b26 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)27 %3 = fadd <2 x double> %1, %228 ; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]29 store <2 x double> %3, ptr %c30 ; CHECK-DAG: st.d [[R3]], 0($4)31 32 ret void33 ; CHECK: .size add_v2f6434}35 36define void @sub_v4f32(ptr %c, ptr %a, ptr %b) nounwind {37 ; CHECK: sub_v4f32:38 39 %1 = load <4 x float>, ptr %a40 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)41 %2 = load <4 x float>, ptr %b42 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)43 %3 = fsub <4 x float> %1, %244 ; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]45 store <4 x float> %3, ptr %c46 ; CHECK-DAG: st.w [[R3]], 0($4)47 48 ret void49 ; CHECK: .size sub_v4f3250}51 52define void @sub_v2f64(ptr %c, ptr %a, ptr %b) nounwind {53 ; CHECK: sub_v2f64:54 55 %1 = load <2 x double>, ptr %a56 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)57 %2 = load <2 x double>, ptr %b58 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)59 %3 = fsub <2 x double> %1, %260 ; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]61 store <2 x double> %3, ptr %c62 ; CHECK-DAG: st.d [[R3]], 0($4)63 64 ret void65 ; CHECK: .size sub_v2f6466}67 68define void @mul_v4f32(ptr %c, ptr %a, ptr %b) nounwind {69 ; CHECK: mul_v4f32:70 71 %1 = load <4 x float>, ptr %a72 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)73 %2 = load <4 x float>, ptr %b74 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)75 %3 = fmul <4 x float> %1, %276 ; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]77 store <4 x float> %3, ptr %c78 ; CHECK-DAG: st.w [[R3]], 0($4)79 80 ret void81 ; CHECK: .size mul_v4f3282}83 84define void @mul_v2f64(ptr %c, ptr %a, ptr %b) nounwind {85 ; CHECK: mul_v2f64:86 87 %1 = load <2 x double>, ptr %a88 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)89 %2 = load <2 x double>, ptr %b90 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)91 %3 = fmul <2 x double> %1, %292 ; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]93 store <2 x double> %3, ptr %c94 ; CHECK-DAG: st.d [[R3]], 0($4)95 96 ret void97 ; CHECK: .size mul_v2f6498}99 100define void @fma_v4f32(ptr %d, ptr %a, ptr %b,101 ptr %c) nounwind {102 ; CHECK: fma_v4f32:103 104 %1 = load <4 x float>, ptr %a105 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)106 %2 = load <4 x float>, ptr %b107 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)108 %3 = load <4 x float>, ptr %c109 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)110 %4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2,111 <4 x float> %3)112 ; CHECK-DAG: fmadd.w [[R1]], [[R2]], [[R3]]113 store <4 x float> %4, ptr %d114 ; CHECK-DAG: st.w [[R1]], 0($4)115 116 ret void117 ; CHECK: .size fma_v4f32118}119 120define void @fma_v2f64(ptr %d, ptr %a, ptr %b,121 ptr %c) nounwind {122 ; CHECK: fma_v2f64:123 124 %1 = load <2 x double>, ptr %a125 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)126 %2 = load <2 x double>, ptr %b127 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)128 %3 = load <2 x double>, ptr %c129 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)130 %4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2,131 <2 x double> %3)132 ; CHECK-DAG: fmadd.d [[R1]], [[R2]], [[R3]]133 store <2 x double> %4, ptr %d134 ; CHECK-DAG: st.d [[R1]], 0($4)135 136 ret void137 ; CHECK: .size fma_v2f64138}139 140define void @fmlu_fsub_v4f32(ptr %d, ptr %a, ptr %b,141 ptr %c) nounwind {142 ; CHECK: fmlu_fsub_v4f32:143 144 %1 = load <4 x float>, ptr %b145 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($6)146 %2 = load <4 x float>, ptr %c147 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($7)148 %3 = fmul <4 x float> %1, %2149 ; CHECK-DAG: fmul.w [[R2]], [[R1]], [[R2]]150 %4 = load <4 x float>, ptr %a151 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($5)152 %5 = fsub <4 x float> %4, %3153 ; CHECK-DAG: fsub.w [[R2]], [[R3]], [[R2]]154 store <4 x float> %5, ptr %d155 ; CHECK-DAG: st.w [[R2]], 0($4)156 157 ret void158 ; CHECK: .size fmlu_fsub_v4f32159}160 161define void @fmul_fsub_v2f64(ptr %d, ptr %a, ptr %b,162 ptr %c) nounwind {163 ; CHECK: fmul_fsub_v2f64:164 165 %1 = load <2 x double>, ptr %b166 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($7)167 %2 = load <2 x double>, ptr %c168 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)169 %3 = fmul <2 x double> %1, %2170 ; CHECK-DAG: fmul.d [[R1]], [[R2]], [[R1]]171 %4 = load <2 x double>, ptr %a172 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($5)173 %5 = fsub <2 x double> %4, %3174 ; CHECK-DAG: fsub.d [[R1]], [[R3]], [[R1]]175 store <2 x double> %5, ptr %d176 ; CHECK-DAG: st.d [[R1]], 0($4)177 178 ret void179 ; CHECK: .size fmul_fsub_v2f64180}181 182define void @fdiv_v4f32(ptr %c, ptr %a, ptr %b) nounwind {183 ; CHECK: fdiv_v4f32:184 185 %1 = load <4 x float>, ptr %a186 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)187 %2 = load <4 x float>, ptr %b188 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)189 %3 = fdiv <4 x float> %1, %2190 ; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]191 store <4 x float> %3, ptr %c192 ; CHECK-DAG: st.w [[R3]], 0($4)193 194 ret void195 ; CHECK: .size fdiv_v4f32196}197 198define void @fdiv_v2f64(ptr %c, ptr %a, ptr %b) nounwind {199 ; CHECK: fdiv_v2f64:200 201 %1 = load <2 x double>, ptr %a202 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)203 %2 = load <2 x double>, ptr %b204 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)205 %3 = fdiv <2 x double> %1, %2206 ; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]207 store <2 x double> %3, ptr %c208 ; CHECK-DAG: st.d [[R3]], 0($4)209 210 ret void211 ; CHECK: .size fdiv_v2f64212}213 214define void @fabs_v4f32(ptr %c, ptr %a) nounwind {215 ; CHECK: fabs_v4f32:216 217 %1 = load <4 x float>, ptr %a218 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)219 %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)220 ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]221 store <4 x float> %2, ptr %c222 ; CHECK-DAG: st.w [[R3]], 0($4)223 224 ret void225 ; CHECK: .size fabs_v4f32226}227 228define void @fabs_v2f64(ptr %c, ptr %a) nounwind {229 ; CHECK: fabs_v2f64:230 231 %1 = load <2 x double>, ptr %a232 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)233 %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)234 ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]235 store <2 x double> %2, ptr %c236 ; CHECK-DAG: st.d [[R3]], 0($4)237 238 ret void239 ; CHECK: .size fabs_v2f64240}241 242define void @fexp2_v4f32(ptr %c, ptr %a) nounwind {243 ; CHECK: fexp2_v4f32:244 245 %1 = load <4 x float>, ptr %a246 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)247 %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)248 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1249 ; CHECK-DAG: ffint_u.w [[R4:\$w[0-9]+]], [[R3]]250 ; CHECK-DAG: fexp2.w [[R4:\$w[0-9]+]], [[R3]], [[R1]]251 store <4 x float> %2, ptr %c252 ; CHECK-DAG: st.w [[R4]], 0($4)253 254 ret void255 ; CHECK: .size fexp2_v4f32256}257 258define void @fexp2_v2f64(ptr %c, ptr %a) nounwind {259 ; CHECK: fexp2_v2f64:260 261 %1 = load <2 x double>, ptr %a262 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)263 %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)264 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1265 ; CHECK-DAG: ffint_u.d [[R4:\$w[0-9]+]], [[R3]]266 ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]267 store <2 x double> %2, ptr %c268 ; CHECK-DAG: st.d [[R4]], 0($4)269 270 ret void271 ; CHECK: .size fexp2_v2f64272}273 274define void @fexp2_v4f32_2(ptr %c, ptr %a) nounwind {275 ; CHECK: fexp2_v4f32_2:276 277 %1 = load <4 x float>, ptr %a278 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)279 %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)280 %3 = fmul <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, %2281 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1282 ; CHECK-DAG: ffint_u.w [[R4:\$w[0-9]+]], [[R3]]283 ; CHECK-DAG: fexp2.w [[R5:\$w[0-9]+]], [[R4]], [[R1]]284 store <4 x float> %3, ptr %c285 ; CHECK-DAG: st.w [[R5]], 0($4)286 287 ret void288 ; CHECK: .size fexp2_v4f32_2289}290 291define void @fexp2_v2f64_2(ptr %c, ptr %a) nounwind {292 ; CHECK: fexp2_v2f64_2:293 294 %1 = load <2 x double>, ptr %a295 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)296 %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)297 %3 = fmul <2 x double> <double 2.0, double 2.0>, %2298 ; CHECK-DAG: ldi.d [[R2:\$w[0-9]+]], 1299 ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R2]]300 ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]301 store <2 x double> %3, ptr %c302 ; CHECK-DAG: st.d [[R4]], 0($4)303 304 ret void305 ; CHECK: .size fexp2_v2f64_2306}307 308define void @fsqrt_v4f32(ptr %c, ptr %a) nounwind {309 ; CHECK: fsqrt_v4f32:310 311 %1 = load <4 x float>, ptr %a312 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)313 %2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)314 ; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]315 store <4 x float> %2, ptr %c316 ; CHECK-DAG: st.w [[R3]], 0($4)317 318 ret void319 ; CHECK: .size fsqrt_v4f32320}321 322define void @fsqrt_v2f64(ptr %c, ptr %a) nounwind {323 ; CHECK: fsqrt_v2f64:324 325 %1 = load <2 x double>, ptr %a326 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)327 %2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)328 ; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]329 store <2 x double> %2, ptr %c330 ; CHECK-DAG: st.d [[R3]], 0($4)331 332 ret void333 ; CHECK: .size fsqrt_v2f64334}335 336define void @ffint_u_v4f32(ptr %c, ptr %a) nounwind {337 ; CHECK: ffint_u_v4f32:338 339 %1 = load <4 x i32>, ptr %a340 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)341 %2 = uitofp <4 x i32> %1 to <4 x float>342 ; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]]343 store <4 x float> %2, ptr %c344 ; CHECK-DAG: st.w [[R3]], 0($4)345 346 ret void347 ; CHECK: .size ffint_u_v4f32348}349 350define void @ffint_u_v2f64(ptr %c, ptr %a) nounwind {351 ; CHECK: ffint_u_v2f64:352 353 %1 = load <2 x i64>, ptr %a354 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)355 %2 = uitofp <2 x i64> %1 to <2 x double>356 ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]]357 store <2 x double> %2, ptr %c358 ; CHECK-DAG: st.d [[R3]], 0($4)359 360 ret void361 ; CHECK: .size ffint_u_v2f64362}363 364define void @ffint_s_v4f32(ptr %c, ptr %a) nounwind {365 ; CHECK: ffint_s_v4f32:366 367 %1 = load <4 x i32>, ptr %a368 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)369 %2 = sitofp <4 x i32> %1 to <4 x float>370 ; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]]371 store <4 x float> %2, ptr %c372 ; CHECK-DAG: st.w [[R3]], 0($4)373 374 ret void375 ; CHECK: .size ffint_s_v4f32376}377 378define void @ffint_s_v2f64(ptr %c, ptr %a) nounwind {379 ; CHECK: ffint_s_v2f64:380 381 %1 = load <2 x i64>, ptr %a382 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)383 %2 = sitofp <2 x i64> %1 to <2 x double>384 ; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]]385 store <2 x double> %2, ptr %c386 ; CHECK-DAG: st.d [[R3]], 0($4)387 388 ret void389 ; CHECK: .size ffint_s_v2f64390}391 392define void @ftrunc_u_v4f32(ptr %c, ptr %a) nounwind {393 ; CHECK: ftrunc_u_v4f32:394 395 %1 = load <4 x float>, ptr %a396 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)397 %2 = fptoui <4 x float> %1 to <4 x i32>398 ; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]]399 store <4 x i32> %2, ptr %c400 ; CHECK-DAG: st.w [[R3]], 0($4)401 402 ret void403 ; CHECK: .size ftrunc_u_v4f32404}405 406define void @ftrunc_u_v2f64(ptr %c, ptr %a) nounwind {407 ; CHECK: ftrunc_u_v2f64:408 409 %1 = load <2 x double>, ptr %a410 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)411 %2 = fptoui <2 x double> %1 to <2 x i64>412 ; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]]413 store <2 x i64> %2, ptr %c414 ; CHECK-DAG: st.d [[R3]], 0($4)415 416 ret void417 ; CHECK: .size ftrunc_u_v2f64418}419 420define void @ftrunc_s_v4f32(ptr %c, ptr %a) nounwind {421 ; CHECK: ftrunc_s_v4f32:422 423 %1 = load <4 x float>, ptr %a424 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)425 %2 = fptosi <4 x float> %1 to <4 x i32>426 ; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]]427 store <4 x i32> %2, ptr %c428 ; CHECK-DAG: st.w [[R3]], 0($4)429 430 ret void431 ; CHECK: .size ftrunc_s_v4f32432}433 434define void @ftrunc_s_v2f64(ptr %c, ptr %a) nounwind {435 ; CHECK: ftrunc_s_v2f64:436 437 %1 = load <2 x double>, ptr %a438 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)439 %2 = fptosi <2 x double> %1 to <2 x i64>440 ; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]]441 store <2 x i64> %2, ptr %c442 ; CHECK-DAG: st.d [[R3]], 0($4)443 444 ret void445 ; CHECK: .size ftrunc_s_v2f64446}447 448declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val)449declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val)450declare <4 x float> @llvm.exp2.v4f32(<4 x float> %val)451declare <2 x double> @llvm.exp2.v2f64(<2 x double> %val)452declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,453 <4 x float> %c)454declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,455 <2 x double> %c)456declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)457declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)458