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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips64el-linux-gnu -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=MIPSEL64R63; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=MIPSEL32R54 5declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32)6declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32)7 8declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32)9declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32)10 11; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C212; MASK_TYPE1 = C2-C1 0s | 1s | ends with C1 0s13define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64(ptr %a, ptr %b) {14; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64:15; MIPSEL64R6: # %bb.0: # %entry16; MIPSEL64R6-NEXT: ld.d $w0, 0($4)17; MIPSEL64R6-NEXT: srli.d $w0, $w0, 5218; MIPSEL64R6-NEXT: slli.d $w0, $w0, 5119; MIPSEL64R6-NEXT: jr $ra20; MIPSEL64R6-NEXT: st.d $w0, 0($5)21;22; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64:23; MIPSEL32R5: # %bb.0: # %entry24; MIPSEL32R5-NEXT: ld.d $w0, 0($4)25; MIPSEL32R5-NEXT: srli.d $w0, $w0, 5226; MIPSEL32R5-NEXT: slli.d $w0, $w0, 5127; MIPSEL32R5-NEXT: jr $ra28; MIPSEL32R5-NEXT: st.d $w0, 0($5)29entry:30 %0 = load <2 x i64>, ptr %a31 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 52)32 %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 51)33 store <2 x i64> %2, ptr %b34 ret void35}36 37; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C238define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long(ptr %a, ptr %b) {39; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long:40; MIPSEL64R6: # %bb.0: # %entry41; MIPSEL64R6-NEXT: ld.d $w0, 0($4)42; MIPSEL64R6-NEXT: srli.d $w0, $w0, 643; MIPSEL64R6-NEXT: slli.d $w0, $w0, 444; MIPSEL64R6-NEXT: jr $ra45; MIPSEL64R6-NEXT: st.d $w0, 0($5)46;47; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long:48; MIPSEL32R5: # %bb.0: # %entry49; MIPSEL32R5-NEXT: ld.d $w0, 0($4)50; MIPSEL32R5-NEXT: srli.d $w0, $w0, 651; MIPSEL32R5-NEXT: slli.d $w0, $w0, 452; MIPSEL32R5-NEXT: jr $ra53; MIPSEL32R5-NEXT: st.d $w0, 0($5)54entry:55 %0 = load <2 x i64>, ptr %a56 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 6)57 %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 4)58 store <2 x i64> %2, ptr %b59 ret void60}61 62; do not fold (shl (srl x, c1), c2) -> (and (shl x, (sub c1, c2), MASK) if C1 >= C263; MASK_TYPE2 = 1s | C1 zeros64define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32(ptr %a, ptr %b) {65; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32:66; MIPSEL64R6: # %bb.0: # %entry67; MIPSEL64R6-NEXT: ld.d $w0, 0($4)68; MIPSEL64R6-NEXT: srli.d $w0, $w0, 469; MIPSEL64R6-NEXT: slli.d $w0, $w0, 670; MIPSEL64R6-NEXT: jr $ra71; MIPSEL64R6-NEXT: st.d $w0, 0($5)72;73; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32:74; MIPSEL32R5: # %bb.0: # %entry75; MIPSEL32R5-NEXT: ld.d $w0, 0($4)76; MIPSEL32R5-NEXT: srli.d $w0, $w0, 477; MIPSEL32R5-NEXT: slli.d $w0, $w0, 678; MIPSEL32R5-NEXT: jr $ra79; MIPSEL32R5-NEXT: st.d $w0, 0($5)80entry:81 %0 = load <2 x i64>, ptr %a82 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 4)83 %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 6)84 store <2 x i64> %2, ptr %b85 ret void86}87 88; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C289define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long(ptr %a, ptr %b) {90; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long:91; MIPSEL64R6: # %bb.0: # %entry92; MIPSEL64R6-NEXT: ld.w $w0, 0($4)93; MIPSEL64R6-NEXT: srli.w $w0, $w0, 794; MIPSEL64R6-NEXT: slli.w $w0, $w0, 395; MIPSEL64R6-NEXT: jr $ra96; MIPSEL64R6-NEXT: st.w $w0, 0($5)97;98; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long:99; MIPSEL32R5: # %bb.0: # %entry100; MIPSEL32R5-NEXT: ld.w $w0, 0($4)101; MIPSEL32R5-NEXT: srli.w $w0, $w0, 7102; MIPSEL32R5-NEXT: slli.w $w0, $w0, 3103; MIPSEL32R5-NEXT: jr $ra104; MIPSEL32R5-NEXT: st.w $w0, 0($5)105entry:106 %0 = load <4 x i32>, ptr %a107 %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 7)108 %2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 3)109 store <4 x i32> %2, ptr %b110 ret void111}112 113; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))114define void @avoid_to_combine_shifts_to_and_mask_type2_i64_long(ptr %a, ptr %b) {115; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64_long:116; MIPSEL64R6: # %bb.0: # %entry117; MIPSEL64R6-NEXT: ld.d $w0, 0($4)118; MIPSEL64R6-NEXT: srli.d $w0, $w0, 38119; MIPSEL64R6-NEXT: slli.d $w0, $w0, 38120; MIPSEL64R6-NEXT: jr $ra121; MIPSEL64R6-NEXT: st.d $w0, 0($5)122;123; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64_long:124; MIPSEL32R5: # %bb.0: # %entry125; MIPSEL32R5-NEXT: ld.d $w0, 0($4)126; MIPSEL32R5-NEXT: srli.d $w0, $w0, 38127; MIPSEL32R5-NEXT: slli.d $w0, $w0, 38128; MIPSEL32R5-NEXT: jr $ra129; MIPSEL32R5-NEXT: st.d $w0, 0($5)130entry:131 %0 = load <2 x i64>, ptr %a132 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 38)133 %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 38)134 store <2 x i64> %2, ptr %b135 ret void136}137 138; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))139define void @avoid_to_combine_shifts_to_and_mask_type2_i64(ptr %a, ptr %b) {140; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64:141; MIPSEL64R6: # %bb.0: # %entry142; MIPSEL64R6-NEXT: ld.d $w0, 0($4)143; MIPSEL64R6-NEXT: srli.d $w0, $w0, 3144; MIPSEL64R6-NEXT: slli.d $w0, $w0, 3145; MIPSEL64R6-NEXT: jr $ra146; MIPSEL64R6-NEXT: st.d $w0, 0($5)147;148; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64:149; MIPSEL32R5: # %bb.0: # %entry150; MIPSEL32R5-NEXT: ld.d $w0, 0($4)151; MIPSEL32R5-NEXT: srli.d $w0, $w0, 3152; MIPSEL32R5-NEXT: slli.d $w0, $w0, 3153; MIPSEL32R5-NEXT: jr $ra154; MIPSEL32R5-NEXT: st.d $w0, 0($5)155entry:156 %0 = load <2 x i64>, ptr %a157 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 3)158 %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 3)159 store <2 x i64> %2, ptr %b160 ret void161}162 163; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))164define void @avoid_to_combine_shifts_to_and_mask_type1_long_i32_a(ptr %a, ptr %b) {165; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_a:166; MIPSEL64R6: # %bb.0: # %entry167; MIPSEL64R6-NEXT: ld.w $w0, 0($4)168; MIPSEL64R6-NEXT: srli.w $w0, $w0, 5169; MIPSEL64R6-NEXT: slli.w $w0, $w0, 5170; MIPSEL64R6-NEXT: jr $ra171; MIPSEL64R6-NEXT: st.w $w0, 0($5)172;173; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_a:174; MIPSEL32R5: # %bb.0: # %entry175; MIPSEL32R5-NEXT: ld.w $w0, 0($4)176; MIPSEL32R5-NEXT: srli.w $w0, $w0, 5177; MIPSEL32R5-NEXT: slli.w $w0, $w0, 5178; MIPSEL32R5-NEXT: jr $ra179; MIPSEL32R5-NEXT: st.w $w0, 0($5)180entry:181 %0 = load <4 x i32>, ptr %a182 %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 5)183 %2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 5)184 store <4 x i32> %2, ptr %b185 ret void186}187 188; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))189define void @avoid_to_combine_shifts_to_and_mask_type1_long_i32_b(ptr %a, ptr %b) {190; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_b:191; MIPSEL64R6: # %bb.0: # %entry192; MIPSEL64R6-NEXT: ld.w $w0, 0($4)193; MIPSEL64R6-NEXT: srli.w $w0, $w0, 30194; MIPSEL64R6-NEXT: slli.w $w0, $w0, 30195; MIPSEL64R6-NEXT: jr $ra196; MIPSEL64R6-NEXT: st.w $w0, 0($5)197;198; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_b:199; MIPSEL32R5: # %bb.0: # %entry200; MIPSEL32R5-NEXT: ld.w $w0, 0($4)201; MIPSEL32R5-NEXT: srli.w $w0, $w0, 30202; MIPSEL32R5-NEXT: slli.w $w0, $w0, 30203; MIPSEL32R5-NEXT: jr $ra204; MIPSEL32R5-NEXT: st.w $w0, 0($5)205entry:206 %0 = load <4 x i32>, ptr %a207 %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 30)208 %2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 30)209 store <4 x i32> %2, ptr %b210 ret void211}212