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1; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \2; RUN: | FileCheck -check-prefixes=ALL,O32 %s3; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \4; RUN: | FileCheck -check-prefixes=ALL,O32 %s5; RUN: llc -mtriple=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \6; RUN: | FileCheck -check-prefixes=ALL,N32 %s7; RUN: llc -mtriple=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \8; RUN: | FileCheck -check-prefixes=ALL,N32 %s9; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \10; RUN: | FileCheck -check-prefixes=ALL,N64 %s11; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \12; RUN: | FileCheck -check-prefixes=ALL,N64 %s13 14@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>15@v2f64 = global <2 x double> <double 0.0, double 0.0>16@i32 = global i32 017@f32 = global float 0.018@f64 = global double 0.019 20define void @const_v4f32() nounwind {21 ; ALL-LABEL: const_v4f32:22 23 store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, ptr @v4f3224 ; ALL: ldi.b [[R1:\$w[0-9]+]], 025 26 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, ptr @v4f3227 ; ALL: lui [[R1:\$[0-9]+]], 1625628 ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]]29 30 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, ptr @v4f3231 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($32 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L33 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L34 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])35 36 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, ptr @v4f3237 ; ALL: lui [[R1:\$[0-9]+]], 1830438 ; ALL: ori [[R2:\$[0-9]+]], [[R1]], 12839 ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]]40 41 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, ptr @v4f3242 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($43 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L44 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L45 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])46 47 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, ptr @v4f3248 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($49 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L50 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L51 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])52 53 ret void54}55 56define void @const_v2f64() nounwind {57 ; ALL-LABEL: const_v2f64:58 59 store volatile <2 x double> <double 0.0, double 0.0>, ptr @v2f6460 ; ALL: ldi.b [[R1:\$w[0-9]+]], 061 62 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, ptr @v2f6463 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($64 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L65 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L66 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])67 68 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, ptr @v2f6469 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($70 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L71 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L72 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])73 74 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, ptr @v2f6475 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($76 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L77 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L78 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])79 80 store volatile <2 x double> <double 1.0, double 1.0>, ptr @v2f6481 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($82 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L83 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L84 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])85 86 store volatile <2 x double> <double 1.0, double 31.0>, ptr @v2f6487 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($88 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L89 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L90 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])91 92 store volatile <2 x double> <double 3.0, double 4.0>, ptr @v2f6493 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($94 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L95 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L96 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])97 98 ret void99}100 101define void @nonconst_v4f32() nounwind {102 ; ALL-LABEL: nonconst_v4f32:103 104 %1 = load float , ptr @f32105 %2 = insertelement <4 x float> undef, float %1, i32 0106 %3 = insertelement <4 x float> %2, float %1, i32 1107 %4 = insertelement <4 x float> %3, float %1, i32 2108 %5 = insertelement <4 x float> %4, float %1, i32 3109 store volatile <4 x float> %5, ptr @v4f32110 ; ALL: lwc1 $f[[R1:[0-9]+]], 0(111 ; ALL: splati.w [[R2:\$w[0-9]+]], $w[[R1]]112 113 ret void114}115 116define void @nonconst_v2f64() nounwind {117 ; ALL-LABEL: nonconst_v2f64:118 119 %1 = load double , ptr @f64120 %2 = insertelement <2 x double> undef, double %1, i32 0121 %3 = insertelement <2 x double> %2, double %1, i32 1122 store volatile <2 x double> %3, ptr @v2f64123 ; ALL: ldc1 $f[[R1:[0-9]+]], 0(124 ; ALL: splati.d [[R2:\$w[0-9]+]], $w[[R1]]125 126 ret void127}128 129define float @extract_v4f32() nounwind {130 ; ALL-LABEL: extract_v4f32:131 132 %1 = load <4 x float>, ptr @v4f32133 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],134 135 %2 = fadd <4 x float> %1, %1136 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]137 138 %3 = extractelement <4 x float> %2, i32 1139 ; Element 1 can be obtained by splatting it across the vector and extracting140 ; $w0:sub_lo141 ; ALL-DAG: splati.w $w0, [[R1]][1]142 143 ret float %3144}145 146define float @extract_v4f32_elt0() nounwind {147 ; ALL-LABEL: extract_v4f32_elt0:148 149 %1 = load <4 x float>, ptr @v4f32150 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],151 152 %2 = fadd <4 x float> %1, %1153 ; ALL-DAG: fadd.w $w0, [[R1]], [[R1]]154 155 %3 = extractelement <4 x float> %2, i32 0156 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)157 ; ALL-NOT: copy_u.w158 ; ALL-NOT: mtc1159 160 ret float %3161}162 163define float @extract_v4f32_elt2() nounwind {164 ; ALL-LABEL: extract_v4f32_elt2:165 166 %1 = load <4 x float>, ptr @v4f32167 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],168 169 %2 = fadd <4 x float> %1, %1170 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]171 172 %3 = extractelement <4 x float> %2, i32 2173 ; Element 2 can be obtained by splatting it across the vector and extracting174 ; $w0:sub_lo175 ; ALL-DAG: splati.w $w0, [[R1]][2]176 177 ret float %3178}179 180define float @extract_v4f32_vidx() nounwind {181 ; ALL-LABEL: extract_v4f32_vidx:182 183 %1 = load <4 x float>, ptr @v4f32184 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(185 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(186 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(187 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])188 189 %2 = fadd <4 x float> %1, %1190 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]191 192 %3 = load i32, ptr @i32193 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(194 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(195 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(196 197 %4 = extractelement <4 x float> %2, i32 %3198 ; ALL-DAG: splat.w $w0, [[R1]][[[PTR_I]]]199 200 ret float %4201}202 203define double @extract_v2f64() nounwind {204 ; ALL-LABEL: extract_v2f64:205 206 %1 = load <2 x double>, ptr @v2f64207 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],208 209 %2 = fadd <2 x double> %1, %1210 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]211 212 %3 = extractelement <2 x double> %2, i32 1213 ; Element 1 can be obtained by splatting it across the vector and extracting214 ; $w0:sub_64215 ; ALL-DAG: splati.d $w0, [[R1]][1]216 ; ALL-NOT: copy_u.w217 ; ALL-NOT: mtc1218 ; ALL-NOT: mthc1219 ; ALL-NOT: sll220 ; ALL-NOT: sra221 222 ret double %3223}224 225define double @extract_v2f64_elt0() nounwind {226 ; ALL-LABEL: extract_v2f64_elt0:227 228 %1 = load <2 x double>, ptr @v2f64229 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],230 231 %2 = fadd <2 x double> %1, %1232 ; ALL-DAG: fadd.d $w0, [[R1]], [[R1]]233 234 %3 = extractelement <2 x double> %2, i32 0235 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)236 ; ALL-NOT: copy_u.w237 ; ALL-NOT: mtc1238 ; ALL-NOT: mthc1239 ; ALL-NOT: sll240 ; ALL-NOT: sra241 242 ret double %3243}244 245define double @extract_v2f64_vidx() nounwind {246 ; ALL-LABEL: extract_v2f64_vidx:247 248 %1 = load <2 x double>, ptr @v2f64249 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(250 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(251 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(252 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])253 254 %2 = fadd <2 x double> %1, %1255 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]256 257 %3 = load i32, ptr @i32258 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(259 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(260 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(261 262 %4 = extractelement <2 x double> %2, i32 %3263 ; ALL-DAG: splat.d $w0, [[R1]][[[PTR_I]]]264 265 ret double %4266}267 268define void @insert_v4f32(float %a) nounwind {269 ; ALL-LABEL: insert_v4f32:270 271 %1 = load <4 x float>, ptr @v4f32272 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],273 274 %2 = insertelement <4 x float> %1, float %a, i32 1275 ; float argument passed in $f12276 ; ALL-DAG: insve.w [[R1]][1], $w12[0]277 278 store volatile <4 x float> %2, ptr @v4f32279 ; ALL-DAG: st.w [[R1]]280 281 ret void282}283 284define void @insert_v2f64(double %a) nounwind {285 ; ALL-LABEL: insert_v2f64:286 287 %1 = load <2 x double>, ptr @v2f64288 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],289 290 %2 = insertelement <2 x double> %1, double %a, i32 1291 ; double argument passed in $f12292 ; ALL-DAG: insve.d [[R1]][1], $w12[0]293 294 store volatile <2 x double> %2, ptr @v2f64295 ; ALL-DAG: st.d [[R1]]296 297 ret void298}299 300define void @insert_v4f32_vidx(float %a) nounwind {301 ; ALL-LABEL: insert_v4f32_vidx:302 303 %1 = load <4 x float>, ptr @v4f32304 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(305 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(306 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(307 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])308 309 %2 = load i32, ptr @i32310 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(311 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(312 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(313 314 %3 = insertelement <4 x float> %1, float %a, i32 %2315 ; float argument passed in $f12316 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[PTR_I]], 2317 ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]318 ; ALL-DAG: insve.w [[R1]][0], $w12[0]319 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]320 ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]321 322 store volatile <4 x float> %3, ptr @v4f32323 ; ALL-DAG: st.w [[R1]]324 325 ret void326}327 328define void @insert_v2f64_vidx(double %a) nounwind {329 ; ALL-LABEL: insert_v2f64_vidx:330 331 %1 = load <2 x double>, ptr @v2f64332 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(333 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(334 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(335 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])336 337 %2 = load i32, ptr @i32338 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(339 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(340 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(341 342 %3 = insertelement <2 x double> %1, double %a, i32 %2343 ; double argument passed in $f12344 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[PTR_I]], 3345 ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]346 ; ALL-DAG: insve.d [[R1]][0], $w12[0]347 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]348 ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]349 350 store volatile <2 x double> %3, ptr @v2f64351 ; ALL-DAG: st.d [[R1]]352 353 ret void354}355