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1; Test the MSA intrinsics that are encoded with the BIT instruction format.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s4; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5 6@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 167@llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 168 9define void @llvm_mips_sat_s_b_test() nounwind {10entry:11 %0 = load <16 x i8>, ptr @llvm_mips_sat_s_b_ARG112 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)13 store <16 x i8> %1, ptr @llvm_mips_sat_s_b_RES14 ret void15}16 17declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind18 19; CHECK: llvm_mips_sat_s_b_test:20; CHECK: ld.b21; CHECK: sat_s.b22; CHECK: st.b23; CHECK: .size llvm_mips_sat_s_b_test24;25@llvm_mips_sat_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1626@llvm_mips_sat_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1627 28define void @llvm_mips_sat_s_h_test() nounwind {29entry:30 %0 = load <8 x i16>, ptr @llvm_mips_sat_s_h_ARG131 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)32 store <8 x i16> %1, ptr @llvm_mips_sat_s_h_RES33 ret void34}35 36declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind37 38; CHECK: llvm_mips_sat_s_h_test:39; CHECK: ld.h40; CHECK: sat_s.h41; CHECK: st.h42; CHECK: .size llvm_mips_sat_s_h_test43;44@llvm_mips_sat_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1645@llvm_mips_sat_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1646 47define void @llvm_mips_sat_s_w_test() nounwind {48entry:49 %0 = load <4 x i32>, ptr @llvm_mips_sat_s_w_ARG150 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)51 store <4 x i32> %1, ptr @llvm_mips_sat_s_w_RES52 ret void53}54 55declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind56 57; CHECK: llvm_mips_sat_s_w_test:58; CHECK: ld.w59; CHECK: sat_s.w60; CHECK: st.w61; CHECK: .size llvm_mips_sat_s_w_test62;63@llvm_mips_sat_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1664@llvm_mips_sat_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 1665 66define void @llvm_mips_sat_s_d_test() nounwind {67entry:68 %0 = load <2 x i64>, ptr @llvm_mips_sat_s_d_ARG169 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)70 store <2 x i64> %1, ptr @llvm_mips_sat_s_d_RES71 ret void72}73 74declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind75 76; CHECK: llvm_mips_sat_s_d_test:77; CHECK: ld.d78; CHECK: sat_s.d79; CHECK: st.d80; CHECK: .size llvm_mips_sat_s_d_test81;82@llvm_mips_sat_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1683@llvm_mips_sat_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1684 85define void @llvm_mips_sat_u_b_test() nounwind {86entry:87 %0 = load <16 x i8>, ptr @llvm_mips_sat_u_b_ARG188 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)89 store <16 x i8> %1, ptr @llvm_mips_sat_u_b_RES90 ret void91}92 93declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind94 95; CHECK: llvm_mips_sat_u_b_test:96; CHECK: ld.b97; CHECK: sat_u.b98; CHECK: st.b99; CHECK: .size llvm_mips_sat_u_b_test100;101@llvm_mips_sat_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16102@llvm_mips_sat_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16103 104define void @llvm_mips_sat_u_h_test() nounwind {105entry:106 %0 = load <8 x i16>, ptr @llvm_mips_sat_u_h_ARG1107 %1 = tail call <8 x i16> @llvm.mips.sat.u.h(<8 x i16> %0, i32 7)108 store <8 x i16> %1, ptr @llvm_mips_sat_u_h_RES109 ret void110}111 112declare <8 x i16> @llvm.mips.sat.u.h(<8 x i16>, i32) nounwind113 114; CHECK: llvm_mips_sat_u_h_test:115; CHECK: ld.h116; CHECK: sat_u.h117; CHECK: st.h118; CHECK: .size llvm_mips_sat_u_h_test119;120@llvm_mips_sat_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16121@llvm_mips_sat_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16122 123define void @llvm_mips_sat_u_w_test() nounwind {124entry:125 %0 = load <4 x i32>, ptr @llvm_mips_sat_u_w_ARG1126 %1 = tail call <4 x i32> @llvm.mips.sat.u.w(<4 x i32> %0, i32 7)127 store <4 x i32> %1, ptr @llvm_mips_sat_u_w_RES128 ret void129}130 131declare <4 x i32> @llvm.mips.sat.u.w(<4 x i32>, i32) nounwind132 133; CHECK: llvm_mips_sat_u_w_test:134; CHECK: ld.w135; CHECK: sat_u.w136; CHECK: st.w137; CHECK: .size llvm_mips_sat_u_w_test138;139@llvm_mips_sat_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16140@llvm_mips_sat_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16141 142define void @llvm_mips_sat_u_d_test() nounwind {143entry:144 %0 = load <2 x i64>, ptr @llvm_mips_sat_u_d_ARG1145 %1 = tail call <2 x i64> @llvm.mips.sat.u.d(<2 x i64> %0, i32 7)146 store <2 x i64> %1, ptr @llvm_mips_sat_u_d_RES147 ret void148}149 150declare <2 x i64> @llvm.mips.sat.u.d(<2 x i64>, i32) nounwind151 152; CHECK: llvm_mips_sat_u_d_test:153; CHECK: ld.d154; CHECK: sat_u.d155; CHECK: st.d156; CHECK: .size llvm_mips_sat_u_d_test157;158@llvm_mips_slli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16159@llvm_mips_slli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16160 161define void @llvm_mips_slli_b_test() nounwind {162entry:163 %0 = load <16 x i8>, ptr @llvm_mips_slli_b_ARG1164 %1 = tail call <16 x i8> @llvm.mips.slli.b(<16 x i8> %0, i32 7)165 store <16 x i8> %1, ptr @llvm_mips_slli_b_RES166 ret void167}168 169declare <16 x i8> @llvm.mips.slli.b(<16 x i8>, i32) nounwind170 171; CHECK: llvm_mips_slli_b_test:172; CHECK: ld.b173; CHECK: slli.b174; CHECK: st.b175; CHECK: .size llvm_mips_slli_b_test176;177@llvm_mips_slli_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16178@llvm_mips_slli_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16179 180define void @llvm_mips_slli_h_test() nounwind {181entry:182 %0 = load <8 x i16>, ptr @llvm_mips_slli_h_ARG1183 %1 = tail call <8 x i16> @llvm.mips.slli.h(<8 x i16> %0, i32 7)184 store <8 x i16> %1, ptr @llvm_mips_slli_h_RES185 ret void186}187 188declare <8 x i16> @llvm.mips.slli.h(<8 x i16>, i32) nounwind189 190; CHECK: llvm_mips_slli_h_test:191; CHECK: ld.h192; CHECK: slli.h193; CHECK: st.h194; CHECK: .size llvm_mips_slli_h_test195;196@llvm_mips_slli_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16197@llvm_mips_slli_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16198 199define void @llvm_mips_slli_w_test() nounwind {200entry:201 %0 = load <4 x i32>, ptr @llvm_mips_slli_w_ARG1202 %1 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %0, i32 7)203 store <4 x i32> %1, ptr @llvm_mips_slli_w_RES204 ret void205}206 207declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32) nounwind208 209; CHECK: llvm_mips_slli_w_test:210; CHECK: ld.w211; CHECK: slli.w212; CHECK: st.w213; CHECK: .size llvm_mips_slli_w_test214;215@llvm_mips_slli_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16216@llvm_mips_slli_d_RES = global <2 x i64> <i64 0, i64 0>, align 16217 218define void @llvm_mips_slli_d_test() nounwind {219entry:220 %0 = load <2 x i64>, ptr @llvm_mips_slli_d_ARG1221 %1 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %0, i32 7)222 store <2 x i64> %1, ptr @llvm_mips_slli_d_RES223 ret void224}225 226declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32) nounwind227 228; CHECK: llvm_mips_slli_d_test:229; CHECK: ld.d230; CHECK: slli.d231; CHECK: st.d232; CHECK: .size llvm_mips_slli_d_test233;234@llvm_mips_srai_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16235@llvm_mips_srai_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16236 237define void @llvm_mips_srai_b_test() nounwind {238entry:239 %0 = load <16 x i8>, ptr @llvm_mips_srai_b_ARG1240 %1 = tail call <16 x i8> @llvm.mips.srai.b(<16 x i8> %0, i32 7)241 store <16 x i8> %1, ptr @llvm_mips_srai_b_RES242 ret void243}244 245declare <16 x i8> @llvm.mips.srai.b(<16 x i8>, i32) nounwind246 247; CHECK: llvm_mips_srai_b_test:248; CHECK: ld.b249; CHECK: srai.b250; CHECK: st.b251; CHECK: .size llvm_mips_srai_b_test252;253@llvm_mips_srai_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16254@llvm_mips_srai_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16255 256define void @llvm_mips_srai_h_test() nounwind {257entry:258 %0 = load <8 x i16>, ptr @llvm_mips_srai_h_ARG1259 %1 = tail call <8 x i16> @llvm.mips.srai.h(<8 x i16> %0, i32 7)260 store <8 x i16> %1, ptr @llvm_mips_srai_h_RES261 ret void262}263 264declare <8 x i16> @llvm.mips.srai.h(<8 x i16>, i32) nounwind265 266; CHECK: llvm_mips_srai_h_test:267; CHECK: ld.h268; CHECK: srai.h269; CHECK: st.h270; CHECK: .size llvm_mips_srai_h_test271;272@llvm_mips_srai_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16273@llvm_mips_srai_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16274 275define void @llvm_mips_srai_w_test() nounwind {276entry:277 %0 = load <4 x i32>, ptr @llvm_mips_srai_w_ARG1278 %1 = tail call <4 x i32> @llvm.mips.srai.w(<4 x i32> %0, i32 7)279 store <4 x i32> %1, ptr @llvm_mips_srai_w_RES280 ret void281}282 283declare <4 x i32> @llvm.mips.srai.w(<4 x i32>, i32) nounwind284 285; CHECK: llvm_mips_srai_w_test:286; CHECK: ld.w287; CHECK: srai.w288; CHECK: st.w289; CHECK: .size llvm_mips_srai_w_test290;291@llvm_mips_srai_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16292@llvm_mips_srai_d_RES = global <2 x i64> <i64 0, i64 0>, align 16293 294define void @llvm_mips_srai_d_test() nounwind {295entry:296 %0 = load <2 x i64>, ptr @llvm_mips_srai_d_ARG1297 %1 = tail call <2 x i64> @llvm.mips.srai.d(<2 x i64> %0, i32 7)298 store <2 x i64> %1, ptr @llvm_mips_srai_d_RES299 ret void300}301 302declare <2 x i64> @llvm.mips.srai.d(<2 x i64>, i32) nounwind303 304; CHECK: llvm_mips_srai_d_test:305; CHECK: ld.d306; CHECK: srai.d307; CHECK: st.d308; CHECK: .size llvm_mips_srai_d_test309;310@llvm_mips_srari_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16311@llvm_mips_srari_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16312 313define void @llvm_mips_srari_b_test() nounwind {314entry:315 %0 = load <16 x i8>, ptr @llvm_mips_srari_b_ARG1316 %1 = tail call <16 x i8> @llvm.mips.srari.b(<16 x i8> %0, i32 7)317 store <16 x i8> %1, ptr @llvm_mips_srari_b_RES318 ret void319}320 321declare <16 x i8> @llvm.mips.srari.b(<16 x i8>, i32) nounwind322 323; CHECK: llvm_mips_srari_b_test:324; CHECK: ld.b325; CHECK: srari.b326; CHECK: st.b327; CHECK: .size llvm_mips_srari_b_test328;329@llvm_mips_srari_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16330@llvm_mips_srari_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16331 332define void @llvm_mips_srari_h_test() nounwind {333entry:334 %0 = load <8 x i16>, ptr @llvm_mips_srari_h_ARG1335 %1 = tail call <8 x i16> @llvm.mips.srari.h(<8 x i16> %0, i32 7)336 store <8 x i16> %1, ptr @llvm_mips_srari_h_RES337 ret void338}339 340declare <8 x i16> @llvm.mips.srari.h(<8 x i16>, i32) nounwind341 342; CHECK: llvm_mips_srari_h_test:343; CHECK: ld.h344; CHECK: srari.h345; CHECK: st.h346; CHECK: .size llvm_mips_srari_h_test347;348@llvm_mips_srari_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16349@llvm_mips_srari_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16350 351define void @llvm_mips_srari_w_test() nounwind {352entry:353 %0 = load <4 x i32>, ptr @llvm_mips_srari_w_ARG1354 %1 = tail call <4 x i32> @llvm.mips.srari.w(<4 x i32> %0, i32 7)355 store <4 x i32> %1, ptr @llvm_mips_srari_w_RES356 ret void357}358 359declare <4 x i32> @llvm.mips.srari.w(<4 x i32>, i32) nounwind360 361; CHECK: llvm_mips_srari_w_test:362; CHECK: ld.w363; CHECK: srari.w364; CHECK: st.w365; CHECK: .size llvm_mips_srari_w_test366;367@llvm_mips_srari_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16368@llvm_mips_srari_d_RES = global <2 x i64> <i64 0, i64 0>, align 16369 370define void @llvm_mips_srari_d_test() nounwind {371entry:372 %0 = load <2 x i64>, ptr @llvm_mips_srari_d_ARG1373 %1 = tail call <2 x i64> @llvm.mips.srari.d(<2 x i64> %0, i32 7)374 store <2 x i64> %1, ptr @llvm_mips_srari_d_RES375 ret void376}377 378declare <2 x i64> @llvm.mips.srari.d(<2 x i64>, i32) nounwind379 380; CHECK: llvm_mips_srari_d_test:381; CHECK: ld.d382; CHECK: srari.d383; CHECK: st.d384; CHECK: .size llvm_mips_srari_d_test385;386@llvm_mips_srli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16387@llvm_mips_srli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16388 389define void @llvm_mips_srli_b_test() nounwind {390entry:391 %0 = load <16 x i8>, ptr @llvm_mips_srli_b_ARG1392 %1 = tail call <16 x i8> @llvm.mips.srli.b(<16 x i8> %0, i32 7)393 store <16 x i8> %1, ptr @llvm_mips_srli_b_RES394 ret void395}396 397declare <16 x i8> @llvm.mips.srli.b(<16 x i8>, i32) nounwind398 399; CHECK: llvm_mips_srli_b_test:400; CHECK: ld.b401; CHECK: srli.b402; CHECK: st.b403; CHECK: .size llvm_mips_srli_b_test404;405@llvm_mips_srli_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16406@llvm_mips_srli_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16407 408define void @llvm_mips_srli_h_test() nounwind {409entry:410 %0 = load <8 x i16>, ptr @llvm_mips_srli_h_ARG1411 %1 = tail call <8 x i16> @llvm.mips.srli.h(<8 x i16> %0, i32 7)412 store <8 x i16> %1, ptr @llvm_mips_srli_h_RES413 ret void414}415 416declare <8 x i16> @llvm.mips.srli.h(<8 x i16>, i32) nounwind417 418; CHECK: llvm_mips_srli_h_test:419; CHECK: ld.h420; CHECK: srli.h421; CHECK: st.h422; CHECK: .size llvm_mips_srli_h_test423;424@llvm_mips_srli_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16425@llvm_mips_srli_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16426 427define void @llvm_mips_srli_w_test() nounwind {428entry:429 %0 = load <4 x i32>, ptr @llvm_mips_srli_w_ARG1430 %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 7)431 store <4 x i32> %1, ptr @llvm_mips_srli_w_RES432 ret void433}434 435declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32) nounwind436 437; CHECK: llvm_mips_srli_w_test:438; CHECK: ld.w439; CHECK: srli.w440; CHECK: st.w441; CHECK: .size llvm_mips_srli_w_test442;443@llvm_mips_srli_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16444@llvm_mips_srli_d_RES = global <2 x i64> <i64 0, i64 0>, align 16445 446define void @llvm_mips_srli_d_test() nounwind {447entry:448 %0 = load <2 x i64>, ptr @llvm_mips_srli_d_ARG1449 %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 7)450 store <2 x i64> %1, ptr @llvm_mips_srli_d_RES451 ret void452}453 454declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32) nounwind455 456; CHECK: llvm_mips_srli_d_test:457; CHECK: ld.d458; CHECK: srli.d459; CHECK: st.d460; CHECK: .size llvm_mips_srli_d_test461;462@llvm_mips_srlri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16463@llvm_mips_srlri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16464 465define void @llvm_mips_srlri_b_test() nounwind {466entry:467 %0 = load <16 x i8>, ptr @llvm_mips_srlri_b_ARG1468 %1 = tail call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %0, i32 7)469 store <16 x i8> %1, ptr @llvm_mips_srlri_b_RES470 ret void471}472 473declare <16 x i8> @llvm.mips.srlri.b(<16 x i8>, i32) nounwind474 475; CHECK: llvm_mips_srlri_b_test:476; CHECK: ld.b477; CHECK: srlri.b478; CHECK: st.b479; CHECK: .size llvm_mips_srlri_b_test480;481@llvm_mips_srlri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16482@llvm_mips_srlri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16483 484define void @llvm_mips_srlri_h_test() nounwind {485entry:486 %0 = load <8 x i16>, ptr @llvm_mips_srlri_h_ARG1487 %1 = tail call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %0, i32 7)488 store <8 x i16> %1, ptr @llvm_mips_srlri_h_RES489 ret void490}491 492declare <8 x i16> @llvm.mips.srlri.h(<8 x i16>, i32) nounwind493 494; CHECK: llvm_mips_srlri_h_test:495; CHECK: ld.h496; CHECK: srlri.h497; CHECK: st.h498; CHECK: .size llvm_mips_srlri_h_test499;500@llvm_mips_srlri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16501@llvm_mips_srlri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16502 503define void @llvm_mips_srlri_w_test() nounwind {504entry:505 %0 = load <4 x i32>, ptr @llvm_mips_srlri_w_ARG1506 %1 = tail call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %0, i32 7)507 store <4 x i32> %1, ptr @llvm_mips_srlri_w_RES508 ret void509}510 511declare <4 x i32> @llvm.mips.srlri.w(<4 x i32>, i32) nounwind512 513; CHECK: llvm_mips_srlri_w_test:514; CHECK: ld.w515; CHECK: srlri.w516; CHECK: st.w517; CHECK: .size llvm_mips_srlri_w_test518;519@llvm_mips_srlri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16520@llvm_mips_srlri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16521 522define void @llvm_mips_srlri_d_test() nounwind {523entry:524 %0 = load <2 x i64>, ptr @llvm_mips_srlri_d_ARG1525 %1 = tail call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %0, i32 7)526 store <2 x i64> %1, ptr @llvm_mips_srlri_d_RES527 ret void528}529 530declare <2 x i64> @llvm.mips.srlri.d(<2 x i64>, i32) nounwind531 532; CHECK: llvm_mips_srlri_d_test:533; CHECK: ld.d534; CHECK: srlri.d535; CHECK: st.d536; CHECK: .size llvm_mips_srlri_d_test537;538