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1; Test the bitcast operation for big-endian and little-endian.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s4; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s5 6define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind {7entry:8 %0 = load volatile <16 x i8>, ptr %src9 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)10 %2 = bitcast <16 x i8> %1 to <16 x i8>11 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)12 store <16 x i8> %3, ptr %dst13 ret void14}15 16; LITENDIAN: v16i8_to_v16i8:17; LITENDIAN: ld.b [[R1:\$w[0-9]+]],18; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]19; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]20; LITENDIAN: st.b [[R3]],21; LITENDIAN: .size v16i8_to_v16i822 23; BIGENDIAN: v16i8_to_v16i8:24; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],25; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]26; BIGENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]27; BIGENDIAN: st.b [[R3]],28; BIGENDIAN: .size v16i8_to_v16i829 30define void @v16i8_to_v8i16(ptr %src, ptr %dst) nounwind {31entry:32 %0 = load volatile <16 x i8>, ptr %src33 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)34 %2 = bitcast <16 x i8> %1 to <8 x i16>35 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)36 store <8 x i16> %3, ptr %dst37 ret void38}39 40; LITENDIAN: v16i8_to_v8i16:41; LITENDIAN: ld.b [[R1:\$w[0-9]+]],42; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]43; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]44; LITENDIAN: st.h [[R3]],45; LITENDIAN: .size v16i8_to_v8i1646 47; BIGENDIAN: v16i8_to_v8i16:48; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],49; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]50; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 17751; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]52; BIGENDIAN: st.h [[R4]],53; BIGENDIAN: .size v16i8_to_v8i1654 55; We can't prevent the (store (bitcast X), Y) DAG Combine here because there56; are no operations for v8f16 to put in the way.57define void @v16i8_to_v8f16(ptr %src, ptr %dst) nounwind {58entry:59 %0 = load volatile <16 x i8>, ptr %src60 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)61 %2 = bitcast <16 x i8> %1 to <8 x half>62 store <8 x half> %2, ptr %dst63 ret void64}65 66; LITENDIAN: v16i8_to_v8f16:67; LITENDIAN: ld.b [[R1:\$w[0-9]+]],68; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]69; LITENDIAN: st.b [[R2]],70; LITENDIAN: .size v16i8_to_v8f1671 72; BIGENDIAN: v16i8_to_v8f16:73; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],74; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]75; BIGENDIAN: st.b [[R2]],76; BIGENDIAN: .size v16i8_to_v8f1677 78define void @v16i8_to_v4i32(ptr %src, ptr %dst) nounwind {79entry:80 %0 = load volatile <16 x i8>, ptr %src81 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)82 %2 = bitcast <16 x i8> %1 to <4 x i32>83 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)84 store <4 x i32> %3, ptr %dst85 ret void86}87 88; LITENDIAN: v16i8_to_v4i32:89; LITENDIAN: ld.b [[R1:\$w[0-9]+]],90; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]91; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]92; LITENDIAN: st.w [[R3]],93; LITENDIAN: .size v16i8_to_v4i3294 95; BIGENDIAN: v16i8_to_v4i32:96; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],97; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]98; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 2799; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]100; BIGENDIAN: st.w [[R4]],101; BIGENDIAN: .size v16i8_to_v4i32102 103define void @v16i8_to_v4f32(ptr %src, ptr %dst) nounwind {104entry:105 %0 = load volatile <16 x i8>, ptr %src106 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)107 %2 = bitcast <16 x i8> %1 to <4 x float>108 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)109 store <4 x float> %3, ptr %dst110 ret void111}112 113; LITENDIAN: v16i8_to_v4f32:114; LITENDIAN: ld.b [[R1:\$w[0-9]+]],115; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]116; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]117; LITENDIAN: st.w [[R3]],118; LITENDIAN: .size v16i8_to_v4f32119 120; BIGENDIAN: v16i8_to_v4f32:121; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],122; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]123; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27124; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]125; BIGENDIAN: st.w [[R4]],126; BIGENDIAN: .size v16i8_to_v4f32127 128define void @v16i8_to_v2i64(ptr %src, ptr %dst) nounwind {129entry:130 %0 = load volatile <16 x i8>, ptr %src131 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)132 %2 = bitcast <16 x i8> %1 to <2 x i64>133 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)134 store <2 x i64> %3, ptr %dst135 ret void136}137 138; LITENDIAN: v16i8_to_v2i64:139; LITENDIAN: ld.b [[R1:\$w[0-9]+]],140; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]141; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]142; LITENDIAN: st.d [[R3]],143; LITENDIAN: .size v16i8_to_v2i64144 145; BIGENDIAN: v16i8_to_v2i64:146; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],147; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]148; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27149; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177150; BIGENDIAN: addv.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]151; BIGENDIAN: st.d [[R4]],152; BIGENDIAN: .size v16i8_to_v2i64153 154define void @v16i8_to_v2f64(ptr %src, ptr %dst) nounwind {155entry:156 %0 = load volatile <16 x i8>, ptr %src157 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)158 %2 = bitcast <16 x i8> %1 to <2 x double>159 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)160 store <2 x double> %3, ptr %dst161 ret void162}163 164; LITENDIAN: v16i8_to_v2f64:165; LITENDIAN: ld.b [[R1:\$w[0-9]+]],166; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]167; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]168; LITENDIAN: st.d [[R3]],169; LITENDIAN: .size v16i8_to_v2f64170 171; BIGENDIAN: v16i8_to_v2f64:172; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],173; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]174; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27175; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177176; BIGENDIAN: fadd.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]177; BIGENDIAN: st.d [[R4]],178; BIGENDIAN: .size v16i8_to_v2f64179 180define void @v8i16_to_v16i8(ptr %src, ptr %dst) nounwind {181entry:182 %0 = load volatile <8 x i16>, ptr %src183 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)184 %2 = bitcast <8 x i16> %1 to <16 x i8>185 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)186 store <16 x i8> %3, ptr %dst187 ret void188}189 190; LITENDIAN: v8i16_to_v16i8:191; LITENDIAN: ld.h [[R1:\$w[0-9]+]],192; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]193; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]194; LITENDIAN: st.b [[R3]],195; LITENDIAN: .size v8i16_to_v16i8196 197; BIGENDIAN: v8i16_to_v16i8:198; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],199; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]200; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 177201; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R2]], [[R2]]202; BIGENDIAN: st.b [[R4]],203; BIGENDIAN: .size v8i16_to_v16i8204 205define void @v8i16_to_v8i16(ptr %src, ptr %dst) nounwind {206entry:207 %0 = load volatile <8 x i16>, ptr %src208 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)209 %2 = bitcast <8 x i16> %1 to <8 x i16>210 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)211 store <8 x i16> %3, ptr %dst212 ret void213}214 215; LITENDIAN: v8i16_to_v8i16:216; LITENDIAN: ld.h [[R1:\$w[0-9]+]],217; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]218; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]219; LITENDIAN: st.h [[R3]],220; LITENDIAN: .size v8i16_to_v8i16221 222; BIGENDIAN: v8i16_to_v8i16:223; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],224; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]225; BIGENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]226; BIGENDIAN: st.h [[R3]],227; BIGENDIAN: .size v8i16_to_v8i16228 229; We can't prevent the (store (bitcast X), Y) DAG Combine here because there230; are no operations for v8f16 to put in the way.231define void @v8i16_to_v8f16(ptr %src, ptr %dst) nounwind {232entry:233 %0 = load volatile <8 x i16>, ptr %src234 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)235 %2 = bitcast <8 x i16> %1 to <8 x half>236 store <8 x half> %2, ptr %dst237 ret void238}239 240; LITENDIAN: v8i16_to_v8f16:241; LITENDIAN: ld.h [[R1:\$w[0-9]+]],242; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]243; LITENDIAN: st.h [[R2]],244; LITENDIAN: .size v8i16_to_v8f16245 246; BIGENDIAN: v8i16_to_v8f16:247; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],248; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]249; BIGENDIAN: st.h [[R2]],250; BIGENDIAN: .size v8i16_to_v8f16251 252define void @v8i16_to_v4i32(ptr %src, ptr %dst) nounwind {253entry:254 %0 = load volatile <8 x i16>, ptr %src255 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)256 %2 = bitcast <8 x i16> %1 to <4 x i32>257 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)258 store <4 x i32> %3, ptr %dst259 ret void260}261 262; LITENDIAN: v8i16_to_v4i32:263; LITENDIAN: ld.h [[R1:\$w[0-9]+]],264; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]265; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]266; LITENDIAN: st.w [[R3]],267; LITENDIAN: .size v8i16_to_v4i32268 269; BIGENDIAN: v8i16_to_v4i32:270; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],271; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]272; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 177273; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]274; BIGENDIAN: st.w [[R4]],275; BIGENDIAN: .size v8i16_to_v4i32276 277define void @v8i16_to_v4f32(ptr %src, ptr %dst) nounwind {278entry:279 %0 = load volatile <8 x i16>, ptr %src280 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)281 %2 = bitcast <8 x i16> %1 to <4 x float>282 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)283 store <4 x float> %3, ptr %dst284 ret void285}286 287; LITENDIAN: v8i16_to_v4f32:288; LITENDIAN: ld.h [[R1:\$w[0-9]+]],289; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]290; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]291; LITENDIAN: st.w [[R3]],292; LITENDIAN: .size v8i16_to_v4f32293 294; BIGENDIAN: v8i16_to_v4f32:295; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],296; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]297; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 177298; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]299; BIGENDIAN: st.w [[R4]],300; BIGENDIAN: .size v8i16_to_v4f32301 302define void @v8i16_to_v2i64(ptr %src, ptr %dst) nounwind {303entry:304 %0 = load volatile <8 x i16>, ptr %src305 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)306 %2 = bitcast <8 x i16> %1 to <2 x i64>307 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)308 store <2 x i64> %3, ptr %dst309 ret void310}311 312; LITENDIAN: v8i16_to_v2i64:313; LITENDIAN: ld.h [[R1:\$w[0-9]+]],314; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]315; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]316; LITENDIAN: st.d [[R3]],317; LITENDIAN: .size v8i16_to_v2i64318 319; BIGENDIAN: v8i16_to_v2i64:320; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],321; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]322; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 27323; BIGENDIAN: addv.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]324; BIGENDIAN: st.d [[R4]],325; BIGENDIAN: .size v8i16_to_v2i64326 327define void @v8i16_to_v2f64(ptr %src, ptr %dst) nounwind {328entry:329 %0 = load volatile <8 x i16>, ptr %src330 %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)331 %2 = bitcast <8 x i16> %1 to <2 x double>332 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)333 store <2 x double> %3, ptr %dst334 ret void335}336 337; LITENDIAN: v8i16_to_v2f64:338; LITENDIAN: ld.h [[R1:\$w[0-9]+]],339; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]340; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]341; LITENDIAN: st.d [[R3]],342; LITENDIAN: .size v8i16_to_v2f64343 344; BIGENDIAN: v8i16_to_v2f64:345; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],346; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]347; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 27348; BIGENDIAN: fadd.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]349; BIGENDIAN: st.d [[R4]],350; BIGENDIAN: .size v8i16_to_v2f64351 352;----353; We can't prevent the (bitcast (load X)) DAG Combine here because there354; are no operations for v8f16 to put in the way.355define void @v8f16_to_v16i8(ptr %src, ptr %dst) nounwind {356entry:357 %0 = load volatile <8 x half>, ptr %src358 %1 = bitcast <8 x half> %0 to <16 x i8>359 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %1, <16 x i8> %1)360 store <16 x i8> %2, ptr %dst361 ret void362}363 364; LITENDIAN: v8f16_to_v16i8:365; LITENDIAN: ld.b [[R1:\$w[0-9]+]],366; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]367; LITENDIAN: st.b [[R3]],368; LITENDIAN: .size v8f16_to_v16i8369 370; BIGENDIAN: v8f16_to_v16i8:371; BIGENDIAN: ld.b [[R1:\$w[0-9]+]],372; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R2]], [[R2]]373; BIGENDIAN: st.b [[R4]],374; BIGENDIAN: .size v8f16_to_v16i8375 376; We can't prevent the (bitcast (load X)) DAG Combine here because there377; are no operations for v8f16 to put in the way.378define void @v8f16_to_v8i16(ptr %src, ptr %dst) nounwind {379entry:380 %0 = load volatile <8 x half>, ptr %src381 %1 = bitcast <8 x half> %0 to <8 x i16>382 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %1, <8 x i16> %1)383 store <8 x i16> %2, ptr %dst384 ret void385}386 387; LITENDIAN: v8f16_to_v8i16:388; LITENDIAN: ld.h [[R1:\$w[0-9]+]],389; LITENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]390; LITENDIAN: st.h [[R2]],391; LITENDIAN: .size v8f16_to_v8i16392 393; BIGENDIAN: v8f16_to_v8i16:394; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],395; BIGENDIAN: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]396; BIGENDIAN: st.h [[R2]],397; BIGENDIAN: .size v8f16_to_v8i16398 399; We can't prevent the (bitcast (load X)) DAG Combine here because there400; are no operations for v8f16 to put in the way.401; We can't prevent the (store (bitcast X), Y) DAG Combine here because there402; are no operations for v8f16 to put in the way.403define void @v8f16_to_v8f16(ptr %src, ptr %dst) nounwind {404entry:405 %0 = load volatile <8 x half>, ptr %src406 %1 = bitcast <8 x half> %0 to <8 x half>407 store <8 x half> %1, ptr %dst408 ret void409}410 411; LITENDIAN: v8f16_to_v8f16:412; LITENDIAN: ld.h [[R1:\$w[0-9]+]],413; LITENDIAN: st.h [[R1]],414; LITENDIAN: .size v8f16_to_v8f16415 416; BIGENDIAN: v8f16_to_v8f16:417; BIGENDIAN: ld.h [[R1:\$w[0-9]+]],418; BIGENDIAN: st.h [[R1]],419; BIGENDIAN: .size v8f16_to_v8f16420 421; We can't prevent the (bitcast (load X)) DAG Combine here because there422; are no operations for v8f16 to put in the way.423define void @v8f16_to_v4i32(ptr %src, ptr %dst) nounwind {424entry:425 %0 = load volatile <8 x half>, ptr %src426 %1 = bitcast <8 x half> %0 to <4 x i32>427 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %1, <4 x i32> %1)428 store <4 x i32> %2, ptr %dst429 ret void430}431 432; LITENDIAN: v8f16_to_v4i32:433; LITENDIAN: ld.w [[R1:\$w[0-9]+]],434; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]435; LITENDIAN: st.w [[R2]],436; LITENDIAN: .size v8f16_to_v4i32437 438; BIGENDIAN: v8f16_to_v4i32:439; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],440; BIGENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]441; BIGENDIAN: st.w [[R3]],442; BIGENDIAN: .size v8f16_to_v4i32443 444; We can't prevent the (bitcast (load X)) DAG Combine here because there445; are no operations for v8f16 to put in the way.446define void @v8f16_to_v4f32(ptr %src, ptr %dst) nounwind {447entry:448 %0 = load volatile <8 x half>, ptr %src449 %1 = bitcast <8 x half> %0 to <4 x float>450 %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %1, <4 x float> %1)451 store <4 x float> %2, ptr %dst452 ret void453}454 455; LITENDIAN: v8f16_to_v4f32:456; LITENDIAN: ld.w [[R1:\$w[0-9]+]],457; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]458; LITENDIAN: st.w [[R2]],459; LITENDIAN: .size v8f16_to_v4f32460 461; BIGENDIAN: v8f16_to_v4f32:462; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],463; BIGENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]464; BIGENDIAN: st.w [[R3]],465; BIGENDIAN: .size v8f16_to_v4f32466 467; We can't prevent the (bitcast (load X)) DAG Combine here because there468; are no operations for v8f16 to put in the way.469define void @v8f16_to_v2i64(ptr %src, ptr %dst) nounwind {470entry:471 %0 = load volatile <8 x half>, ptr %src472 %1 = bitcast <8 x half> %0 to <2 x i64>473 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %1, <2 x i64> %1)474 store <2 x i64> %2, ptr %dst475 ret void476}477 478; LITENDIAN: v8f16_to_v2i64:479; LITENDIAN: ld.d [[R1:\$w[0-9]+]],480; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]481; LITENDIAN: st.d [[R2]],482; LITENDIAN: .size v8f16_to_v2i64483 484; BIGENDIAN: v8f16_to_v2i64:485; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],486; BIGENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]487; BIGENDIAN: st.d [[R3]],488; BIGENDIAN: .size v8f16_to_v2i64489 490; We can't prevent the (bitcast (load X)) DAG Combine here because there491; are no operations for v8f16 to put in the way.492define void @v8f16_to_v2f64(ptr %src, ptr %dst) nounwind {493entry:494 %0 = load volatile <8 x half>, ptr %src495 %1 = bitcast <8 x half> %0 to <2 x double>496 %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %1, <2 x double> %1)497 store <2 x double> %2, ptr %dst498 ret void499}500 501; LITENDIAN: v8f16_to_v2f64:502; LITENDIAN: ld.d [[R1:\$w[0-9]+]],503; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]504; LITENDIAN: st.d [[R2]],505; LITENDIAN: .size v8f16_to_v2f64506 507; BIGENDIAN: v8f16_to_v2f64:508; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],509; BIGENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]510; BIGENDIAN: st.d [[R3]],511; BIGENDIAN: .size v8f16_to_v2f64512;----513 514define void @v4i32_to_v16i8(ptr %src, ptr %dst) nounwind {515entry:516 %0 = load volatile <4 x i32>, ptr %src517 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)518 %2 = bitcast <4 x i32> %1 to <16 x i8>519 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)520 store <16 x i8> %3, ptr %dst521 ret void522}523 524; LITENDIAN: v4i32_to_v16i8:525; LITENDIAN: ld.w [[R1:\$w[0-9]+]],526; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]527; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]528; LITENDIAN: st.b [[R3]],529; LITENDIAN: .size v4i32_to_v16i8530 531; BIGENDIAN: v4i32_to_v16i8:532; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],533; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]534; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27535; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R3]], [[R3]]536; BIGENDIAN: st.b [[R4]],537; BIGENDIAN: .size v4i32_to_v16i8538 539define void @v4i32_to_v8i16(ptr %src, ptr %dst) nounwind {540entry:541 %0 = load volatile <4 x i32>, ptr %src542 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)543 %2 = bitcast <4 x i32> %1 to <8 x i16>544 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)545 store <8 x i16> %3, ptr %dst546 ret void547}548 549; LITENDIAN: v4i32_to_v8i16:550; LITENDIAN: ld.w [[R1:\$w[0-9]+]],551; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]552; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]553; LITENDIAN: st.h [[R3]],554; LITENDIAN: .size v4i32_to_v8i16555 556; BIGENDIAN: v4i32_to_v8i16:557; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],558; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]559; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 177560; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]561; BIGENDIAN: st.h [[R4]],562; BIGENDIAN: .size v4i32_to_v8i16563 564; We can't prevent the (store (bitcast X), Y) DAG Combine here because there565; are no operations for v8f16 to put in the way.566define void @v4i32_to_v8f16(ptr %src, ptr %dst) nounwind {567entry:568 %0 = load volatile <4 x i32>, ptr %src569 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)570 %2 = bitcast <4 x i32> %1 to <8 x half>571 store <8 x half> %2, ptr %dst572 ret void573}574 575; LITENDIAN: v4i32_to_v8f16:576; LITENDIAN: ld.w [[R1:\$w[0-9]+]],577; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]578; LITENDIAN: st.w [[R2]],579; LITENDIAN: .size v4i32_to_v8f16580 581; BIGENDIAN: v4i32_to_v8f16:582; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],583; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]584; BIGENDIAN: st.w [[R2]],585; BIGENDIAN: .size v4i32_to_v8f16586 587define void @v4i32_to_v4i32(ptr %src, ptr %dst) nounwind {588entry:589 %0 = load volatile <4 x i32>, ptr %src590 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)591 %2 = bitcast <4 x i32> %1 to <4 x i32>592 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)593 store <4 x i32> %3, ptr %dst594 ret void595}596 597; LITENDIAN: v4i32_to_v4i32:598; LITENDIAN: ld.w [[R1:\$w[0-9]+]],599; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]600; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]601; LITENDIAN: st.w [[R3]],602; LITENDIAN: .size v4i32_to_v4i32603 604; BIGENDIAN: v4i32_to_v4i32:605; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],606; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]607; BIGENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]608; BIGENDIAN: st.w [[R3]],609; BIGENDIAN: .size v4i32_to_v4i32610 611define void @v4i32_to_v4f32(ptr %src, ptr %dst) nounwind {612entry:613 %0 = load volatile <4 x i32>, ptr %src614 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)615 %2 = bitcast <4 x i32> %1 to <4 x float>616 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)617 store <4 x float> %3, ptr %dst618 ret void619}620 621; LITENDIAN: v4i32_to_v4f32:622; LITENDIAN: ld.w [[R1:\$w[0-9]+]],623; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]624; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]625; LITENDIAN: st.w [[R3]],626; LITENDIAN: .size v4i32_to_v4f32627 628; BIGENDIAN: v4i32_to_v4f32:629; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],630; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]631; BIGENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]632; BIGENDIAN: st.w [[R3]],633; BIGENDIAN: .size v4i32_to_v4f32634 635define void @v4i32_to_v2i64(ptr %src, ptr %dst) nounwind {636entry:637 %0 = load volatile <4 x i32>, ptr %src638 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)639 %2 = bitcast <4 x i32> %1 to <2 x i64>640 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)641 store <2 x i64> %3, ptr %dst642 ret void643}644 645; LITENDIAN: v4i32_to_v2i64:646; LITENDIAN: ld.w [[R1:\$w[0-9]+]],647; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]648; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]649; LITENDIAN: st.d [[R3]],650; LITENDIAN: .size v4i32_to_v2i64651 652; BIGENDIAN: v4i32_to_v2i64:653; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],654; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]655; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177656; BIGENDIAN: addv.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]657; BIGENDIAN: st.d [[R4]],658; BIGENDIAN: .size v4i32_to_v2i64659 660define void @v4i32_to_v2f64(ptr %src, ptr %dst) nounwind {661entry:662 %0 = load volatile <4 x i32>, ptr %src663 %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)664 %2 = bitcast <4 x i32> %1 to <2 x double>665 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)666 store <2 x double> %3, ptr %dst667 ret void668}669 670; LITENDIAN: v4i32_to_v2f64:671; LITENDIAN: ld.w [[R1:\$w[0-9]+]],672; LITENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]673; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]674; LITENDIAN: st.d [[R3]],675; LITENDIAN: .size v4i32_to_v2f64676 677; BIGENDIAN: v4i32_to_v2f64:678; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],679; BIGENDIAN: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]680; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177681; BIGENDIAN: fadd.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]682; BIGENDIAN: st.d [[R4]],683; BIGENDIAN: .size v4i32_to_v2f64684 685define void @v4f32_to_v16i8(ptr %src, ptr %dst) nounwind {686entry:687 %0 = load volatile <4 x float>, ptr %src688 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)689 %2 = bitcast <4 x float> %1 to <16 x i8>690 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)691 store <16 x i8> %3, ptr %dst692 ret void693}694 695; LITENDIAN: v4f32_to_v16i8:696; LITENDIAN: ld.w [[R1:\$w[0-9]+]],697; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]698; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]699; LITENDIAN: st.b [[R3]],700; LITENDIAN: .size v4f32_to_v16i8701 702; BIGENDIAN: v4f32_to_v16i8:703; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],704; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]705; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27706; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R3]], [[R3]]707; BIGENDIAN: st.b [[R4]],708; BIGENDIAN: .size v4f32_to_v16i8709 710define void @v4f32_to_v8i16(ptr %src, ptr %dst) nounwind {711entry:712 %0 = load volatile <4 x float>, ptr %src713 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)714 %2 = bitcast <4 x float> %1 to <8 x i16>715 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)716 store <8 x i16> %3, ptr %dst717 ret void718}719 720; LITENDIAN: v4f32_to_v8i16:721; LITENDIAN: ld.w [[R1:\$w[0-9]+]],722; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]723; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]724; LITENDIAN: st.h [[R3]],725; LITENDIAN: .size v4f32_to_v8i16726 727; BIGENDIAN: v4f32_to_v8i16:728; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],729; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]730; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 177731; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]732; BIGENDIAN: st.h [[R4]],733; BIGENDIAN: .size v4f32_to_v8i16734 735; We can't prevent the (store (bitcast X), Y) DAG Combine here because there736; are no operations for v8f16 to put in the way.737define void @v4f32_to_v8f16(ptr %src, ptr %dst) nounwind {738entry:739 %0 = load volatile <4 x float>, ptr %src740 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)741 %2 = bitcast <4 x float> %1 to <8 x half>742 store <8 x half> %2, ptr %dst743 ret void744}745 746; LITENDIAN: v4f32_to_v8f16:747; LITENDIAN: ld.w [[R1:\$w[0-9]+]],748; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]749; LITENDIAN: st.w [[R2]],750; LITENDIAN: .size v4f32_to_v8f16751 752; BIGENDIAN: v4f32_to_v8f16:753; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],754; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]755; BIGENDIAN: st.w [[R2]],756; BIGENDIAN: .size v4f32_to_v8f16757 758define void @v4f32_to_v4i32(ptr %src, ptr %dst) nounwind {759entry:760 %0 = load volatile <4 x float>, ptr %src761 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)762 %2 = bitcast <4 x float> %1 to <4 x i32>763 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)764 store <4 x i32> %3, ptr %dst765 ret void766}767 768; LITENDIAN: v4f32_to_v4i32:769; LITENDIAN: ld.w [[R1:\$w[0-9]+]],770; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]771; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]772; LITENDIAN: st.w [[R3]],773; LITENDIAN: .size v4f32_to_v4i32774 775; BIGENDIAN: v4f32_to_v4i32:776; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],777; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]778; BIGENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]779; BIGENDIAN: st.w [[R3]],780; BIGENDIAN: .size v4f32_to_v4i32781 782define void @v4f32_to_v4f32(ptr %src, ptr %dst) nounwind {783entry:784 %0 = load volatile <4 x float>, ptr %src785 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)786 %2 = bitcast <4 x float> %1 to <4 x float>787 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)788 store <4 x float> %3, ptr %dst789 ret void790}791 792; LITENDIAN: v4f32_to_v4f32:793; LITENDIAN: ld.w [[R1:\$w[0-9]+]],794; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]795; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]796; LITENDIAN: st.w [[R3]],797; LITENDIAN: .size v4f32_to_v4f32798 799; BIGENDIAN: v4f32_to_v4f32:800; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],801; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]802; BIGENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]803; BIGENDIAN: st.w [[R3]],804; BIGENDIAN: .size v4f32_to_v4f32805 806define void @v4f32_to_v2i64(ptr %src, ptr %dst) nounwind {807entry:808 %0 = load volatile <4 x float>, ptr %src809 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)810 %2 = bitcast <4 x float> %1 to <2 x i64>811 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)812 store <2 x i64> %3, ptr %dst813 ret void814}815 816; LITENDIAN: v4f32_to_v2i64:817; LITENDIAN: ld.w [[R1:\$w[0-9]+]],818; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]819; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]820; LITENDIAN: st.d [[R3]],821; LITENDIAN: .size v4f32_to_v2i64822 823; BIGENDIAN: v4f32_to_v2i64:824; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],825; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]826; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177827; BIGENDIAN: addv.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]828; BIGENDIAN: st.d [[R4]],829; BIGENDIAN: .size v4f32_to_v2i64830 831define void @v4f32_to_v2f64(ptr %src, ptr %dst) nounwind {832entry:833 %0 = load volatile <4 x float>, ptr %src834 %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)835 %2 = bitcast <4 x float> %1 to <2 x double>836 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)837 store <2 x double> %3, ptr %dst838 ret void839}840 841; LITENDIAN: v4f32_to_v2f64:842; LITENDIAN: ld.w [[R1:\$w[0-9]+]],843; LITENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]844; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]845; LITENDIAN: st.d [[R3]],846; LITENDIAN: .size v4f32_to_v2f64847 848; BIGENDIAN: v4f32_to_v2f64:849; BIGENDIAN: ld.w [[R1:\$w[0-9]+]],850; BIGENDIAN: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]851; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177852; BIGENDIAN: fadd.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]853; BIGENDIAN: st.d [[R4]],854; BIGENDIAN: .size v4f32_to_v2f64855 856define void @v2i64_to_v16i8(ptr %src, ptr %dst) nounwind {857entry:858 %0 = load volatile <2 x i64>, ptr %src859 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)860 %2 = bitcast <2 x i64> %1 to <16 x i8>861 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)862 store <16 x i8> %3, ptr %dst863 ret void864}865 866; LITENDIAN: v2i64_to_v16i8:867; LITENDIAN: ld.d [[R1:\$w[0-9]+]],868; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]869; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]870; LITENDIAN: st.b [[R3]],871; LITENDIAN: .size v2i64_to_v16i8872 873; BIGENDIAN: v2i64_to_v16i8:874; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],875; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]876; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 27877; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177878; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R3]], [[R3]]879; BIGENDIAN: st.b [[R4]],880; BIGENDIAN: .size v2i64_to_v16i8881 882define void @v2i64_to_v8i16(ptr %src, ptr %dst) nounwind {883entry:884 %0 = load volatile <2 x i64>, ptr %src885 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)886 %2 = bitcast <2 x i64> %1 to <8 x i16>887 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)888 store <8 x i16> %3, ptr %dst889 ret void890}891 892; LITENDIAN: v2i64_to_v8i16:893; LITENDIAN: ld.d [[R1:\$w[0-9]+]],894; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]895; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]896; LITENDIAN: st.h [[R3]],897; LITENDIAN: .size v2i64_to_v8i16898 899; BIGENDIAN: v2i64_to_v8i16:900; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],901; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]902; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 27903; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]904; BIGENDIAN: st.h [[R4]],905; BIGENDIAN: .size v2i64_to_v8i16906 907; We can't prevent the (store (bitcast X), Y) DAG Combine here because there908; are no operations for v8f16 to put in the way.909define void @v2i64_to_v8f16(ptr %src, ptr %dst) nounwind {910entry:911 %0 = load volatile <2 x i64>, ptr %src912 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)913 %2 = bitcast <2 x i64> %1 to <8 x half>914 store <8 x half> %2, ptr %dst915 ret void916}917 918; LITENDIAN: v2i64_to_v8f16:919; LITENDIAN: ld.d [[R1:\$w[0-9]+]],920; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]921; LITENDIAN: st.d [[R2]],922; LITENDIAN: .size v2i64_to_v8f16923 924; BIGENDIAN: v2i64_to_v8f16:925; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],926; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]927; BIGENDIAN: st.d [[R2]],928; BIGENDIAN: .size v2i64_to_v8f16929 930define void @v2i64_to_v4i32(ptr %src, ptr %dst) nounwind {931entry:932 %0 = load volatile <2 x i64>, ptr %src933 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)934 %2 = bitcast <2 x i64> %1 to <4 x i32>935 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)936 store <4 x i32> %3, ptr %dst937 ret void938}939 940; LITENDIAN: v2i64_to_v4i32:941; LITENDIAN: ld.d [[R1:\$w[0-9]+]],942; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]943; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]944; LITENDIAN: st.w [[R3]],945; LITENDIAN: .size v2i64_to_v4i32946 947; BIGENDIAN: v2i64_to_v4i32:948; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],949; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]950; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177951; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]952; BIGENDIAN: st.w [[R4]],953; BIGENDIAN: .size v2i64_to_v4i32954 955define void @v2i64_to_v4f32(ptr %src, ptr %dst) nounwind {956entry:957 %0 = load volatile <2 x i64>, ptr %src958 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)959 %2 = bitcast <2 x i64> %1 to <4 x float>960 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)961 store <4 x float> %3, ptr %dst962 ret void963}964 965; LITENDIAN: v2i64_to_v4f32:966; LITENDIAN: ld.d [[R1:\$w[0-9]+]],967; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]968; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]969; LITENDIAN: st.w [[R3]],970; LITENDIAN: .size v2i64_to_v4f32971 972; BIGENDIAN: v2i64_to_v4f32:973; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],974; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]975; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 177976; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]977; BIGENDIAN: st.w [[R4]],978; BIGENDIAN: .size v2i64_to_v4f32979 980define void @v2i64_to_v2i64(ptr %src, ptr %dst) nounwind {981entry:982 %0 = load volatile <2 x i64>, ptr %src983 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)984 %2 = bitcast <2 x i64> %1 to <2 x i64>985 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)986 store <2 x i64> %3, ptr %dst987 ret void988}989 990; LITENDIAN: v2i64_to_v2i64:991; LITENDIAN: ld.d [[R1:\$w[0-9]+]],992; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]993; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]994; LITENDIAN: st.d [[R3]],995; LITENDIAN: .size v2i64_to_v2i64996 997; BIGENDIAN: v2i64_to_v2i64:998; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],999; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1000; BIGENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1001; BIGENDIAN: st.d [[R3]],1002; BIGENDIAN: .size v2i64_to_v2i641003 1004define void @v2i64_to_v2f64(ptr %src, ptr %dst) nounwind {1005entry:1006 %0 = load volatile <2 x i64>, ptr %src1007 %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)1008 %2 = bitcast <2 x i64> %1 to <2 x double>1009 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)1010 store <2 x double> %3, ptr %dst1011 ret void1012}1013 1014; LITENDIAN: v2i64_to_v2f64:1015; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1016; LITENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1017; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1018; LITENDIAN: st.d [[R3]],1019; LITENDIAN: .size v2i64_to_v2f641020 1021; BIGENDIAN: v2i64_to_v2f64:1022; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1023; BIGENDIAN: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1024; BIGENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1025; BIGENDIAN: st.d [[R3]],1026; BIGENDIAN: .size v2i64_to_v2f641027 1028define void @v2f64_to_v16i8(ptr %src, ptr %dst) nounwind {1029entry:1030 %0 = load volatile <2 x double>, ptr %src1031 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1032 %2 = bitcast <2 x double> %1 to <16 x i8>1033 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)1034 store <16 x i8> %3, ptr %dst1035 ret void1036}1037 1038; LITENDIAN: v2f64_to_v16i8:1039; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1040; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1041; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]1042; LITENDIAN: st.b [[R3]],1043; LITENDIAN: .size v2f64_to_v16i81044 1045; BIGENDIAN: v2f64_to_v16i8:1046; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1047; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1048; BIGENDIAN: shf.b [[R3:\$w[0-9]+]], [[R2]], 271049; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 1771050; BIGENDIAN: addv.b [[R4:\$w[0-9]+]], [[R3]], [[R3]]1051; BIGENDIAN: st.b [[R4]],1052; BIGENDIAN: .size v2f64_to_v16i81053 1054define void @v2f64_to_v8i16(ptr %src, ptr %dst) nounwind {1055entry:1056 %0 = load volatile <2 x double>, ptr %src1057 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1058 %2 = bitcast <2 x double> %1 to <8 x i16>1059 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)1060 store <8 x i16> %3, ptr %dst1061 ret void1062}1063 1064; LITENDIAN: v2f64_to_v8i16:1065; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1066; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1067; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]1068; LITENDIAN: st.h [[R3]],1069; LITENDIAN: .size v2f64_to_v8i161070 1071; BIGENDIAN: v2f64_to_v8i16:1072; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1073; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1074; BIGENDIAN: shf.h [[R3:\$w[0-9]+]], [[R2]], 271075; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]1076; BIGENDIAN: st.h [[R4]],1077; BIGENDIAN: .size v2f64_to_v8i161078 1079; We can't prevent the (store (bitcast X), Y) DAG Combine here because there1080; are no operations for v8f16 to put in the way.1081define void @v2f64_to_v8f16(ptr %src, ptr %dst) nounwind {1082entry:1083 %0 = load volatile <2 x double>, ptr %src1084 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1085 %2 = bitcast <2 x double> %1 to <8 x half>1086 store <8 x half> %2, ptr %dst1087 ret void1088}1089 1090; LITENDIAN: v2f64_to_v8f16:1091; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1092; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1093; LITENDIAN: st.d [[R2]],1094; LITENDIAN: .size v2f64_to_v8f161095 1096; BIGENDIAN: v2f64_to_v8f16:1097; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1098; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1099; BIGENDIAN: st.d [[R2]],1100; BIGENDIAN: .size v2f64_to_v8f161101 1102define void @v2f64_to_v4i32(ptr %src, ptr %dst) nounwind {1103entry:1104 %0 = load volatile <2 x double>, ptr %src1105 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1106 %2 = bitcast <2 x double> %1 to <4 x i32>1107 %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)1108 store <4 x i32> %3, ptr %dst1109 ret void1110}1111 1112; LITENDIAN: v2f64_to_v4i32:1113; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1114; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1115; LITENDIAN: addv.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]1116; LITENDIAN: st.w [[R3]],1117; LITENDIAN: .size v2f64_to_v4i321118 1119; BIGENDIAN: v2f64_to_v4i32:1120; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1121; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1122; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 1771123; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]1124; BIGENDIAN: st.w [[R4]],1125; BIGENDIAN: .size v2f64_to_v4i321126 1127define void @v2f64_to_v4f32(ptr %src, ptr %dst) nounwind {1128entry:1129 %0 = load volatile <2 x double>, ptr %src1130 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1131 %2 = bitcast <2 x double> %1 to <4 x float>1132 %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)1133 store <4 x float> %3, ptr %dst1134 ret void1135}1136 1137; LITENDIAN: v2f64_to_v4f32:1138; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1139; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1140; LITENDIAN: fadd.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]1141; LITENDIAN: st.w [[R3]],1142; LITENDIAN: .size v2f64_to_v4f321143 1144; BIGENDIAN: v2f64_to_v4f32:1145; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1146; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1147; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R2]], 1771148; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]1149; BIGENDIAN: st.w [[R4]],1150; BIGENDIAN: .size v2f64_to_v4f321151 1152define void @v2f64_to_v2i64(ptr %src, ptr %dst) nounwind {1153entry:1154 %0 = load volatile <2 x double>, ptr %src1155 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1156 %2 = bitcast <2 x double> %1 to <2 x i64>1157 %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)1158 store <2 x i64> %3, ptr %dst1159 ret void1160}1161 1162; LITENDIAN: v2f64_to_v2i64:1163; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1164; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1165; LITENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1166; LITENDIAN: st.d [[R3]],1167; LITENDIAN: .size v2f64_to_v2i641168 1169; BIGENDIAN: v2f64_to_v2i64:1170; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1171; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1172; BIGENDIAN: addv.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1173; BIGENDIAN: st.d [[R3]],1174; BIGENDIAN: .size v2f64_to_v2i641175 1176define void @v2f64_to_v2f64(ptr %src, ptr %dst) nounwind {1177entry:1178 %0 = load volatile <2 x double>, ptr %src1179 %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)1180 %2 = bitcast <2 x double> %1 to <2 x double>1181 %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)1182 store <2 x double> %3, ptr %dst1183 ret void1184}1185 1186; LITENDIAN: v2f64_to_v2f64:1187; LITENDIAN: ld.d [[R1:\$w[0-9]+]],1188; LITENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1189; LITENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1190; LITENDIAN: st.d [[R3]],1191; LITENDIAN: .size v2f64_to_v2f641192 1193; BIGENDIAN: v2f64_to_v2f64:1194; BIGENDIAN: ld.d [[R1:\$w[0-9]+]],1195; BIGENDIAN: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]1196; BIGENDIAN: fadd.d [[R3:\$w[0-9]+]], [[R2]], [[R2]]1197; BIGENDIAN: st.d [[R3]],1198; BIGENDIAN: .size v2f64_to_v2f641199 1200declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind1201declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind1202declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind1203declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind1204declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind1205declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind1206