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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS3; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL4 5define void @and_v16i8(ptr %c, ptr %a, ptr %b) nounwind {6; CHECK-LABEL: and_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: ld.b $w0, 0($6)9; CHECK-NEXT: ld.b $w1, 0($5)10; CHECK-NEXT: and.v $w0, $w1, $w011; CHECK-NEXT: jr $ra12; CHECK-NEXT: st.b $w0, 0($4)13 %1 = load <16 x i8>, ptr %a14 %2 = load <16 x i8>, ptr %b15 %3 = and <16 x i8> %1, %216 store <16 x i8> %3, ptr %c17 ret void18}19 20define void @and_v8i16(ptr %c, ptr %a, ptr %b) nounwind {21; CHECK-LABEL: and_v8i16:22; CHECK: # %bb.0:23; CHECK-NEXT: ld.h $w0, 0($6)24; CHECK-NEXT: ld.h $w1, 0($5)25; CHECK-NEXT: and.v $w0, $w1, $w026; CHECK-NEXT: jr $ra27; CHECK-NEXT: st.h $w0, 0($4)28 %1 = load <8 x i16>, ptr %a29 %2 = load <8 x i16>, ptr %b30 %3 = and <8 x i16> %1, %231 store <8 x i16> %3, ptr %c32 ret void33}34 35define void @and_v4i32(ptr %c, ptr %a, ptr %b) nounwind {36; CHECK-LABEL: and_v4i32:37; CHECK: # %bb.0:38; CHECK-NEXT: ld.w $w0, 0($6)39; CHECK-NEXT: ld.w $w1, 0($5)40; CHECK-NEXT: and.v $w0, $w1, $w041; CHECK-NEXT: jr $ra42; CHECK-NEXT: st.w $w0, 0($4)43 %1 = load <4 x i32>, ptr %a44 %2 = load <4 x i32>, ptr %b45 %3 = and <4 x i32> %1, %246 store <4 x i32> %3, ptr %c47 ret void48}49 50define void @and_v2i64(ptr %c, ptr %a, ptr %b) nounwind {51; CHECK-LABEL: and_v2i64:52; CHECK: # %bb.0:53; CHECK-NEXT: ld.d $w0, 0($6)54; CHECK-NEXT: ld.d $w1, 0($5)55; CHECK-NEXT: and.v $w0, $w1, $w056; CHECK-NEXT: jr $ra57; CHECK-NEXT: st.d $w0, 0($4)58 %1 = load <2 x i64>, ptr %a59 %2 = load <2 x i64>, ptr %b60 %3 = and <2 x i64> %1, %261 store <2 x i64> %3, ptr %c62 ret void63}64 65define void @and_v16i8_i(ptr %c, ptr %a) nounwind {66; CHECK-LABEL: and_v16i8_i:67; CHECK: # %bb.0:68; CHECK-NEXT: ld.b $w0, 0($5)69; CHECK-NEXT: andi.b $w0, $w0, 170; CHECK-NEXT: jr $ra71; CHECK-NEXT: st.b $w0, 0($4)72 %1 = load <16 x i8>, ptr %a73 %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>74 store <16 x i8> %2, ptr %c75 ret void76}77 78define void @and_v8i16_i(ptr %c, ptr %a) nounwind {79; CHECK-LABEL: and_v8i16_i:80; CHECK: # %bb.0:81; CHECK-NEXT: ld.h $w0, 0($5)82; CHECK-NEXT: ldi.h $w1, 183; CHECK-NEXT: and.v $w0, $w0, $w184; CHECK-NEXT: jr $ra85; CHECK-NEXT: st.h $w0, 0($4)86 %1 = load <8 x i16>, ptr %a87 %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>88 store <8 x i16> %2, ptr %c89 ret void90}91 92define void @and_v4i32_i(ptr %c, ptr %a) nounwind {93; CHECK-LABEL: and_v4i32_i:94; CHECK: # %bb.0:95; CHECK-NEXT: ld.w $w0, 0($5)96; CHECK-NEXT: ldi.w $w1, 197; CHECK-NEXT: and.v $w0, $w0, $w198; CHECK-NEXT: jr $ra99; CHECK-NEXT: st.w $w0, 0($4)100 %1 = load <4 x i32>, ptr %a101 %2 = and <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>102 store <4 x i32> %2, ptr %c103 ret void104}105 106define void @and_v2i64_i(ptr %c, ptr %a) nounwind {107; MIPS-LABEL: and_v2i64_i:108; MIPS: # %bb.0:109; MIPS-NEXT: ldi.d $w0, 1110; MIPS-NEXT: shf.w $w0, $w0, 177111; MIPS-NEXT: ld.d $w1, 0($5)112; MIPS-NEXT: and.v $w0, $w1, $w0113; MIPS-NEXT: jr $ra114; MIPS-NEXT: st.d $w0, 0($4)115;116; MIPSEL-LABEL: and_v2i64_i:117; MIPSEL: # %bb.0:118; MIPSEL-NEXT: ldi.d $w0, 1119; MIPSEL-NEXT: ld.d $w1, 0($5)120; MIPSEL-NEXT: and.v $w0, $w1, $w0121; MIPSEL-NEXT: jr $ra122; MIPSEL-NEXT: st.d $w0, 0($4)123 %1 = load <2 x i64>, ptr %a124 %2 = and <2 x i64> %1, <i64 1, i64 1>125 store <2 x i64> %2, ptr %c126 ret void127}128 129define void @or_v16i8(ptr %c, ptr %a, ptr %b) nounwind {130; CHECK-LABEL: or_v16i8:131; CHECK: # %bb.0:132; CHECK-NEXT: ld.b $w0, 0($6)133; CHECK-NEXT: ld.b $w1, 0($5)134; CHECK-NEXT: or.v $w0, $w1, $w0135; CHECK-NEXT: jr $ra136; CHECK-NEXT: st.b $w0, 0($4)137 %1 = load <16 x i8>, ptr %a138 %2 = load <16 x i8>, ptr %b139 %3 = or <16 x i8> %1, %2140 store <16 x i8> %3, ptr %c141 ret void142}143 144define void @or_v8i16(ptr %c, ptr %a, ptr %b) nounwind {145; CHECK-LABEL: or_v8i16:146; CHECK: # %bb.0:147; CHECK-NEXT: ld.h $w0, 0($6)148; CHECK-NEXT: ld.h $w1, 0($5)149; CHECK-NEXT: or.v $w0, $w1, $w0150; CHECK-NEXT: jr $ra151; CHECK-NEXT: st.h $w0, 0($4)152 %1 = load <8 x i16>, ptr %a153 %2 = load <8 x i16>, ptr %b154 %3 = or <8 x i16> %1, %2155 store <8 x i16> %3, ptr %c156 ret void157}158 159define void @or_v4i32(ptr %c, ptr %a, ptr %b) nounwind {160; CHECK-LABEL: or_v4i32:161; CHECK: # %bb.0:162; CHECK-NEXT: ld.w $w0, 0($6)163; CHECK-NEXT: ld.w $w1, 0($5)164; CHECK-NEXT: or.v $w0, $w1, $w0165; CHECK-NEXT: jr $ra166; CHECK-NEXT: st.w $w0, 0($4)167 %1 = load <4 x i32>, ptr %a168 %2 = load <4 x i32>, ptr %b169 %3 = or <4 x i32> %1, %2170 store <4 x i32> %3, ptr %c171 ret void172}173 174define void @or_v2i64(ptr %c, ptr %a, ptr %b) nounwind {175; CHECK-LABEL: or_v2i64:176; CHECK: # %bb.0:177; CHECK-NEXT: ld.d $w0, 0($6)178; CHECK-NEXT: ld.d $w1, 0($5)179; CHECK-NEXT: or.v $w0, $w1, $w0180; CHECK-NEXT: jr $ra181; CHECK-NEXT: st.d $w0, 0($4)182 %1 = load <2 x i64>, ptr %a183 %2 = load <2 x i64>, ptr %b184 %3 = or <2 x i64> %1, %2185 store <2 x i64> %3, ptr %c186 ret void187}188 189define void @or_v16i8_i(ptr %c, ptr %a) nounwind {190; CHECK-LABEL: or_v16i8_i:191; CHECK: # %bb.0:192; CHECK-NEXT: ld.b $w0, 0($5)193; CHECK-NEXT: ori.b $w0, $w0, 3194; CHECK-NEXT: jr $ra195; CHECK-NEXT: st.b $w0, 0($4)196 %1 = load <16 x i8>, ptr %a197 %2 = or <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>198 store <16 x i8> %2, ptr %c199 ret void200}201 202define void @or_v8i16_i(ptr %c, ptr %a) nounwind {203; CHECK-LABEL: or_v8i16_i:204; CHECK: # %bb.0:205; CHECK-NEXT: ld.h $w0, 0($5)206; CHECK-NEXT: ldi.h $w1, 3207; CHECK-NEXT: or.v $w0, $w0, $w1208; CHECK-NEXT: jr $ra209; CHECK-NEXT: st.h $w0, 0($4)210 %1 = load <8 x i16>, ptr %a211 %2 = or <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>212 store <8 x i16> %2, ptr %c213 ret void214}215 216define void @or_v4i32_i(ptr %c, ptr %a) nounwind {217; CHECK-LABEL: or_v4i32_i:218; CHECK: # %bb.0:219; CHECK-NEXT: ld.w $w0, 0($5)220; CHECK-NEXT: ldi.w $w1, 3221; CHECK-NEXT: or.v $w0, $w0, $w1222; CHECK-NEXT: jr $ra223; CHECK-NEXT: st.w $w0, 0($4)224 %1 = load <4 x i32>, ptr %a225 %2 = or <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>226 store <4 x i32> %2, ptr %c227 ret void228}229 230define void @or_v2i64_i(ptr %c, ptr %a) nounwind {231; MIPS-LABEL: or_v2i64_i:232; MIPS: # %bb.0:233; MIPS-NEXT: ldi.d $w0, 3234; MIPS-NEXT: shf.w $w0, $w0, 177235; MIPS-NEXT: ld.d $w1, 0($5)236; MIPS-NEXT: or.v $w0, $w1, $w0237; MIPS-NEXT: jr $ra238; MIPS-NEXT: st.d $w0, 0($4)239;240; MIPSEL-LABEL: or_v2i64_i:241; MIPSEL: # %bb.0:242; MIPSEL-NEXT: ldi.d $w0, 3243; MIPSEL-NEXT: ld.d $w1, 0($5)244; MIPSEL-NEXT: or.v $w0, $w1, $w0245; MIPSEL-NEXT: jr $ra246; MIPSEL-NEXT: st.d $w0, 0($4)247 %1 = load <2 x i64>, ptr %a248 %2 = or <2 x i64> %1, <i64 3, i64 3>249 store <2 x i64> %2, ptr %c250 ret void251}252 253define void @nor_v16i8(ptr %c, ptr %a, ptr %b) nounwind {254; CHECK-LABEL: nor_v16i8:255; CHECK: # %bb.0:256; CHECK-NEXT: ld.b $w0, 0($6)257; CHECK-NEXT: ld.b $w1, 0($5)258; CHECK-NEXT: nor.v $w0, $w1, $w0259; CHECK-NEXT: jr $ra260; CHECK-NEXT: st.b $w0, 0($4)261 %1 = load <16 x i8>, ptr %a262 %2 = load <16 x i8>, ptr %b263 %3 = or <16 x i8> %1, %2264 %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>265 store <16 x i8> %4, ptr %c266 ret void267}268 269define void @nor_v8i16(ptr %c, ptr %a, ptr %b) nounwind {270; CHECK-LABEL: nor_v8i16:271; CHECK: # %bb.0:272; CHECK-NEXT: ld.h $w0, 0($6)273; CHECK-NEXT: ld.h $w1, 0($5)274; CHECK-NEXT: nor.v $w0, $w1, $w0275; CHECK-NEXT: jr $ra276; CHECK-NEXT: st.h $w0, 0($4)277 %1 = load <8 x i16>, ptr %a278 %2 = load <8 x i16>, ptr %b279 %3 = or <8 x i16> %1, %2280 %4 = xor <8 x i16> %3, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>281 store <8 x i16> %4, ptr %c282 ret void283}284 285define void @nor_v4i32(ptr %c, ptr %a, ptr %b) nounwind {286; CHECK-LABEL: nor_v4i32:287; CHECK: # %bb.0:288; CHECK-NEXT: ld.w $w0, 0($6)289; CHECK-NEXT: ld.w $w1, 0($5)290; CHECK-NEXT: nor.v $w0, $w1, $w0291; CHECK-NEXT: jr $ra292; CHECK-NEXT: st.w $w0, 0($4)293 %1 = load <4 x i32>, ptr %a294 %2 = load <4 x i32>, ptr %b295 %3 = or <4 x i32> %1, %2296 %4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>297 store <4 x i32> %4, ptr %c298 ret void299}300 301define void @nor_v2i64(ptr %c, ptr %a, ptr %b) nounwind {302; CHECK-LABEL: nor_v2i64:303; CHECK: # %bb.0:304; CHECK-NEXT: ld.d $w0, 0($6)305; CHECK-NEXT: ld.d $w1, 0($5)306; CHECK-NEXT: nor.v $w0, $w1, $w0307; CHECK-NEXT: jr $ra308; CHECK-NEXT: st.d $w0, 0($4)309 %1 = load <2 x i64>, ptr %a310 %2 = load <2 x i64>, ptr %b311 %3 = or <2 x i64> %1, %2312 %4 = xor <2 x i64> %3, <i64 -1, i64 -1>313 store <2 x i64> %4, ptr %c314 ret void315}316 317define void @nor_v16i8_i(ptr %c, ptr %a) nounwind {318; CHECK-LABEL: nor_v16i8_i:319; CHECK: # %bb.0:320; CHECK-NEXT: ld.b $w0, 0($5)321; CHECK-NEXT: nori.b $w0, $w0, 1322; CHECK-NEXT: jr $ra323; CHECK-NEXT: st.b $w0, 0($4)324 %1 = load <16 x i8>, ptr %a325 %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>326 %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>327 store <16 x i8> %3, ptr %c328 ret void329}330 331define void @nor_v8i16_i(ptr %c, ptr %a) nounwind {332; CHECK-LABEL: nor_v8i16_i:333; CHECK: # %bb.0:334; CHECK-NEXT: ld.h $w0, 0($5)335; CHECK-NEXT: ldi.h $w1, 1336; CHECK-NEXT: nor.v $w0, $w0, $w1337; CHECK-NEXT: jr $ra338; CHECK-NEXT: st.h $w0, 0($4)339 %1 = load <8 x i16>, ptr %a340 %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>341 %3 = xor <8 x i16> %2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>342 store <8 x i16> %3, ptr %c343 ret void344}345 346define void @nor_v4i32_i(ptr %c, ptr %a) nounwind {347; CHECK-LABEL: nor_v4i32_i:348; CHECK: # %bb.0:349; CHECK-NEXT: ld.w $w0, 0($5)350; CHECK-NEXT: ldi.w $w1, 1351; CHECK-NEXT: nor.v $w0, $w0, $w1352; CHECK-NEXT: jr $ra353; CHECK-NEXT: st.w $w0, 0($4)354 %1 = load <4 x i32>, ptr %a355 %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>356 %3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1>357 store <4 x i32> %3, ptr %c358 ret void359}360 361define void @nor_v2i64_i(ptr %c, ptr %a) nounwind {362; MIPS-LABEL: nor_v2i64_i:363; MIPS: # %bb.0:364; MIPS-NEXT: ldi.d $w0, 1365; MIPS-NEXT: shf.w $w0, $w0, 177366; MIPS-NEXT: ld.d $w1, 0($5)367; MIPS-NEXT: nor.v $w0, $w1, $w0368; MIPS-NEXT: jr $ra369; MIPS-NEXT: st.d $w0, 0($4)370;371; MIPSEL-LABEL: nor_v2i64_i:372; MIPSEL: # %bb.0:373; MIPSEL-NEXT: ldi.d $w0, 1374; MIPSEL-NEXT: ld.d $w1, 0($5)375; MIPSEL-NEXT: nor.v $w0, $w1, $w0376; MIPSEL-NEXT: jr $ra377; MIPSEL-NEXT: st.d $w0, 0($4)378 %1 = load <2 x i64>, ptr %a379 %2 = or <2 x i64> %1, <i64 1, i64 1>380 %3 = xor <2 x i64> %2, <i64 -1, i64 -1>381 store <2 x i64> %3, ptr %c382 ret void383}384 385define void @xor_v16i8(ptr %c, ptr %a, ptr %b) nounwind {386; CHECK-LABEL: xor_v16i8:387; CHECK: # %bb.0:388; CHECK-NEXT: ld.b $w0, 0($6)389; CHECK-NEXT: ld.b $w1, 0($5)390; CHECK-NEXT: xor.v $w0, $w1, $w0391; CHECK-NEXT: jr $ra392; CHECK-NEXT: st.b $w0, 0($4)393 %1 = load <16 x i8>, ptr %a394 %2 = load <16 x i8>, ptr %b395 %3 = xor <16 x i8> %1, %2396 store <16 x i8> %3, ptr %c397 ret void398}399 400define void @xor_v8i16(ptr %c, ptr %a, ptr %b) nounwind {401; CHECK-LABEL: xor_v8i16:402; CHECK: # %bb.0:403; CHECK-NEXT: ld.h $w0, 0($6)404; CHECK-NEXT: ld.h $w1, 0($5)405; CHECK-NEXT: xor.v $w0, $w1, $w0406; CHECK-NEXT: jr $ra407; CHECK-NEXT: st.h $w0, 0($4)408 %1 = load <8 x i16>, ptr %a409 %2 = load <8 x i16>, ptr %b410 %3 = xor <8 x i16> %1, %2411 store <8 x i16> %3, ptr %c412 ret void413}414 415define void @xor_v4i32(ptr %c, ptr %a, ptr %b) nounwind {416; CHECK-LABEL: xor_v4i32:417; CHECK: # %bb.0:418; CHECK-NEXT: ld.w $w0, 0($6)419; CHECK-NEXT: ld.w $w1, 0($5)420; CHECK-NEXT: xor.v $w0, $w1, $w0421; CHECK-NEXT: jr $ra422; CHECK-NEXT: st.w $w0, 0($4)423 %1 = load <4 x i32>, ptr %a424 %2 = load <4 x i32>, ptr %b425 %3 = xor <4 x i32> %1, %2426 store <4 x i32> %3, ptr %c427 ret void428}429 430define void @xor_v2i64(ptr %c, ptr %a, ptr %b) nounwind {431; CHECK-LABEL: xor_v2i64:432; CHECK: # %bb.0:433; CHECK-NEXT: ld.d $w0, 0($6)434; CHECK-NEXT: ld.d $w1, 0($5)435; CHECK-NEXT: xor.v $w0, $w1, $w0436; CHECK-NEXT: jr $ra437; CHECK-NEXT: st.d $w0, 0($4)438 %1 = load <2 x i64>, ptr %a439 %2 = load <2 x i64>, ptr %b440 %3 = xor <2 x i64> %1, %2441 store <2 x i64> %3, ptr %c442 ret void443}444 445define void @xor_v16i8_i(ptr %c, ptr %a) nounwind {446; CHECK-LABEL: xor_v16i8_i:447; CHECK: # %bb.0:448; CHECK-NEXT: ld.b $w0, 0($5)449; CHECK-NEXT: xori.b $w0, $w0, 3450; CHECK-NEXT: jr $ra451; CHECK-NEXT: st.b $w0, 0($4)452 %1 = load <16 x i8>, ptr %a453 %2 = xor <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>454 store <16 x i8> %2, ptr %c455 ret void456}457 458define void @xor_v8i16_i(ptr %c, ptr %a) nounwind {459; CHECK-LABEL: xor_v8i16_i:460; CHECK: # %bb.0:461; CHECK-NEXT: ld.h $w0, 0($5)462; CHECK-NEXT: ldi.h $w1, 3463; CHECK-NEXT: xor.v $w0, $w0, $w1464; CHECK-NEXT: jr $ra465; CHECK-NEXT: st.h $w0, 0($4)466 %1 = load <8 x i16>, ptr %a467 %2 = xor <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>468 store <8 x i16> %2, ptr %c469 ret void470}471 472define void @xor_v4i32_i(ptr %c, ptr %a) nounwind {473; CHECK-LABEL: xor_v4i32_i:474; CHECK: # %bb.0:475; CHECK-NEXT: ld.w $w0, 0($5)476; CHECK-NEXT: ldi.w $w1, 3477; CHECK-NEXT: xor.v $w0, $w0, $w1478; CHECK-NEXT: jr $ra479; CHECK-NEXT: st.w $w0, 0($4)480 %1 = load <4 x i32>, ptr %a481 %2 = xor <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>482 store <4 x i32> %2, ptr %c483 ret void484}485 486define void @xor_v2i64_i(ptr %c, ptr %a) nounwind {487; MIPS-LABEL: xor_v2i64_i:488; MIPS: # %bb.0:489; MIPS-NEXT: ldi.d $w0, 3490; MIPS-NEXT: shf.w $w0, $w0, 177491; MIPS-NEXT: ld.d $w1, 0($5)492; MIPS-NEXT: xor.v $w0, $w1, $w0493; MIPS-NEXT: jr $ra494; MIPS-NEXT: st.d $w0, 0($4)495;496; MIPSEL-LABEL: xor_v2i64_i:497; MIPSEL: # %bb.0:498; MIPSEL-NEXT: ldi.d $w0, 3499; MIPSEL-NEXT: ld.d $w1, 0($5)500; MIPSEL-NEXT: xor.v $w0, $w1, $w0501; MIPSEL-NEXT: jr $ra502; MIPSEL-NEXT: st.d $w0, 0($4)503 %1 = load <2 x i64>, ptr %a504 %2 = xor <2 x i64> %1, <i64 3, i64 3>505 store <2 x i64> %2, ptr %c506 ret void507}508 509define void @sll_v16i8(ptr %c, ptr %a, ptr %b) nounwind {510; CHECK-LABEL: sll_v16i8:511; CHECK: # %bb.0:512; CHECK-NEXT: ld.b $w0, 0($6)513; CHECK-NEXT: ld.b $w1, 0($5)514; CHECK-NEXT: sll.b $w0, $w1, $w0515; CHECK-NEXT: jr $ra516; CHECK-NEXT: st.b $w0, 0($4)517 %1 = load <16 x i8>, ptr %a518 %2 = load <16 x i8>, ptr %b519 %3 = shl <16 x i8> %1, %2520 store <16 x i8> %3, ptr %c521 ret void522}523 524define void @sll_v8i16(ptr %c, ptr %a, ptr %b) nounwind {525; CHECK-LABEL: sll_v8i16:526; CHECK: # %bb.0:527; CHECK-NEXT: ld.h $w0, 0($6)528; CHECK-NEXT: ld.h $w1, 0($5)529; CHECK-NEXT: sll.h $w0, $w1, $w0530; CHECK-NEXT: jr $ra531; CHECK-NEXT: st.h $w0, 0($4)532 %1 = load <8 x i16>, ptr %a533 %2 = load <8 x i16>, ptr %b534 %3 = shl <8 x i16> %1, %2535 store <8 x i16> %3, ptr %c536 ret void537}538 539define void @sll_v4i32(ptr %c, ptr %a, ptr %b) nounwind {540; CHECK-LABEL: sll_v4i32:541; CHECK: # %bb.0:542; CHECK-NEXT: ld.w $w0, 0($6)543; CHECK-NEXT: ld.w $w1, 0($5)544; CHECK-NEXT: sll.w $w0, $w1, $w0545; CHECK-NEXT: jr $ra546; CHECK-NEXT: st.w $w0, 0($4)547 %1 = load <4 x i32>, ptr %a548 %2 = load <4 x i32>, ptr %b549 %3 = shl <4 x i32> %1, %2550 store <4 x i32> %3, ptr %c551 ret void552}553 554define void @sll_v2i64(ptr %c, ptr %a, ptr %b) nounwind {555; CHECK-LABEL: sll_v2i64:556; CHECK: # %bb.0:557; CHECK-NEXT: ld.d $w0, 0($6)558; CHECK-NEXT: ld.d $w1, 0($5)559; CHECK-NEXT: sll.d $w0, $w1, $w0560; CHECK-NEXT: jr $ra561; CHECK-NEXT: st.d $w0, 0($4)562 %1 = load <2 x i64>, ptr %a563 %2 = load <2 x i64>, ptr %b564 %3 = shl <2 x i64> %1, %2565 store <2 x i64> %3, ptr %c566 ret void567}568 569define void @sll_v16i8_i(ptr %c, ptr %a) nounwind {570; CHECK-LABEL: sll_v16i8_i:571; CHECK: # %bb.0:572; CHECK-NEXT: ld.b $w0, 0($5)573; CHECK-NEXT: slli.b $w0, $w0, 1574; CHECK-NEXT: jr $ra575; CHECK-NEXT: st.b $w0, 0($4)576 %1 = load <16 x i8>, ptr %a577 %2 = shl <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>578 store <16 x i8> %2, ptr %c579 ret void580}581 582define void @sll_v8i16_i(ptr %c, ptr %a) nounwind {583; CHECK-LABEL: sll_v8i16_i:584; CHECK: # %bb.0:585; CHECK-NEXT: ld.h $w0, 0($5)586; CHECK-NEXT: slli.h $w0, $w0, 1587; CHECK-NEXT: jr $ra588; CHECK-NEXT: st.h $w0, 0($4)589 %1 = load <8 x i16>, ptr %a590 %2 = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>591 store <8 x i16> %2, ptr %c592 ret void593}594 595define void @sll_v4i32_i(ptr %c, ptr %a) nounwind {596; CHECK-LABEL: sll_v4i32_i:597; CHECK: # %bb.0:598; CHECK-NEXT: ld.w $w0, 0($5)599; CHECK-NEXT: slli.w $w0, $w0, 1600; CHECK-NEXT: jr $ra601; CHECK-NEXT: st.w $w0, 0($4)602 %1 = load <4 x i32>, ptr %a603 %2 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>604 store <4 x i32> %2, ptr %c605 ret void606}607 608define void @sll_v2i64_i(ptr %c, ptr %a) nounwind {609; CHECK-LABEL: sll_v2i64_i:610; CHECK: # %bb.0:611; CHECK-NEXT: ld.d $w0, 0($5)612; CHECK-NEXT: slli.d $w0, $w0, 1613; CHECK-NEXT: jr $ra614; CHECK-NEXT: st.d $w0, 0($4)615 %1 = load <2 x i64>, ptr %a616 %2 = shl <2 x i64> %1, <i64 1, i64 1>617 store <2 x i64> %2, ptr %c618 ret void619}620 621define void @sra_v16i8(ptr %c, ptr %a, ptr %b) nounwind {622; CHECK-LABEL: sra_v16i8:623; CHECK: # %bb.0:624; CHECK-NEXT: ld.b $w0, 0($6)625; CHECK-NEXT: ld.b $w1, 0($5)626; CHECK-NEXT: sra.b $w0, $w1, $w0627; CHECK-NEXT: jr $ra628; CHECK-NEXT: st.b $w0, 0($4)629 %1 = load <16 x i8>, ptr %a630 %2 = load <16 x i8>, ptr %b631 %3 = ashr <16 x i8> %1, %2632 store <16 x i8> %3, ptr %c633 ret void634}635 636define void @sra_v8i16(ptr %c, ptr %a, ptr %b) nounwind {637; CHECK-LABEL: sra_v8i16:638; CHECK: # %bb.0:639; CHECK-NEXT: ld.h $w0, 0($6)640; CHECK-NEXT: ld.h $w1, 0($5)641; CHECK-NEXT: sra.h $w0, $w1, $w0642; CHECK-NEXT: jr $ra643; CHECK-NEXT: st.h $w0, 0($4)644 %1 = load <8 x i16>, ptr %a645 %2 = load <8 x i16>, ptr %b646 %3 = ashr <8 x i16> %1, %2647 store <8 x i16> %3, ptr %c648 ret void649}650 651define void @sra_v4i32(ptr %c, ptr %a, ptr %b) nounwind {652; CHECK-LABEL: sra_v4i32:653; CHECK: # %bb.0:654; CHECK-NEXT: ld.w $w0, 0($6)655; CHECK-NEXT: ld.w $w1, 0($5)656; CHECK-NEXT: sra.w $w0, $w1, $w0657; CHECK-NEXT: jr $ra658; CHECK-NEXT: st.w $w0, 0($4)659 %1 = load <4 x i32>, ptr %a660 %2 = load <4 x i32>, ptr %b661 %3 = ashr <4 x i32> %1, %2662 store <4 x i32> %3, ptr %c663 ret void664}665 666define void @sra_v2i64(ptr %c, ptr %a, ptr %b) nounwind {667; CHECK-LABEL: sra_v2i64:668; CHECK: # %bb.0:669; CHECK-NEXT: ld.d $w0, 0($6)670; CHECK-NEXT: ld.d $w1, 0($5)671; CHECK-NEXT: sra.d $w0, $w1, $w0672; CHECK-NEXT: jr $ra673; CHECK-NEXT: st.d $w0, 0($4)674 %1 = load <2 x i64>, ptr %a675 %2 = load <2 x i64>, ptr %b676 %3 = ashr <2 x i64> %1, %2677 store <2 x i64> %3, ptr %c678 ret void679}680 681define void @sra_v16i8_i(ptr %c, ptr %a) nounwind {682; CHECK-LABEL: sra_v16i8_i:683; CHECK: # %bb.0:684; CHECK-NEXT: ld.b $w0, 0($5)685; CHECK-NEXT: srai.b $w0, $w0, 1686; CHECK-NEXT: jr $ra687; CHECK-NEXT: st.b $w0, 0($4)688 %1 = load <16 x i8>, ptr %a689 %2 = ashr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>690 store <16 x i8> %2, ptr %c691 ret void692}693 694define void @sra_v8i16_i(ptr %c, ptr %a) nounwind {695; CHECK-LABEL: sra_v8i16_i:696; CHECK: # %bb.0:697; CHECK-NEXT: ld.h $w0, 0($5)698; CHECK-NEXT: srai.h $w0, $w0, 1699; CHECK-NEXT: jr $ra700; CHECK-NEXT: st.h $w0, 0($4)701 %1 = load <8 x i16>, ptr %a702 %2 = ashr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>703 store <8 x i16> %2, ptr %c704 ret void705}706 707define void @sra_v4i32_i(ptr %c, ptr %a) nounwind {708; CHECK-LABEL: sra_v4i32_i:709; CHECK: # %bb.0:710; CHECK-NEXT: ld.w $w0, 0($5)711; CHECK-NEXT: srai.w $w0, $w0, 1712; CHECK-NEXT: jr $ra713; CHECK-NEXT: st.w $w0, 0($4)714 %1 = load <4 x i32>, ptr %a715 %2 = ashr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>716 store <4 x i32> %2, ptr %c717 ret void718}719 720define void @sra_v2i64_i(ptr %c, ptr %a) nounwind {721; CHECK-LABEL: sra_v2i64_i:722; CHECK: # %bb.0:723; CHECK-NEXT: ld.d $w0, 0($5)724; CHECK-NEXT: srai.d $w0, $w0, 1725; CHECK-NEXT: jr $ra726; CHECK-NEXT: st.d $w0, 0($4)727 %1 = load <2 x i64>, ptr %a728 %2 = ashr <2 x i64> %1, <i64 1, i64 1>729 store <2 x i64> %2, ptr %c730 ret void731}732 733define void @srl_v16i8(ptr %c, ptr %a, ptr %b) nounwind {734; CHECK-LABEL: srl_v16i8:735; CHECK: # %bb.0:736; CHECK-NEXT: ld.b $w0, 0($6)737; CHECK-NEXT: ld.b $w1, 0($5)738; CHECK-NEXT: srl.b $w0, $w1, $w0739; CHECK-NEXT: jr $ra740; CHECK-NEXT: st.b $w0, 0($4)741 %1 = load <16 x i8>, ptr %a742 %2 = load <16 x i8>, ptr %b743 %3 = lshr <16 x i8> %1, %2744 store <16 x i8> %3, ptr %c745 ret void746}747 748define void @srl_v8i16(ptr %c, ptr %a, ptr %b) nounwind {749; CHECK-LABEL: srl_v8i16:750; CHECK: # %bb.0:751; CHECK-NEXT: ld.h $w0, 0($6)752; CHECK-NEXT: ld.h $w1, 0($5)753; CHECK-NEXT: srl.h $w0, $w1, $w0754; CHECK-NEXT: jr $ra755; CHECK-NEXT: st.h $w0, 0($4)756 %1 = load <8 x i16>, ptr %a757 %2 = load <8 x i16>, ptr %b758 %3 = lshr <8 x i16> %1, %2759 store <8 x i16> %3, ptr %c760 ret void761}762 763define void @srl_v4i32(ptr %c, ptr %a, ptr %b) nounwind {764; CHECK-LABEL: srl_v4i32:765; CHECK: # %bb.0:766; CHECK-NEXT: ld.w $w0, 0($6)767; CHECK-NEXT: ld.w $w1, 0($5)768; CHECK-NEXT: srl.w $w0, $w1, $w0769; CHECK-NEXT: jr $ra770; CHECK-NEXT: st.w $w0, 0($4)771 %1 = load <4 x i32>, ptr %a772 %2 = load <4 x i32>, ptr %b773 %3 = lshr <4 x i32> %1, %2774 store <4 x i32> %3, ptr %c775 ret void776}777 778define void @srl_v2i64(ptr %c, ptr %a, ptr %b) nounwind {779; CHECK-LABEL: srl_v2i64:780; CHECK: # %bb.0:781; CHECK-NEXT: ld.d $w0, 0($6)782; CHECK-NEXT: ld.d $w1, 0($5)783; CHECK-NEXT: srl.d $w0, $w1, $w0784; CHECK-NEXT: jr $ra785; CHECK-NEXT: st.d $w0, 0($4)786 %1 = load <2 x i64>, ptr %a787 %2 = load <2 x i64>, ptr %b788 %3 = lshr <2 x i64> %1, %2789 store <2 x i64> %3, ptr %c790 ret void791}792 793define void @srl_v16i8_i(ptr %c, ptr %a) nounwind {794; CHECK-LABEL: srl_v16i8_i:795; CHECK: # %bb.0:796; CHECK-NEXT: ld.b $w0, 0($5)797; CHECK-NEXT: srli.b $w0, $w0, 1798; CHECK-NEXT: jr $ra799; CHECK-NEXT: st.b $w0, 0($4)800 %1 = load <16 x i8>, ptr %a801 %2 = lshr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>802 store <16 x i8> %2, ptr %c803 ret void804}805 806define void @srl_v8i16_i(ptr %c, ptr %a) nounwind {807; CHECK-LABEL: srl_v8i16_i:808; CHECK: # %bb.0:809; CHECK-NEXT: ld.h $w0, 0($5)810; CHECK-NEXT: srli.h $w0, $w0, 1811; CHECK-NEXT: jr $ra812; CHECK-NEXT: st.h $w0, 0($4)813 %1 = load <8 x i16>, ptr %a814 %2 = lshr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>815 store <8 x i16> %2, ptr %c816 ret void817}818 819define void @srl_v4i32_i(ptr %c, ptr %a) nounwind {820; CHECK-LABEL: srl_v4i32_i:821; CHECK: # %bb.0:822; CHECK-NEXT: ld.w $w0, 0($5)823; CHECK-NEXT: srli.w $w0, $w0, 1824; CHECK-NEXT: jr $ra825; CHECK-NEXT: st.w $w0, 0($4)826 %1 = load <4 x i32>, ptr %a827 %2 = lshr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>828 store <4 x i32> %2, ptr %c829 ret void830}831 832define void @srl_v2i64_i(ptr %c, ptr %a) nounwind {833; CHECK-LABEL: srl_v2i64_i:834; CHECK: # %bb.0:835; CHECK-NEXT: ld.d $w0, 0($5)836; CHECK-NEXT: srli.d $w0, $w0, 1837; CHECK-NEXT: jr $ra838; CHECK-NEXT: st.d $w0, 0($4)839 %1 = load <2 x i64>, ptr %a840 %2 = lshr <2 x i64> %1, <i64 1, i64 1>841 store <2 x i64> %2, ptr %c842 ret void843}844 845define void @ctpop_v16i8(ptr %c, ptr %a) nounwind {846; CHECK-LABEL: ctpop_v16i8:847; CHECK: # %bb.0:848; CHECK-NEXT: ld.b $w0, 0($5)849; CHECK-NEXT: pcnt.b $w0, $w0850; CHECK-NEXT: jr $ra851; CHECK-NEXT: st.b $w0, 0($4)852 %1 = load <16 x i8>, ptr %a853 %2 = tail call <16 x i8> @llvm.ctpop.v16i8 (<16 x i8> %1)854 store <16 x i8> %2, ptr %c855 ret void856}857 858define void @ctpop_v8i16(ptr %c, ptr %a) nounwind {859; CHECK-LABEL: ctpop_v8i16:860; CHECK: # %bb.0:861; CHECK-NEXT: ld.h $w0, 0($5)862; CHECK-NEXT: pcnt.h $w0, $w0863; CHECK-NEXT: jr $ra864; CHECK-NEXT: st.h $w0, 0($4)865 %1 = load <8 x i16>, ptr %a866 %2 = tail call <8 x i16> @llvm.ctpop.v8i16 (<8 x i16> %1)867 store <8 x i16> %2, ptr %c868 ret void869}870 871define void @ctpop_v4i32(ptr %c, ptr %a) nounwind {872; CHECK-LABEL: ctpop_v4i32:873; CHECK: # %bb.0:874; CHECK-NEXT: ld.w $w0, 0($5)875; CHECK-NEXT: pcnt.w $w0, $w0876; CHECK-NEXT: jr $ra877; CHECK-NEXT: st.w $w0, 0($4)878 %1 = load <4 x i32>, ptr %a879 %2 = tail call <4 x i32> @llvm.ctpop.v4i32 (<4 x i32> %1)880 store <4 x i32> %2, ptr %c881 ret void882}883 884define void @ctpop_v2i64(ptr %c, ptr %a) nounwind {885; CHECK-LABEL: ctpop_v2i64:886; CHECK: # %bb.0:887; CHECK-NEXT: ld.d $w0, 0($5)888; CHECK-NEXT: pcnt.d $w0, $w0889; CHECK-NEXT: jr $ra890; CHECK-NEXT: st.d $w0, 0($4)891 %1 = load <2 x i64>, ptr %a892 %2 = tail call <2 x i64> @llvm.ctpop.v2i64 (<2 x i64> %1)893 store <2 x i64> %2, ptr %c894 ret void895}896 897define void @ctlz_v16i8(ptr %c, ptr %a) nounwind {898; CHECK-LABEL: ctlz_v16i8:899; CHECK: # %bb.0:900; CHECK-NEXT: ld.b $w0, 0($5)901; CHECK-NEXT: nlzc.b $w0, $w0902; CHECK-NEXT: jr $ra903; CHECK-NEXT: st.b $w0, 0($4)904 %1 = load <16 x i8>, ptr %a905 %2 = tail call <16 x i8> @llvm.ctlz.v16i8 (<16 x i8> %1)906 store <16 x i8> %2, ptr %c907 ret void908}909 910define void @ctlz_v8i16(ptr %c, ptr %a) nounwind {911; CHECK-LABEL: ctlz_v8i16:912; CHECK: # %bb.0:913; CHECK-NEXT: ld.h $w0, 0($5)914; CHECK-NEXT: nlzc.h $w0, $w0915; CHECK-NEXT: jr $ra916; CHECK-NEXT: st.h $w0, 0($4)917 %1 = load <8 x i16>, ptr %a918 %2 = tail call <8 x i16> @llvm.ctlz.v8i16 (<8 x i16> %1)919 store <8 x i16> %2, ptr %c920 ret void921}922 923define void @ctlz_v4i32(ptr %c, ptr %a) nounwind {924; CHECK-LABEL: ctlz_v4i32:925; CHECK: # %bb.0:926; CHECK-NEXT: ld.w $w0, 0($5)927; CHECK-NEXT: nlzc.w $w0, $w0928; CHECK-NEXT: jr $ra929; CHECK-NEXT: st.w $w0, 0($4)930 %1 = load <4 x i32>, ptr %a931 %2 = tail call <4 x i32> @llvm.ctlz.v4i32 (<4 x i32> %1)932 store <4 x i32> %2, ptr %c933 ret void934}935 936define void @ctlz_v2i64(ptr %c, ptr %a) nounwind {937; CHECK-LABEL: ctlz_v2i64:938; CHECK: # %bb.0:939; CHECK-NEXT: ld.d $w0, 0($5)940; CHECK-NEXT: nlzc.d $w0, $w0941; CHECK-NEXT: jr $ra942; CHECK-NEXT: st.d $w0, 0($4)943 %1 = load <2 x i64>, ptr %a944 %2 = tail call <2 x i64> @llvm.ctlz.v2i64 (<2 x i64> %1)945 store <2 x i64> %2, ptr %c946 ret void947}948 949define void @bsel_v16i8(ptr %c, ptr %a, ptr %b, ptr %m) nounwind {950; CHECK-LABEL: bsel_v16i8:951; CHECK: # %bb.0:952; CHECK-NEXT: ld.b $w0, 0($7)953; CHECK-NEXT: ld.b $w1, 0($5)954; CHECK-NEXT: ld.b $w2, 0($6)955; CHECK-NEXT: bmnz.v $w2, $w1, $w0956; CHECK-NEXT: jr $ra957; CHECK-NEXT: st.b $w2, 0($4)958 %1 = load <16 x i8>, ptr %a959 %2 = load <16 x i8>, ptr %b960 %3 = load <16 x i8>, ptr %m961 %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1,962 i8 -1, i8 -1, i8 -1, i8 -1,963 i8 -1, i8 -1, i8 -1, i8 -1,964 i8 -1, i8 -1, i8 -1, i8 -1>965 %5 = and <16 x i8> %1, %3966 %6 = and <16 x i8> %2, %4967 %7 = or <16 x i8> %5, %6968 ; bmnz is the same operation969 ; (vselect Mask, IfSet, IfClr) -> (BMNZ IfClr, IfSet, Mask)970 store <16 x i8> %7, ptr %c971 ret void972}973 974define void @bsel_v16i8_i(ptr %c, ptr %a, ptr %m) nounwind {975; CHECK-LABEL: bsel_v16i8_i:976; CHECK: # %bb.0:977; CHECK-NEXT: ld.b $w0, 0($5)978; CHECK-NEXT: ld.b $w1, 0($6)979; CHECK-NEXT: bseli.b $w1, $w0, 6980; CHECK-NEXT: jr $ra981; CHECK-NEXT: st.b $w1, 0($4)982 %1 = load <16 x i8>, ptr %a983 %2 = load <16 x i8>, ptr %m984 %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1,985 i8 -1, i8 -1, i8 -1, i8 -1,986 i8 -1, i8 -1, i8 -1, i8 -1,987 i8 -1, i8 -1, i8 -1, i8 -1>988 %4 = and <16 x i8> %1, %3989 %5 = and <16 x i8> <i8 6, i8 6, i8 6, i8 6,990 i8 6, i8 6, i8 6, i8 6,991 i8 6, i8 6, i8 6, i8 6,992 i8 6, i8 6, i8 6, i8 6>, %2993 %6 = or <16 x i8> %4, %5994 store <16 x i8> %6, ptr %c995 ret void996}997 998define void @bsel_v8i16(ptr %c, ptr %a, ptr %b) nounwind {999; CHECK-LABEL: bsel_v8i16:1000; CHECK: # %bb.0:1001; CHECK-NEXT: ld.h $w0, 0($5)1002; CHECK-NEXT: ld.h $w1, 0($6)1003; CHECK-NEXT: ldi.h $w2, 61004; CHECK-NEXT: bsel.v $w2, $w1, $w01005; CHECK-NEXT: jr $ra1006; CHECK-NEXT: st.h $w2, 0($4)1007 %1 = load <8 x i16>, ptr %a1008 %2 = load <8 x i16>, ptr %b1009 %3 = and <8 x i16> %1, <i16 6, i16 6, i16 6, i16 6,1010 i16 6, i16 6, i16 6, i16 6>1011 %4 = and <8 x i16> %2, <i16 65529, i16 65529, i16 65529, i16 65529,1012 i16 65529, i16 65529, i16 65529, i16 65529>1013 %5 = or <8 x i16> %3, %41014 store <8 x i16> %5, ptr %c1015 ret void1016}1017 1018define void @bsel_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1019; CHECK-LABEL: bsel_v4i32:1020; CHECK: # %bb.0:1021; CHECK-NEXT: ld.w $w0, 0($5)1022; CHECK-NEXT: ld.w $w1, 0($6)1023; CHECK-NEXT: ldi.w $w2, 61024; CHECK-NEXT: bsel.v $w2, $w1, $w01025; CHECK-NEXT: jr $ra1026; CHECK-NEXT: st.w $w2, 0($4)1027 %1 = load <4 x i32>, ptr %a1028 %2 = load <4 x i32>, ptr %b1029 %3 = and <4 x i32> %1, <i32 6, i32 6, i32 6, i32 6>1030 %4 = and <4 x i32> %2, <i32 4294967289, i32 4294967289, i32 4294967289, i32 4294967289>1031 %5 = or <4 x i32> %3, %41032 store <4 x i32> %5, ptr %c1033 ret void1034}1035 1036define void @bsel_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1037; MIPS-LABEL: bsel_v2i64:1038; MIPS: # %bb.0:1039; MIPS-NEXT: ldi.d $w0, 61040; MIPS-NEXT: shf.w $w0, $w0, 1771041; MIPS-NEXT: ld.d $w1, 0($5)1042; MIPS-NEXT: ld.d $w2, 0($6)1043; MIPS-NEXT: bsel.v $w0, $w2, $w11044; MIPS-NEXT: jr $ra1045; MIPS-NEXT: st.d $w0, 0($4)1046;1047; MIPSEL-LABEL: bsel_v2i64:1048; MIPSEL: # %bb.0:1049; MIPSEL-NEXT: ldi.d $w0, 61050; MIPSEL-NEXT: ld.d $w1, 0($5)1051; MIPSEL-NEXT: ld.d $w2, 0($6)1052; MIPSEL-NEXT: bsel.v $w0, $w2, $w11053; MIPSEL-NEXT: jr $ra1054; MIPSEL-NEXT: st.d $w0, 0($4)1055 %1 = load <2 x i64>, ptr %a1056 %2 = load <2 x i64>, ptr %b1057 %3 = and <2 x i64> %1, <i64 6, i64 6>1058 %4 = and <2 x i64> %2, <i64 18446744073709551609, i64 18446744073709551609>1059 %5 = or <2 x i64> %3, %41060 store <2 x i64> %5, ptr %c1061 ret void1062}1063 1064define void @binsl_v16i8_i(ptr %c, ptr %a, ptr %b) nounwind {1065; CHECK-LABEL: binsl_v16i8_i:1066; CHECK: # %bb.0:1067; CHECK-NEXT: ld.b $w0, 0($5)1068; CHECK-NEXT: ld.b $w1, 0($6)1069; CHECK-NEXT: binsli.b $w1, $w0, 11070; CHECK-NEXT: jr $ra1071; CHECK-NEXT: st.b $w1, 0($4)1072 %1 = load <16 x i8>, ptr %a1073 %2 = load <16 x i8>, ptr %b1074 %3 = and <16 x i8> %1, <i8 192, i8 192, i8 192, i8 192,1075 i8 192, i8 192, i8 192, i8 192,1076 i8 192, i8 192, i8 192, i8 192,1077 i8 192, i8 192, i8 192, i8 192>1078 %4 = and <16 x i8> %2, <i8 63, i8 63, i8 63, i8 63,1079 i8 63, i8 63, i8 63, i8 63,1080 i8 63, i8 63, i8 63, i8 63,1081 i8 63, i8 63, i8 63, i8 63>1082 %5 = or <16 x i8> %3, %41083 store <16 x i8> %5, ptr %c1084 ret void1085}1086 1087define void @binsl_v8i16_i(ptr %c, ptr %a, ptr %b) nounwind {1088; CHECK-LABEL: binsl_v8i16_i:1089; CHECK: # %bb.0:1090; CHECK-NEXT: ld.h $w0, 0($5)1091; CHECK-NEXT: ld.h $w1, 0($6)1092; CHECK-NEXT: binsli.h $w1, $w0, 11093; CHECK-NEXT: jr $ra1094; CHECK-NEXT: st.h $w1, 0($4)1095 %1 = load <8 x i16>, ptr %a1096 %2 = load <8 x i16>, ptr %b1097 %3 = and <8 x i16> %1, <i16 49152, i16 49152, i16 49152, i16 49152,1098 i16 49152, i16 49152, i16 49152, i16 49152>1099 %4 = and <8 x i16> %2, <i16 16383, i16 16383, i16 16383, i16 16383,1100 i16 16383, i16 16383, i16 16383, i16 16383>1101 %5 = or <8 x i16> %3, %41102 store <8 x i16> %5, ptr %c1103 ret void1104}1105 1106define void @binsl_v4i32_i(ptr %c, ptr %a, ptr %b) nounwind {1107; CHECK-LABEL: binsl_v4i32_i:1108; CHECK: # %bb.0:1109; CHECK-NEXT: ld.w $w0, 0($5)1110; CHECK-NEXT: ld.w $w1, 0($6)1111; CHECK-NEXT: binsli.w $w1, $w0, 11112; CHECK-NEXT: jr $ra1113; CHECK-NEXT: st.w $w1, 0($4)1114 %1 = load <4 x i32>, ptr %a1115 %2 = load <4 x i32>, ptr %b1116 %3 = and <4 x i32> %1, <i32 3221225472, i32 3221225472, i32 3221225472, i32 3221225472>1117 %4 = and <4 x i32> %2, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>1118 %5 = or <4 x i32> %3, %41119 store <4 x i32> %5, ptr %c1120 ret void1121}1122 1123define void @binsl_v2i64_i(ptr %c, ptr %a, ptr %b) nounwind {1124; CHECK-LABEL: binsl_v2i64_i:1125; CHECK: # %bb.0:1126; CHECK-NEXT: ld.d $w0, 0($5)1127; CHECK-NEXT: ld.d $w1, 0($6)1128; CHECK-NEXT: binsli.d $w1, $w0, 601129; CHECK-NEXT: jr $ra1130; CHECK-NEXT: st.d $w1, 0($4)1131 %1 = load <2 x i64>, ptr %a1132 %2 = load <2 x i64>, ptr %b1133 %3 = and <2 x i64> %1, <i64 18446744073709551608, i64 18446744073709551608>1134 %4 = and <2 x i64> %2, <i64 7, i64 7>1135 %5 = or <2 x i64> %3, %41136 ; TODO: We use a particularly wide mask here to work around a legalization1137 ; issue. If the mask doesn't fit within a 10-bit immediate, it gets1138 ; legalized into a constant pool. We should add a test to cover the1139 ; other cases once they correctly select binsli.d.1140 store <2 x i64> %5, ptr %c1141 ret void1142}1143 1144define void @binsr_v16i8_i(ptr %c, ptr %a, ptr %b) nounwind {1145; CHECK-LABEL: binsr_v16i8_i:1146; CHECK: # %bb.0:1147; CHECK-NEXT: ld.b $w0, 0($5)1148; CHECK-NEXT: ld.b $w1, 0($6)1149; CHECK-NEXT: binsri.b $w1, $w0, 11150; CHECK-NEXT: jr $ra1151; CHECK-NEXT: st.b $w1, 0($4)1152 %1 = load <16 x i8>, ptr %a1153 %2 = load <16 x i8>, ptr %b1154 %3 = and <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3,1155 i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>1156 %4 = and <16 x i8> %2, <i8 252, i8 252, i8 252, i8 252,1157 i8 252, i8 252, i8 252, i8 252,1158 i8 252, i8 252, i8 252, i8 252,1159 i8 252, i8 252, i8 252, i8 252>1160 %5 = or <16 x i8> %3, %41161 store <16 x i8> %5, ptr %c1162 ret void1163}1164 1165define void @binsr_v8i16_i(ptr %c, ptr %a, ptr %b) nounwind {1166; CHECK-LABEL: binsr_v8i16_i:1167; CHECK: # %bb.0:1168; CHECK-NEXT: ld.h $w0, 0($5)1169; CHECK-NEXT: ld.h $w1, 0($6)1170; CHECK-NEXT: binsri.h $w1, $w0, 11171; CHECK-NEXT: jr $ra1172; CHECK-NEXT: st.h $w1, 0($4)1173 %1 = load <8 x i16>, ptr %a1174 %2 = load <8 x i16>, ptr %b1175 %3 = and <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3,1176 i16 3, i16 3, i16 3, i16 3>1177 %4 = and <8 x i16> %2, <i16 65532, i16 65532, i16 65532, i16 65532,1178 i16 65532, i16 65532, i16 65532, i16 65532>1179 %5 = or <8 x i16> %3, %41180 store <8 x i16> %5, ptr %c1181 ret void1182}1183 1184define void @binsr_v4i32_i(ptr %c, ptr %a, ptr %b) nounwind {1185; CHECK-LABEL: binsr_v4i32_i:1186; CHECK: # %bb.0:1187; CHECK-NEXT: ld.w $w0, 0($5)1188; CHECK-NEXT: ld.w $w1, 0($6)1189; CHECK-NEXT: binsri.w $w1, $w0, 11190; CHECK-NEXT: jr $ra1191; CHECK-NEXT: st.w $w1, 0($4)1192 %1 = load <4 x i32>, ptr %a1193 %2 = load <4 x i32>, ptr %b1194 %3 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>1195 %4 = and <4 x i32> %2, <i32 4294967292, i32 4294967292, i32 4294967292, i32 4294967292>1196 %5 = or <4 x i32> %3, %41197 store <4 x i32> %5, ptr %c1198 ret void1199}1200 1201define void @binsr_v2i64_i(ptr %c, ptr %a, ptr %b) nounwind {1202; CHECK-LABEL: binsr_v2i64_i:1203; CHECK: # %bb.0:1204; CHECK-NEXT: ld.d $w0, 0($5)1205; CHECK-NEXT: ld.d $w1, 0($6)1206; CHECK-NEXT: binsri.d $w1, $w0, 11207; CHECK-NEXT: jr $ra1208; CHECK-NEXT: st.d $w1, 0($4)1209 %1 = load <2 x i64>, ptr %a1210 %2 = load <2 x i64>, ptr %b1211 %3 = and <2 x i64> %1, <i64 3, i64 3>1212 %4 = and <2 x i64> %2, <i64 18446744073709551612, i64 18446744073709551612>1213 %5 = or <2 x i64> %3, %41214 store <2 x i64> %5, ptr %c1215 ret void1216}1217 1218define void @bclr_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1219; CHECK-LABEL: bclr_v16i8:1220; CHECK: # %bb.0:1221; CHECK-NEXT: ld.b $w0, 0($6)1222; CHECK-NEXT: ld.b $w1, 0($5)1223; CHECK-NEXT: bclr.b $w0, $w1, $w01224; CHECK-NEXT: jr $ra1225; CHECK-NEXT: st.b $w0, 0($4)1226 %1 = load <16 x i8>, ptr %a1227 %2 = load <16 x i8>, ptr %b1228 %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %21229 %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1230 %5 = and <16 x i8> %1, %41231 store <16 x i8> %5, ptr %c1232 ret void1233}1234 1235define void @bclr_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1236; CHECK-LABEL: bclr_v8i16:1237; CHECK: # %bb.0:1238; CHECK-NEXT: ld.h $w0, 0($6)1239; CHECK-NEXT: ld.h $w1, 0($5)1240; CHECK-NEXT: bclr.h $w0, $w1, $w01241; CHECK-NEXT: jr $ra1242; CHECK-NEXT: st.h $w0, 0($4)1243 %1 = load <8 x i16>, ptr %a1244 %2 = load <8 x i16>, ptr %b1245 %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %21246 %4 = xor <8 x i16> %3, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1247 %5 = and <8 x i16> %1, %41248 store <8 x i16> %5, ptr %c1249 ret void1250}1251 1252define void @bclr_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1253; CHECK-LABEL: bclr_v4i32:1254; CHECK: # %bb.0:1255; CHECK-NEXT: ld.w $w0, 0($6)1256; CHECK-NEXT: ld.w $w1, 0($5)1257; CHECK-NEXT: bclr.w $w0, $w1, $w01258; CHECK-NEXT: jr $ra1259; CHECK-NEXT: st.w $w0, 0($4)1260 %1 = load <4 x i32>, ptr %a1261 %2 = load <4 x i32>, ptr %b1262 %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %21263 %4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>1264 %5 = and <4 x i32> %1, %41265 store <4 x i32> %5, ptr %c1266 ret void1267}1268 1269define void @bclr_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1270; CHECK-LABEL: bclr_v2i64:1271; CHECK: # %bb.0:1272; CHECK-NEXT: ld.d $w0, 0($6)1273; CHECK-NEXT: ld.d $w1, 0($5)1274; CHECK-NEXT: bclr.d $w0, $w1, $w01275; CHECK-NEXT: jr $ra1276; CHECK-NEXT: st.d $w0, 0($4)1277 %1 = load <2 x i64>, ptr %a1278 %2 = load <2 x i64>, ptr %b1279 %3 = shl <2 x i64> <i64 1, i64 1>, %21280 %4 = xor <2 x i64> %3, <i64 -1, i64 -1>1281 %5 = and <2 x i64> %1, %41282 store <2 x i64> %5, ptr %c1283 ret void1284}1285 1286define void @bset_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1287; CHECK-LABEL: bset_v16i8:1288; CHECK: # %bb.0:1289; CHECK-NEXT: ld.b $w0, 0($6)1290; CHECK-NEXT: ld.b $w1, 0($5)1291; CHECK-NEXT: bset.b $w0, $w1, $w01292; CHECK-NEXT: jr $ra1293; CHECK-NEXT: st.b $w0, 0($4)1294 %1 = load <16 x i8>, ptr %a1295 %2 = load <16 x i8>, ptr %b1296 %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %21297 %4 = or <16 x i8> %1, %31298 store <16 x i8> %4, ptr %c1299 ret void1300}1301 1302define void @bset_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1303; CHECK-LABEL: bset_v8i16:1304; CHECK: # %bb.0:1305; CHECK-NEXT: ld.h $w0, 0($6)1306; CHECK-NEXT: ld.h $w1, 0($5)1307; CHECK-NEXT: bset.h $w0, $w1, $w01308; CHECK-NEXT: jr $ra1309; CHECK-NEXT: st.h $w0, 0($4)1310 %1 = load <8 x i16>, ptr %a1311 %2 = load <8 x i16>, ptr %b1312 %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %21313 %4 = or <8 x i16> %1, %31314 store <8 x i16> %4, ptr %c1315 ret void1316}1317 1318define void @bset_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1319; CHECK-LABEL: bset_v4i32:1320; CHECK: # %bb.0:1321; CHECK-NEXT: ld.w $w0, 0($6)1322; CHECK-NEXT: ld.w $w1, 0($5)1323; CHECK-NEXT: bset.w $w0, $w1, $w01324; CHECK-NEXT: jr $ra1325; CHECK-NEXT: st.w $w0, 0($4)1326 %1 = load <4 x i32>, ptr %a1327 %2 = load <4 x i32>, ptr %b1328 %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %21329 %4 = or <4 x i32> %1, %31330 store <4 x i32> %4, ptr %c1331 ret void1332}1333 1334define void @bset_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1335; CHECK-LABEL: bset_v2i64:1336; CHECK: # %bb.0:1337; CHECK-NEXT: ld.d $w0, 0($6)1338; CHECK-NEXT: ld.d $w1, 0($5)1339; CHECK-NEXT: bset.d $w0, $w1, $w01340; CHECK-NEXT: jr $ra1341; CHECK-NEXT: st.d $w0, 0($4)1342 %1 = load <2 x i64>, ptr %a1343 %2 = load <2 x i64>, ptr %b1344 %3 = shl <2 x i64> <i64 1, i64 1>, %21345 %4 = or <2 x i64> %1, %31346 store <2 x i64> %4, ptr %c1347 ret void1348}1349 1350define void @bneg_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1351; CHECK-LABEL: bneg_v16i8:1352; CHECK: # %bb.0:1353; CHECK-NEXT: ld.b $w0, 0($6)1354; CHECK-NEXT: ld.b $w1, 0($5)1355; CHECK-NEXT: bneg.b $w0, $w1, $w01356; CHECK-NEXT: jr $ra1357; CHECK-NEXT: st.b $w0, 0($4)1358 %1 = load <16 x i8>, ptr %a1359 %2 = load <16 x i8>, ptr %b1360 %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %21361 %4 = xor <16 x i8> %1, %31362 store <16 x i8> %4, ptr %c1363 ret void1364}1365 1366define void @bneg_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1367; CHECK-LABEL: bneg_v8i16:1368; CHECK: # %bb.0:1369; CHECK-NEXT: ld.h $w0, 0($6)1370; CHECK-NEXT: ld.h $w1, 0($5)1371; CHECK-NEXT: bneg.h $w0, $w1, $w01372; CHECK-NEXT: jr $ra1373; CHECK-NEXT: st.h $w0, 0($4)1374 %1 = load <8 x i16>, ptr %a1375 %2 = load <8 x i16>, ptr %b1376 %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %21377 %4 = xor <8 x i16> %1, %31378 store <8 x i16> %4, ptr %c1379 ret void1380}1381 1382define void @bneg_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1383; CHECK-LABEL: bneg_v4i32:1384; CHECK: # %bb.0:1385; CHECK-NEXT: ld.w $w0, 0($6)1386; CHECK-NEXT: ld.w $w1, 0($5)1387; CHECK-NEXT: bneg.w $w0, $w1, $w01388; CHECK-NEXT: jr $ra1389; CHECK-NEXT: st.w $w0, 0($4)1390 %1 = load <4 x i32>, ptr %a1391 %2 = load <4 x i32>, ptr %b1392 %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %21393 %4 = xor <4 x i32> %1, %31394 store <4 x i32> %4, ptr %c1395 ret void1396}1397 1398define void @bneg_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1399; CHECK-LABEL: bneg_v2i64:1400; CHECK: # %bb.0:1401; CHECK-NEXT: ld.d $w0, 0($6)1402; CHECK-NEXT: ld.d $w1, 0($5)1403; CHECK-NEXT: bneg.d $w0, $w1, $w01404; CHECK-NEXT: jr $ra1405; CHECK-NEXT: st.d $w0, 0($4)1406 %1 = load <2 x i64>, ptr %a1407 %2 = load <2 x i64>, ptr %b1408 %3 = shl <2 x i64> <i64 1, i64 1>, %21409 %4 = xor <2 x i64> %1, %31410 store <2 x i64> %4, ptr %c1411 ret void1412}1413 1414define void @bclri_v16i8(ptr %c, ptr %a) nounwind {1415; CHECK-LABEL: bclri_v16i8:1416; CHECK: # %bb.0:1417; CHECK-NEXT: ld.b $w0, 0($5)1418; CHECK-NEXT: andi.b $w0, $w0, 2471419; CHECK-NEXT: jr $ra1420; CHECK-NEXT: st.b $w0, 0($4)1421 %1 = load <16 x i8>, ptr %a1422 %2 = xor <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>,1423 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1424 %3 = and <16 x i8> %1, %21425 ; bclri.b and andi.b are exactly equivalent.1426 store <16 x i8> %3, ptr %c1427 ret void1428}1429 1430define void @bclri_v8i16(ptr %c, ptr %a) nounwind {1431; CHECK-LABEL: bclri_v8i16:1432; CHECK: # %bb.0:1433; CHECK-NEXT: ld.h $w0, 0($5)1434; CHECK-NEXT: bclri.h $w0, $w0, 31435; CHECK-NEXT: jr $ra1436; CHECK-NEXT: st.h $w0, 0($4)1437 %1 = load <8 x i16>, ptr %a1438 %2 = xor <8 x i16> <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>,1439 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1440 %3 = and <8 x i16> %1, %21441 store <8 x i16> %3, ptr %c1442 ret void1443}1444 1445define void @bclri_v4i32(ptr %c, ptr %a) nounwind {1446; CHECK-LABEL: bclri_v4i32:1447; CHECK: # %bb.0:1448; CHECK-NEXT: ld.w $w0, 0($5)1449; CHECK-NEXT: bclri.w $w0, $w0, 31450; CHECK-NEXT: jr $ra1451; CHECK-NEXT: st.w $w0, 0($4)1452 %1 = load <4 x i32>, ptr %a1453 %2 = xor <4 x i32> <i32 8, i32 8, i32 8, i32 8>,1454 <i32 -1, i32 -1, i32 -1, i32 -1>1455 %3 = and <4 x i32> %1, %21456 store <4 x i32> %3, ptr %c1457 ret void1458}1459 1460define void @bclri_v2i64(ptr %c, ptr %a) nounwind {1461; CHECK-LABEL: bclri_v2i64:1462; CHECK: # %bb.0:1463; CHECK-NEXT: ld.d $w0, 0($5)1464; CHECK-NEXT: bclri.d $w0, $w0, 31465; CHECK-NEXT: jr $ra1466; CHECK-NEXT: st.d $w0, 0($4)1467 %1 = load <2 x i64>, ptr %a1468 %2 = xor <2 x i64> <i64 8, i64 8>,1469 <i64 -1, i64 -1>1470 %3 = and <2 x i64> %1, %21471 store <2 x i64> %3, ptr %c1472 ret void1473}1474 1475define void @bseti_v16i8(ptr %c, ptr %a) nounwind {1476; CHECK-LABEL: bseti_v16i8:1477; CHECK: # %bb.0:1478; CHECK-NEXT: ld.b $w0, 0($5)1479; CHECK-NEXT: bseti.b $w0, $w0, 31480; CHECK-NEXT: jr $ra1481; CHECK-NEXT: st.b $w0, 0($4)1482 %1 = load <16 x i8>, ptr %a1483 %2 = or <16 x i8> %1, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>1484 store <16 x i8> %2, ptr %c1485 ret void1486}1487 1488define void @bseti_v8i16(ptr %c, ptr %a) nounwind {1489; CHECK-LABEL: bseti_v8i16:1490; CHECK: # %bb.0:1491; CHECK-NEXT: ld.h $w0, 0($5)1492; CHECK-NEXT: bseti.h $w0, $w0, 31493; CHECK-NEXT: jr $ra1494; CHECK-NEXT: st.h $w0, 0($4)1495 %1 = load <8 x i16>, ptr %a1496 %2 = or <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1497 store <8 x i16> %2, ptr %c1498 ret void1499}1500 1501define void @bseti_v4i32(ptr %c, ptr %a) nounwind {1502; CHECK-LABEL: bseti_v4i32:1503; CHECK: # %bb.0:1504; CHECK-NEXT: ld.w $w0, 0($5)1505; CHECK-NEXT: bseti.w $w0, $w0, 31506; CHECK-NEXT: jr $ra1507; CHECK-NEXT: st.w $w0, 0($4)1508 %1 = load <4 x i32>, ptr %a1509 %2 = or <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>1510 store <4 x i32> %2, ptr %c1511 ret void1512}1513 1514define void @bseti_v2i64(ptr %c, ptr %a) nounwind {1515; CHECK-LABEL: bseti_v2i64:1516; CHECK: # %bb.0:1517; CHECK-NEXT: ld.d $w0, 0($5)1518; CHECK-NEXT: bseti.d $w0, $w0, 31519; CHECK-NEXT: jr $ra1520; CHECK-NEXT: st.d $w0, 0($4)1521 %1 = load <2 x i64>, ptr %a1522 %2 = or <2 x i64> %1, <i64 8, i64 8>1523 store <2 x i64> %2, ptr %c1524 ret void1525}1526 1527define void @bnegi_v16i8(ptr %c, ptr %a) nounwind {1528; CHECK-LABEL: bnegi_v16i8:1529; CHECK: # %bb.0:1530; CHECK-NEXT: ld.b $w0, 0($5)1531; CHECK-NEXT: bnegi.b $w0, $w0, 31532; CHECK-NEXT: jr $ra1533; CHECK-NEXT: st.b $w0, 0($4)1534 %1 = load <16 x i8>, ptr %a1535 %2 = xor <16 x i8> %1, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>1536 store <16 x i8> %2, ptr %c1537 ret void1538}1539 1540define void @bnegi_v8i16(ptr %c, ptr %a) nounwind {1541; CHECK-LABEL: bnegi_v8i16:1542; CHECK: # %bb.0:1543; CHECK-NEXT: ld.h $w0, 0($5)1544; CHECK-NEXT: bnegi.h $w0, $w0, 31545; CHECK-NEXT: jr $ra1546; CHECK-NEXT: st.h $w0, 0($4)1547 %1 = load <8 x i16>, ptr %a1548 %2 = xor <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1549 store <8 x i16> %2, ptr %c1550 ret void1551}1552 1553define void @bnegi_v4i32(ptr %c, ptr %a) nounwind {1554; CHECK-LABEL: bnegi_v4i32:1555; CHECK: # %bb.0:1556; CHECK-NEXT: ld.w $w0, 0($5)1557; CHECK-NEXT: bnegi.w $w0, $w0, 31558; CHECK-NEXT: jr $ra1559; CHECK-NEXT: st.w $w0, 0($4)1560 %1 = load <4 x i32>, ptr %a1561 %2 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>1562 store <4 x i32> %2, ptr %c1563 ret void1564}1565 1566define void @bnegi_v2i64(ptr %c, ptr %a) nounwind {1567; CHECK-LABEL: bnegi_v2i64:1568; CHECK: # %bb.0:1569; CHECK-NEXT: ld.d $w0, 0($5)1570; CHECK-NEXT: bnegi.d $w0, $w0, 31571; CHECK-NEXT: jr $ra1572; CHECK-NEXT: st.d $w0, 0($4)1573 %1 = load <2 x i64>, ptr %a1574 %2 = xor <2 x i64> %1, <i64 8, i64 8>1575 store <2 x i64> %2, ptr %c1576 ret void1577}1578 1579declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val)1580declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val)1581declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val)1582declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val)1583declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %val)1584declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %val)1585declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val)1586declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %val)1587