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1; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s2 3@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 164@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 165@llvm_mips_bmnzi_b_RES = global <16 x i8> zeroinitializer, align 166 7define void @llvm_mips_bmnzi_b_test() nounwind {8entry:9 %0 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG110 %1 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG211 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 240)12 store volatile <16 x i8> %2, ptr @llvm_mips_bmnzi_b_RES13 %3 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 15)14 store volatile <16 x i8> %3, ptr @llvm_mips_bmnzi_b_RES15 %4 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 170)16 store <16 x i8> %4, ptr @llvm_mips_bmnzi_b_RES17 ret void18}19; CHECK-LABEL: llvm_mips_bmnzi_b_test:20; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)(21; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(22; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(23; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])24; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])25; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]26; CHECK: binsli.b [[R5]], [[R3]], 327; CHECK: binsri.b [[R5]], [[R3]], 328; CHECK: bmnzi.b [[R4]], [[R3]], 17029 30define void @llvm_mips_bmzi_b_test() nounwind {31entry:32 %0 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG133 %1 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG234 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 240)35 store volatile <16 x i8> %2, ptr @llvm_mips_bmnzi_b_RES36 %3 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 15)37 store volatile <16 x i8> %3, ptr @llvm_mips_bmnzi_b_RES38 %4 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 170)39 store <16 x i8> %4, ptr @llvm_mips_bmnzi_b_RES40 ret void41}42; CHECK-LABEL: llvm_mips_bmzi_b_test:43; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)(44; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(45; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(46; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])47; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])48; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]49; CHECK: binsli.b [[R5]], [[R3]], 350; CHECK: binsri.b [[R5]], [[R3]], 351; bmnzi.b is the same as bmzi.b with ws and wd_in swapped52; CHECK: bmnzi.b [[R4]], [[R3]], 17053 54declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind55declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind56