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1; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s2; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s3 4define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {5 ; CHECK: ceq_v16i8:6 7 %1 = load <16 x i8>, ptr %a8 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)9 %2 = load <16 x i8>, ptr %b10 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)11 %3 = icmp eq <16 x i8> %1, %212 %4 = sext <16 x i1> %3 to <16 x i8>13 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]14 store <16 x i8> %4, ptr %c15 ; CHECK-DAG: st.b [[R3]], 0($4)16 17 ret void18 ; CHECK: .size ceq_v16i819}20 21define void @ceq_v8i16(ptr %c, ptr %a, ptr %b) nounwind {22 ; CHECK: ceq_v8i16:23 24 %1 = load <8 x i16>, ptr %a25 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)26 %2 = load <8 x i16>, ptr %b27 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)28 %3 = icmp eq <8 x i16> %1, %229 %4 = sext <8 x i1> %3 to <8 x i16>30 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]31 store <8 x i16> %4, ptr %c32 ; CHECK-DAG: st.h [[R3]], 0($4)33 34 ret void35 ; CHECK: .size ceq_v8i1636}37 38define void @ceq_v4i32(ptr %c, ptr %a, ptr %b) nounwind {39 ; CHECK: ceq_v4i32:40 41 %1 = load <4 x i32>, ptr %a42 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)43 %2 = load <4 x i32>, ptr %b44 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)45 %3 = icmp eq <4 x i32> %1, %246 %4 = sext <4 x i1> %3 to <4 x i32>47 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]48 store <4 x i32> %4, ptr %c49 ; CHECK-DAG: st.w [[R3]], 0($4)50 51 ret void52 ; CHECK: .size ceq_v4i3253}54 55define void @ceq_v2i64(ptr %c, ptr %a, ptr %b) nounwind {56 ; CHECK: ceq_v2i64:57 58 %1 = load <2 x i64>, ptr %a59 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)60 %2 = load <2 x i64>, ptr %b61 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)62 %3 = icmp eq <2 x i64> %1, %263 %4 = sext <2 x i1> %3 to <2 x i64>64 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]65 store <2 x i64> %4, ptr %c66 ; CHECK-DAG: st.d [[R3]], 0($4)67 68 ret void69 ; CHECK: .size ceq_v2i6470}71 72define void @cle_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {73 ; CHECK: cle_s_v16i8:74 75 %1 = load <16 x i8>, ptr %a76 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)77 %2 = load <16 x i8>, ptr %b78 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)79 %3 = icmp sle <16 x i8> %1, %280 %4 = sext <16 x i1> %3 to <16 x i8>81 ; CHECK-DAG: cle_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]82 store <16 x i8> %4, ptr %c83 ; CHECK-DAG: st.b [[R3]], 0($4)84 85 ret void86 ; CHECK: .size cle_s_v16i887}88 89define void @cle_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {90 ; CHECK: cle_s_v8i16:91 92 %1 = load <8 x i16>, ptr %a93 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)94 %2 = load <8 x i16>, ptr %b95 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)96 %3 = icmp sle <8 x i16> %1, %297 %4 = sext <8 x i1> %3 to <8 x i16>98 ; CHECK-DAG: cle_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]99 store <8 x i16> %4, ptr %c100 ; CHECK-DAG: st.h [[R3]], 0($4)101 102 ret void103 ; CHECK: .size cle_s_v8i16104}105 106define void @cle_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {107 ; CHECK: cle_s_v4i32:108 109 %1 = load <4 x i32>, ptr %a110 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)111 %2 = load <4 x i32>, ptr %b112 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)113 %3 = icmp sle <4 x i32> %1, %2114 %4 = sext <4 x i1> %3 to <4 x i32>115 ; CHECK-DAG: cle_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]116 store <4 x i32> %4, ptr %c117 ; CHECK-DAG: st.w [[R3]], 0($4)118 119 ret void120 ; CHECK: .size cle_s_v4i32121}122 123define void @cle_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {124 ; CHECK: cle_s_v2i64:125 126 %1 = load <2 x i64>, ptr %a127 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)128 %2 = load <2 x i64>, ptr %b129 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)130 %3 = icmp sle <2 x i64> %1, %2131 %4 = sext <2 x i1> %3 to <2 x i64>132 ; CHECK-DAG: cle_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]133 store <2 x i64> %4, ptr %c134 ; CHECK-DAG: st.d [[R3]], 0($4)135 136 ret void137 ; CHECK: .size cle_s_v2i64138}139 140define void @cle_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {141 ; CHECK: cle_u_v16i8:142 143 %1 = load <16 x i8>, ptr %a144 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)145 %2 = load <16 x i8>, ptr %b146 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)147 %3 = icmp ule <16 x i8> %1, %2148 %4 = sext <16 x i1> %3 to <16 x i8>149 ; CHECK-DAG: cle_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]150 store <16 x i8> %4, ptr %c151 ; CHECK-DAG: st.b [[R3]], 0($4)152 153 ret void154 ; CHECK: .size cle_u_v16i8155}156 157define void @cle_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {158 ; CHECK: cle_u_v8i16:159 160 %1 = load <8 x i16>, ptr %a161 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)162 %2 = load <8 x i16>, ptr %b163 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)164 %3 = icmp ule <8 x i16> %1, %2165 %4 = sext <8 x i1> %3 to <8 x i16>166 ; CHECK-DAG: cle_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]167 store <8 x i16> %4, ptr %c168 ; CHECK-DAG: st.h [[R3]], 0($4)169 170 ret void171 ; CHECK: .size cle_u_v8i16172}173 174define void @cle_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {175 ; CHECK: cle_u_v4i32:176 177 %1 = load <4 x i32>, ptr %a178 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)179 %2 = load <4 x i32>, ptr %b180 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)181 %3 = icmp ule <4 x i32> %1, %2182 %4 = sext <4 x i1> %3 to <4 x i32>183 ; CHECK-DAG: cle_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]184 store <4 x i32> %4, ptr %c185 ; CHECK-DAG: st.w [[R3]], 0($4)186 187 ret void188 ; CHECK: .size cle_u_v4i32189}190 191define void @cle_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {192 ; CHECK: cle_u_v2i64:193 194 %1 = load <2 x i64>, ptr %a195 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)196 %2 = load <2 x i64>, ptr %b197 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)198 %3 = icmp ule <2 x i64> %1, %2199 %4 = sext <2 x i1> %3 to <2 x i64>200 ; CHECK-DAG: cle_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]201 store <2 x i64> %4, ptr %c202 ; CHECK-DAG: st.d [[R3]], 0($4)203 204 ret void205 ; CHECK: .size cle_u_v2i64206}207 208define void @clt_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {209 ; CHECK: clt_s_v16i8:210 211 %1 = load <16 x i8>, ptr %a212 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)213 %2 = load <16 x i8>, ptr %b214 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)215 %3 = icmp slt <16 x i8> %1, %2216 %4 = sext <16 x i1> %3 to <16 x i8>217 ; CHECK-DAG: clt_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]218 store <16 x i8> %4, ptr %c219 ; CHECK-DAG: st.b [[R3]], 0($4)220 221 ret void222 ; CHECK: .size clt_s_v16i8223}224 225define void @clt_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {226 ; CHECK: clt_s_v8i16:227 228 %1 = load <8 x i16>, ptr %a229 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)230 %2 = load <8 x i16>, ptr %b231 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)232 %3 = icmp slt <8 x i16> %1, %2233 %4 = sext <8 x i1> %3 to <8 x i16>234 ; CHECK-DAG: clt_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]235 store <8 x i16> %4, ptr %c236 ; CHECK-DAG: st.h [[R3]], 0($4)237 238 ret void239 ; CHECK: .size clt_s_v8i16240}241 242define void @clt_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {243 ; CHECK: clt_s_v4i32:244 245 %1 = load <4 x i32>, ptr %a246 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)247 %2 = load <4 x i32>, ptr %b248 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)249 %3 = icmp slt <4 x i32> %1, %2250 %4 = sext <4 x i1> %3 to <4 x i32>251 ; CHECK-DAG: clt_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]252 store <4 x i32> %4, ptr %c253 ; CHECK-DAG: st.w [[R3]], 0($4)254 255 ret void256 ; CHECK: .size clt_s_v4i32257}258 259define void @clt_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {260 ; CHECK: clt_s_v2i64:261 262 %1 = load <2 x i64>, ptr %a263 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)264 %2 = load <2 x i64>, ptr %b265 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)266 %3 = icmp slt <2 x i64> %1, %2267 %4 = sext <2 x i1> %3 to <2 x i64>268 ; CHECK-DAG: clt_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]269 store <2 x i64> %4, ptr %c270 ; CHECK-DAG: st.d [[R3]], 0($4)271 272 ret void273 ; CHECK: .size clt_s_v2i64274}275 276define void @clt_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {277 ; CHECK: clt_u_v16i8:278 279 %1 = load <16 x i8>, ptr %a280 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)281 %2 = load <16 x i8>, ptr %b282 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)283 %3 = icmp ult <16 x i8> %1, %2284 %4 = sext <16 x i1> %3 to <16 x i8>285 ; CHECK-DAG: clt_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]286 store <16 x i8> %4, ptr %c287 ; CHECK-DAG: st.b [[R3]], 0($4)288 289 ret void290 ; CHECK: .size clt_u_v16i8291}292 293define void @clt_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {294 ; CHECK: clt_u_v8i16:295 296 %1 = load <8 x i16>, ptr %a297 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)298 %2 = load <8 x i16>, ptr %b299 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)300 %3 = icmp ult <8 x i16> %1, %2301 %4 = sext <8 x i1> %3 to <8 x i16>302 ; CHECK-DAG: clt_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]303 store <8 x i16> %4, ptr %c304 ; CHECK-DAG: st.h [[R3]], 0($4)305 306 ret void307 ; CHECK: .size clt_u_v8i16308}309 310define void @clt_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {311 ; CHECK: clt_u_v4i32:312 313 %1 = load <4 x i32>, ptr %a314 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)315 %2 = load <4 x i32>, ptr %b316 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)317 %3 = icmp ult <4 x i32> %1, %2318 %4 = sext <4 x i1> %3 to <4 x i32>319 ; CHECK-DAG: clt_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]320 store <4 x i32> %4, ptr %c321 ; CHECK-DAG: st.w [[R3]], 0($4)322 323 ret void324 ; CHECK: .size clt_u_v4i32325}326 327define void @clt_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {328 ; CHECK: clt_u_v2i64:329 330 %1 = load <2 x i64>, ptr %a331 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)332 %2 = load <2 x i64>, ptr %b333 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)334 %3 = icmp ult <2 x i64> %1, %2335 %4 = sext <2 x i1> %3 to <2 x i64>336 ; CHECK-DAG: clt_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]337 store <2 x i64> %4, ptr %c338 ; CHECK-DAG: st.d [[R3]], 0($4)339 340 ret void341 ; CHECK: .size clt_u_v2i64342}343 344; There is no != comparison, but test it anyway since we've had legalizer345; issues in this area.346define void @cne_v16i8(ptr %c, ptr %a, ptr %b) nounwind {347 ; CHECK: cne_v16i8:348 %1 = load <16 x i8>, ptr %a349 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)350 %2 = load <16 x i8>, ptr %b351 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)352 %3 = icmp ne <16 x i8> %1, %2353 %4 = sext <16 x i1> %3 to <16 x i8>354 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]355 ; CHECK-DAG: xori.b [[R3]], [[R3]], 255356 store <16 x i8> %4, ptr %c357 ; CHECK-DAG: st.b [[R3]], 0($4)358 359 ret void360 ; CHECK: .size cne_v16i8361}362 363; There is no != comparison, but test it anyway since we've had legalizer364; issues in this area.365define void @cne_v8i16(ptr %c, ptr %a, ptr %b) nounwind {366 ; CHECK: cne_v8i16:367 368 %1 = load <8 x i16>, ptr %a369 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)370 %2 = load <8 x i16>, ptr %b371 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)372 %3 = icmp ne <8 x i16> %1, %2373 %4 = sext <8 x i1> %3 to <8 x i16>374 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]375 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue376 ; CHECK-DAG: ldi.b [[R4:\$w[0-9]+]], -1377 ; CHECK-DAG: xor.v [[R3]], [[R3]], [[R4]]378 store <8 x i16> %4, ptr %c379 ; CHECK-DAG: st.h [[R3]], 0($4)380 381 ret void382 ; CHECK: .size cne_v8i16383}384 385; There is no != comparison, but test it anyway since we've had legalizer386; issues in this area.387define void @cne_v4i32(ptr %c, ptr %a, ptr %b) nounwind {388 ; CHECK: cne_v4i32:389 390 %1 = load <4 x i32>, ptr %a391 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)392 %2 = load <4 x i32>, ptr %b393 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)394 %3 = icmp ne <4 x i32> %1, %2395 %4 = sext <4 x i1> %3 to <4 x i32>396 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]397 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue398 ; CHECK-DAG: ldi.b [[R4:\$w[0-9]+]], -1399 ; CHECK-DAG: xor.v [[R3]], [[R3]], [[R4]]400 store <4 x i32> %4, ptr %c401 ; CHECK-DAG: st.w [[R3]], 0($4)402 403 ret void404 ; CHECK: .size cne_v4i32405}406 407; There is no != comparison, but test it anyway since we've had legalizer408; issues in this area.409define void @cne_v2i64(ptr %c, ptr %a, ptr %b) nounwind {410 ; CHECK: cne_v2i64:411 412 %1 = load <2 x i64>, ptr %a413 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)414 %2 = load <2 x i64>, ptr %b415 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)416 %3 = icmp ne <2 x i64> %1, %2417 %4 = sext <2 x i1> %3 to <2 x i64>418 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]419 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue420 ; CHECK-DAG: ldi.b [[R4:\$w[0-9]+]], -1421 ; CHECK-DAG: xor.v [[R3]], [[R3]], [[R4]]422 store <2 x i64> %4, ptr %c423 ; CHECK-DAG: st.d [[R3]], 0($4)424 425 ret void426 ; CHECK: .size cne_v2i64427}428 429define void @ceqi_v16i8(ptr %c, ptr %a) nounwind {430 ; CHECK: ceqi_v16i8:431 432 %1 = load <16 x i8>, ptr %a433 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)434 %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>435 %3 = sext <16 x i1> %2 to <16 x i8>436 ; CHECK-DAG: ceqi.b [[R3:\$w[0-9]+]], [[R1]], 1437 store <16 x i8> %3, ptr %c438 ; CHECK-DAG: st.b [[R3]], 0($4)439 440 ret void441 ; CHECK: .size ceqi_v16i8442}443 444define void @ceqi_v8i16(ptr %c, ptr %a) nounwind {445 ; CHECK: ceqi_v8i16:446 447 %1 = load <8 x i16>, ptr %a448 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)449 %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>450 %3 = sext <8 x i1> %2 to <8 x i16>451 ; CHECK-DAG: ceqi.h [[R3:\$w[0-9]+]], [[R1]], 1452 store <8 x i16> %3, ptr %c453 ; CHECK-DAG: st.h [[R3]], 0($4)454 455 ret void456 ; CHECK: .size ceqi_v8i16457}458 459define void @ceqi_v4i32(ptr %c, ptr %a) nounwind {460 ; CHECK: ceqi_v4i32:461 462 %1 = load <4 x i32>, ptr %a463 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)464 %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>465 %3 = sext <4 x i1> %2 to <4 x i32>466 ; CHECK-DAG: ceqi.w [[R3:\$w[0-9]+]], [[R1]], 1467 store <4 x i32> %3, ptr %c468 ; CHECK-DAG: st.w [[R3]], 0($4)469 470 ret void471 ; CHECK: .size ceqi_v4i32472}473 474define void @ceqi_v2i64(ptr %c, ptr %a) nounwind {475 ; CHECK: ceqi_v2i64:476 477 %1 = load <2 x i64>, ptr %a478 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)479 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>480 %3 = sext <2 x i1> %2 to <2 x i64>481 ; CHECK-DAG: ceqi.d [[R3:\$w[0-9]+]], [[R1]], 1482 store <2 x i64> %3, ptr %c483 ; CHECK-DAG: st.d [[R3]], 0($4)484 485 ret void486 ; CHECK: .size ceqi_v2i64487}488 489define void @clei_s_v16i8(ptr %c, ptr %a) nounwind {490 ; CHECK: clei_s_v16i8:491 492 %1 = load <16 x i8>, ptr %a493 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)494 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>495 %3 = sext <16 x i1> %2 to <16 x i8>496 ; CHECK-DAG: clei_s.b [[R3:\$w[0-9]+]], [[R1]], 1497 store <16 x i8> %3, ptr %c498 ; CHECK-DAG: st.b [[R3]], 0($4)499 500 ret void501 ; CHECK: .size clei_s_v16i8502}503 504define void @clei_s_v8i16(ptr %c, ptr %a) nounwind {505 ; CHECK: clei_s_v8i16:506 507 %1 = load <8 x i16>, ptr %a508 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)509 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>510 %3 = sext <8 x i1> %2 to <8 x i16>511 ; CHECK-DAG: clei_s.h [[R3:\$w[0-9]+]], [[R1]], 1512 store <8 x i16> %3, ptr %c513 ; CHECK-DAG: st.h [[R3]], 0($4)514 515 ret void516 ; CHECK: .size clei_s_v8i16517}518 519define void @clei_s_v4i32(ptr %c, ptr %a) nounwind {520 ; CHECK: clei_s_v4i32:521 522 %1 = load <4 x i32>, ptr %a523 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)524 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>525 %3 = sext <4 x i1> %2 to <4 x i32>526 ; CHECK-DAG: clei_s.w [[R3:\$w[0-9]+]], [[R1]], 1527 store <4 x i32> %3, ptr %c528 ; CHECK-DAG: st.w [[R3]], 0($4)529 530 ret void531 ; CHECK: .size clei_s_v4i32532}533 534define void @clei_s_v2i64(ptr %c, ptr %a) nounwind {535 ; CHECK: clei_s_v2i64:536 537 %1 = load <2 x i64>, ptr %a538 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)539 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>540 %3 = sext <2 x i1> %2 to <2 x i64>541 ; CHECK-DAG: clei_s.d [[R3:\$w[0-9]+]], [[R1]], 1542 store <2 x i64> %3, ptr %c543 ; CHECK-DAG: st.d [[R3]], 0($4)544 545 ret void546 ; CHECK: .size clei_s_v2i64547}548 549define void @clei_u_v16i8(ptr %c, ptr %a) nounwind {550 ; CHECK: clei_u_v16i8:551 552 %1 = load <16 x i8>, ptr %a553 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)554 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>555 %3 = sext <16 x i1> %2 to <16 x i8>556 ; CHECK-DAG: clei_u.b [[R3:\$w[0-9]+]], [[R1]], 1557 store <16 x i8> %3, ptr %c558 ; CHECK-DAG: st.b [[R3]], 0($4)559 560 ret void561 ; CHECK: .size clei_u_v16i8562}563 564define void @clei_u_v8i16(ptr %c, ptr %a) nounwind {565 ; CHECK: clei_u_v8i16:566 567 %1 = load <8 x i16>, ptr %a568 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)569 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>570 %3 = sext <8 x i1> %2 to <8 x i16>571 ; CHECK-DAG: clei_u.h [[R3:\$w[0-9]+]], [[R1]], 1572 store <8 x i16> %3, ptr %c573 ; CHECK-DAG: st.h [[R3]], 0($4)574 575 ret void576 ; CHECK: .size clei_u_v8i16577}578 579define void @clei_u_v4i32(ptr %c, ptr %a) nounwind {580 ; CHECK: clei_u_v4i32:581 582 %1 = load <4 x i32>, ptr %a583 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)584 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>585 %3 = sext <4 x i1> %2 to <4 x i32>586 ; CHECK-DAG: clei_u.w [[R3:\$w[0-9]+]], [[R1]], 1587 store <4 x i32> %3, ptr %c588 ; CHECK-DAG: st.w [[R3]], 0($4)589 590 ret void591 ; CHECK: .size clei_u_v4i32592}593 594define void @clei_u_v2i64(ptr %c, ptr %a) nounwind {595 ; CHECK: clei_u_v2i64:596 597 %1 = load <2 x i64>, ptr %a598 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)599 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>600 %3 = sext <2 x i1> %2 to <2 x i64>601 ; CHECK-DAG: clei_u.d [[R3:\$w[0-9]+]], [[R1]], 1602 store <2 x i64> %3, ptr %c603 ; CHECK-DAG: st.d [[R3]], 0($4)604 605 ret void606 ; CHECK: .size clei_u_v2i64607}608 609define void @clti_s_v16i8(ptr %c, ptr %a) nounwind {610 ; CHECK: clti_s_v16i8:611 612 %1 = load <16 x i8>, ptr %a613 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)614 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>615 %3 = sext <16 x i1> %2 to <16 x i8>616 ; CHECK-DAG: clti_s.b [[R3:\$w[0-9]+]], [[R1]], 1617 store <16 x i8> %3, ptr %c618 ; CHECK-DAG: st.b [[R3]], 0($4)619 620 ret void621 ; CHECK: .size clti_s_v16i8622}623 624define void @clti_s_v8i16(ptr %c, ptr %a) nounwind {625 ; CHECK: clti_s_v8i16:626 627 %1 = load <8 x i16>, ptr %a628 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)629 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>630 %3 = sext <8 x i1> %2 to <8 x i16>631 ; CHECK-DAG: clti_s.h [[R3:\$w[0-9]+]], [[R1]], 1632 store <8 x i16> %3, ptr %c633 ; CHECK-DAG: st.h [[R3]], 0($4)634 635 ret void636 ; CHECK: .size clti_s_v8i16637}638 639define void @clti_s_v4i32(ptr %c, ptr %a) nounwind {640 ; CHECK: clti_s_v4i32:641 642 %1 = load <4 x i32>, ptr %a643 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)644 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>645 %3 = sext <4 x i1> %2 to <4 x i32>646 ; CHECK-DAG: clti_s.w [[R3:\$w[0-9]+]], [[R1]], 1647 store <4 x i32> %3, ptr %c648 ; CHECK-DAG: st.w [[R3]], 0($4)649 650 ret void651 ; CHECK: .size clti_s_v4i32652}653 654define void @clti_s_v2i64(ptr %c, ptr %a) nounwind {655 ; CHECK: clti_s_v2i64:656 657 %1 = load <2 x i64>, ptr %a658 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)659 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>660 %3 = sext <2 x i1> %2 to <2 x i64>661 ; CHECK-DAG: clti_s.d [[R3:\$w[0-9]+]], [[R1]], 1662 store <2 x i64> %3, ptr %c663 ; CHECK-DAG: st.d [[R3]], 0($4)664 665 ret void666 ; CHECK: .size clti_s_v2i64667}668 669define void @clti_u_v16i8(ptr %c, ptr %a) nounwind {670 ; CHECK: clti_u_v16i8:671 672 %1 = load <16 x i8>, ptr %a673 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)674 %2 = icmp ult <16 x i8> %1, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>675 %3 = sext <16 x i1> %2 to <16 x i8>676 ; CHECK-DAG: clti_u.b [[R3:\$w[0-9]+]], [[R1]], 2677 store <16 x i8> %3, ptr %c678 ; CHECK-DAG: st.b [[R3]], 0($4)679 680 ret void681 ; CHECK: .size clti_u_v16i8682}683 684define void @clti_u_v8i16(ptr %c, ptr %a) nounwind {685 ; CHECK: clti_u_v8i16:686 687 %1 = load <8 x i16>, ptr %a688 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)689 %2 = icmp ult <8 x i16> %1, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>690 %3 = sext <8 x i1> %2 to <8 x i16>691 ; CHECK-DAG: clti_u.h [[R3:\$w[0-9]+]], [[R1]], 2692 store <8 x i16> %3, ptr %c693 ; CHECK-DAG: st.h [[R3]], 0($4)694 695 ret void696 ; CHECK: .size clti_u_v8i16697}698 699define void @clti_u_v4i32(ptr %c, ptr %a) nounwind {700 ; CHECK: clti_u_v4i32:701 702 %1 = load <4 x i32>, ptr %a703 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)704 %2 = icmp ult <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>705 %3 = sext <4 x i1> %2 to <4 x i32>706 ; CHECK-DAG: clti_u.w [[R3:\$w[0-9]+]], [[R1]], 2707 store <4 x i32> %3, ptr %c708 ; CHECK-DAG: st.w [[R3]], 0($4)709 710 ret void711 ; CHECK: .size clti_u_v4i32712}713 714define void @clti_u_v2i64(ptr %c, ptr %a) nounwind {715 ; CHECK: clti_u_v2i64:716 717 %1 = load <2 x i64>, ptr %a718 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)719 %2 = icmp ult <2 x i64> %1, <i64 2, i64 2>720 %3 = sext <2 x i1> %2 to <2 x i64>721 ; CHECK-DAG: clti_u.d [[R3:\$w[0-9]+]], [[R1]], 2722 store <2 x i64> %3, ptr %c723 ; CHECK-DAG: st.d [[R3]], 0($4)724 725 ret void726 ; CHECK: .size clti_u_v2i64727}728 729define void @bsel_s_v16i8(ptr %d, ptr %a, ptr %b,730 ptr %c) nounwind {731 ; CHECK: bsel_s_v16i8:732 733 %1 = load <16 x i8>, ptr %a734 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)735 %2 = load <16 x i8>, ptr %b736 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)737 %3 = load <16 x i8>, ptr %c738 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)739 %4 = icmp sgt <16 x i8> %1, %2740 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]741 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3742 ; bmnz.v is the same operation743 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]744 store <16 x i8> %5, ptr %d745 ; CHECK-DAG: st.b [[R3]], 0($4)746 747 ret void748 ; CHECK: .size bsel_s_v16i8749}750 751define void @bsel_s_v8i16(ptr %d, ptr %a, ptr %b,752 ptr %c) nounwind {753 ; CHECK: bsel_s_v8i16:754 755 %1 = load <8 x i16>, ptr %a756 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)757 %2 = load <8 x i16>, ptr %b758 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)759 %3 = load <8 x i16>, ptr %c760 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)761 %4 = icmp sgt <8 x i16> %1, %2762 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]763 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3764 ; Note that IfSet and IfClr are swapped since the condition is inverted765 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]766 store <8 x i16> %5, ptr %d767 ; CHECK-DAG: st.h [[R4]], 0($4)768 769 ret void770 ; CHECK: .size bsel_s_v8i16771}772 773define void @bsel_s_v4i32(ptr %d, ptr %a, ptr %b,774 ptr %c) nounwind {775 ; CHECK: bsel_s_v4i32:776 777 %1 = load <4 x i32>, ptr %a778 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)779 %2 = load <4 x i32>, ptr %b780 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)781 %3 = load <4 x i32>, ptr %c782 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)783 %4 = icmp sgt <4 x i32> %1, %2784 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]785 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3786 ; Note that IfSet and IfClr are swapped since the condition is inverted787 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]788 store <4 x i32> %5, ptr %d789 ; CHECK-DAG: st.w [[R4]], 0($4)790 791 ret void792 ; CHECK: .size bsel_s_v4i32793}794 795define void @bsel_s_v2i64(ptr %d, ptr %a, ptr %b,796 ptr %c) nounwind {797 ; CHECK: bsel_s_v2i64:798 799 %1 = load <2 x i64>, ptr %a800 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)801 %2 = load <2 x i64>, ptr %b802 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)803 %3 = load <2 x i64>, ptr %c804 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)805 %4 = icmp sgt <2 x i64> %1, %2806 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]807 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3808 ; Note that IfSet and IfClr are swapped since the condition is inverted809 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]810 store <2 x i64> %5, ptr %d811 ; CHECK-DAG: st.d [[R4]], 0($4)812 813 ret void814 ; CHECK: .size bsel_s_v2i64815}816 817define void @bsel_u_v16i8(ptr %d, ptr %a, ptr %b,818 ptr %c) nounwind {819 ; CHECK: bsel_u_v16i8:820 821 %1 = load <16 x i8>, ptr %a822 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)823 %2 = load <16 x i8>, ptr %b824 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)825 %3 = load <16 x i8>, ptr %c826 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)827 %4 = icmp ugt <16 x i8> %1, %2828 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]829 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3830 ; bmnz.v is the same operation831 ; CHECK-DAG: bmnz.v [[R3]], [[R1]], [[R4]]832 store <16 x i8> %5, ptr %d833 ; CHECK-DAG: st.b [[R3]], 0($4)834 835 ret void836 ; CHECK: .size bsel_u_v16i8837}838 839define void @bsel_u_v8i16(ptr %d, ptr %a, ptr %b,840 ptr %c) nounwind {841 ; CHECK: bsel_u_v8i16:842 843 %1 = load <8 x i16>, ptr %a844 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)845 %2 = load <8 x i16>, ptr %b846 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)847 %3 = load <8 x i16>, ptr %c848 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)849 %4 = icmp ugt <8 x i16> %1, %2850 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]851 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3852 ; Note that IfSet and IfClr are swapped since the condition is inverted853 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]854 store <8 x i16> %5, ptr %d855 ; CHECK-DAG: st.h [[R4]], 0($4)856 857 ret void858 ; CHECK: .size bsel_u_v8i16859}860 861define void @bsel_u_v4i32(ptr %d, ptr %a, ptr %b,862 ptr %c) nounwind {863 ; CHECK: bsel_u_v4i32:864 865 %1 = load <4 x i32>, ptr %a866 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)867 %2 = load <4 x i32>, ptr %b868 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)869 %3 = load <4 x i32>, ptr %c870 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)871 %4 = icmp ugt <4 x i32> %1, %2872 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]873 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3874 ; Note that IfSet and IfClr are swapped since the condition is inverted875 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]876 store <4 x i32> %5, ptr %d877 ; CHECK-DAG: st.w [[R4]], 0($4)878 879 ret void880 ; CHECK: .size bsel_u_v4i32881}882 883define void @bsel_u_v2i64(ptr %d, ptr %a, ptr %b,884 ptr %c) nounwind {885 ; CHECK: bsel_u_v2i64:886 887 %1 = load <2 x i64>, ptr %a888 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)889 %2 = load <2 x i64>, ptr %b890 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)891 %3 = load <2 x i64>, ptr %c892 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)893 %4 = icmp ugt <2 x i64> %1, %2894 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]895 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3896 ; Note that IfSet and IfClr are swapped since the condition is inverted897 ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]]898 store <2 x i64> %5, ptr %d899 ; CHECK-DAG: st.d [[R4]], 0($4)900 901 ret void902 ; CHECK: .size bsel_u_v2i64903}904 905define void @bseli_s_v16i8(ptr %d, ptr %a, ptr %b,906 ptr %c) nounwind {907 ; CHECK: bseli_s_v16i8:908 909 %1 = load <16 x i8>, ptr %a910 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)911 %2 = load <16 x i8>, ptr %b912 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)913 %3 = icmp sgt <16 x i8> %1, %2914 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]915 %4 = select <16 x i1> %3, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> %1916 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1917 store <16 x i8> %4, ptr %d918 ; CHECK-DAG: st.b [[R4]], 0($4)919 920 ret void921 ; CHECK: .size bseli_s_v16i8922}923 924define void @bseli_s_v8i16(ptr %d, ptr %a, ptr %b,925 ptr %c) nounwind {926 ; CHECK: bseli_s_v8i16:927 928 %1 = load <8 x i16>, ptr %a929 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)930 %2 = load <8 x i16>, ptr %b931 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)932 %3 = icmp sgt <8 x i16> %1, %2933 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]934 %4 = select <8 x i1> %3, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %1935 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1936 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]937 store <8 x i16> %4, ptr %d938 ; CHECK-DAG: st.h [[R4]], 0($4)939 940 ret void941 ; CHECK: .size bseli_s_v8i16942}943 944define void @bseli_s_v4i32(ptr %d, ptr %a, ptr %b,945 ptr %c) nounwind {946 ; CHECK: bseli_s_v4i32:947 948 %1 = load <4 x i32>, ptr %a949 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)950 %2 = load <4 x i32>, ptr %b951 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)952 %3 = icmp sgt <4 x i32> %1, %2953 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]954 %4 = select <4 x i1> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> %1955 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1956 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]957 store <4 x i32> %4, ptr %d958 ; CHECK-DAG: st.w [[R4]], 0($4)959 960 ret void961 ; CHECK: .size bseli_s_v4i32962}963 964define void @bseli_s_v2i64(ptr %d, ptr %a, ptr %b,965 ptr %c) nounwind {966 ; CHECK: bseli_s_v2i64:967 968 %1 = load <2 x i64>, ptr %a969 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)970 %2 = load <2 x i64>, ptr %b971 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)972 %3 = icmp sgt <2 x i64> %1, %2973 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]974 %4 = select <2 x i1> %3, <2 x i64> <i64 1, i64 1>, <2 x i64> %1975 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1976 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]977 store <2 x i64> %4, ptr %d978 ; CHECK-DAG: st.d [[R4]], 0($4)979 980 ret void981 ; CHECK: .size bseli_s_v2i64982}983 984define void @bseli_u_v16i8(ptr %d, ptr %a, ptr %b,985 ptr %c) nounwind {986 ; CHECK: bseli_u_v16i8:987 988 %1 = load <16 x i8>, ptr %a989 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)990 %2 = load <16 x i8>, ptr %b991 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)992 %3 = icmp ugt <16 x i8> %1, %2993 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]994 %4 = select <16 x i1> %3, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> %1995 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1996 store <16 x i8> %4, ptr %d997 ; CHECK-DAG: st.b [[R4]], 0($4)998 999 ret void1000 ; CHECK: .size bseli_u_v16i81001}1002 1003define void @bseli_u_v8i16(ptr %d, ptr %a, ptr %b,1004 ptr %c) nounwind {1005 ; CHECK: bseli_u_v8i16:1006 1007 %1 = load <8 x i16>, ptr %a1008 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1009 %2 = load <8 x i16>, ptr %b1010 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1011 %3 = icmp ugt <8 x i16> %1, %21012 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]1013 %4 = select <8 x i1> %3, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %11014 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 11015 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]1016 store <8 x i16> %4, ptr %d1017 ; CHECK-DAG: st.h [[R4]], 0($4)1018 1019 ret void1020 ; CHECK: .size bseli_u_v8i161021}1022 1023define void @bseli_u_v4i32(ptr %d, ptr %a, ptr %b,1024 ptr %c) nounwind {1025 ; CHECK: bseli_u_v4i32:1026 1027 %1 = load <4 x i32>, ptr %a1028 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1029 %2 = load <4 x i32>, ptr %b1030 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1031 %3 = icmp ugt <4 x i32> %1, %21032 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]1033 %4 = select <4 x i1> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> %11034 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 11035 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]1036 store <4 x i32> %4, ptr %d1037 ; CHECK-DAG: st.w [[R4]], 0($4)1038 1039 ret void1040 ; CHECK: .size bseli_u_v4i321041}1042 1043define void @bseli_u_v2i64(ptr %d, ptr %a, ptr %b,1044 ptr %c) nounwind {1045 ; CHECK: bseli_u_v2i64:1046 1047 %1 = load <2 x i64>, ptr %a1048 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1049 %2 = load <2 x i64>, ptr %b1050 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1051 %3 = icmp ugt <2 x i64> %1, %21052 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]1053 %4 = select <2 x i1> %3, <2 x i64> <i64 1, i64 1>, <2 x i64> %11054 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 11055 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]1056 store <2 x i64> %4, ptr %d1057 ; CHECK-DAG: st.d [[R4]], 0($4)1058 1059 ret void1060 ; CHECK: .size bseli_u_v2i641061}1062 1063define void @max_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1064 ; CHECK: max_s_v16i8:1065 1066 %1 = load <16 x i8>, ptr %a1067 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1068 %2 = load <16 x i8>, ptr %b1069 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1070 %3 = icmp sgt <16 x i8> %1, %21071 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21072 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1073 store <16 x i8> %4, ptr %c1074 ; CHECK-DAG: st.b [[R3]], 0($4)1075 1076 ret void1077 ; CHECK: .size max_s_v16i81078}1079 1080define void @max_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1081 ; CHECK: max_s_v8i16:1082 1083 %1 = load <8 x i16>, ptr %a1084 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1085 %2 = load <8 x i16>, ptr %b1086 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1087 %3 = icmp sgt <8 x i16> %1, %21088 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21089 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1090 store <8 x i16> %4, ptr %c1091 ; CHECK-DAG: st.h [[R3]], 0($4)1092 1093 ret void1094 ; CHECK: .size max_s_v8i161095}1096 1097define void @max_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1098 ; CHECK: max_s_v4i32:1099 1100 %1 = load <4 x i32>, ptr %a1101 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1102 %2 = load <4 x i32>, ptr %b1103 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1104 %3 = icmp sgt <4 x i32> %1, %21105 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21106 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1107 store <4 x i32> %4, ptr %c1108 ; CHECK-DAG: st.w [[R3]], 0($4)1109 1110 ret void1111 ; CHECK: .size max_s_v4i321112}1113 1114define void @max_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1115 ; CHECK: max_s_v2i64:1116 1117 %1 = load <2 x i64>, ptr %a1118 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1119 %2 = load <2 x i64>, ptr %b1120 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1121 %3 = icmp sgt <2 x i64> %1, %21122 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21123 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1124 store <2 x i64> %4, ptr %c1125 ; CHECK-DAG: st.d [[R3]], 0($4)1126 1127 ret void1128 ; CHECK: .size max_s_v2i641129}1130 1131define void @max_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1132 ; CHECK: max_u_v16i8:1133 1134 %1 = load <16 x i8>, ptr %a1135 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1136 %2 = load <16 x i8>, ptr %b1137 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1138 %3 = icmp ugt <16 x i8> %1, %21139 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21140 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1141 store <16 x i8> %4, ptr %c1142 ; CHECK-DAG: st.b [[R3]], 0($4)1143 1144 ret void1145 ; CHECK: .size max_u_v16i81146}1147 1148define void @max_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1149 ; CHECK: max_u_v8i16:1150 1151 %1 = load <8 x i16>, ptr %a1152 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1153 %2 = load <8 x i16>, ptr %b1154 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1155 %3 = icmp ugt <8 x i16> %1, %21156 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21157 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1158 store <8 x i16> %4, ptr %c1159 ; CHECK-DAG: st.h [[R3]], 0($4)1160 1161 ret void1162 ; CHECK: .size max_u_v8i161163}1164 1165define void @max_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1166 ; CHECK: max_u_v4i32:1167 1168 %1 = load <4 x i32>, ptr %a1169 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1170 %2 = load <4 x i32>, ptr %b1171 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1172 %3 = icmp ugt <4 x i32> %1, %21173 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21174 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1175 store <4 x i32> %4, ptr %c1176 ; CHECK-DAG: st.w [[R3]], 0($4)1177 1178 ret void1179 ; CHECK: .size max_u_v4i321180}1181 1182define void @max_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1183 ; CHECK: max_u_v2i64:1184 1185 %1 = load <2 x i64>, ptr %a1186 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1187 %2 = load <2 x i64>, ptr %b1188 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1189 %3 = icmp ugt <2 x i64> %1, %21190 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21191 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1192 store <2 x i64> %4, ptr %c1193 ; CHECK-DAG: st.d [[R3]], 0($4)1194 1195 ret void1196 ; CHECK: .size max_u_v2i641197}1198 1199define void @max_s_eq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1200 ; CHECK: max_s_eq_v16i8:1201 1202 %1 = load <16 x i8>, ptr %a1203 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1204 %2 = load <16 x i8>, ptr %b1205 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1206 %3 = icmp sge <16 x i8> %1, %21207 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21208 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1209 store <16 x i8> %4, ptr %c1210 ; CHECK-DAG: st.b [[R3]], 0($4)1211 1212 ret void1213 ; CHECK: .size max_s_eq_v16i81214}1215 1216define void @max_s_eq_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1217 ; CHECK: max_s_eq_v8i16:1218 1219 %1 = load <8 x i16>, ptr %a1220 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1221 %2 = load <8 x i16>, ptr %b1222 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1223 %3 = icmp sge <8 x i16> %1, %21224 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21225 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1226 store <8 x i16> %4, ptr %c1227 ; CHECK-DAG: st.h [[R3]], 0($4)1228 1229 ret void1230 ; CHECK: .size max_s_eq_v8i161231}1232 1233define void @max_s_eq_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1234 ; CHECK: max_s_eq_v4i32:1235 1236 %1 = load <4 x i32>, ptr %a1237 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1238 %2 = load <4 x i32>, ptr %b1239 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1240 %3 = icmp sge <4 x i32> %1, %21241 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21242 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1243 store <4 x i32> %4, ptr %c1244 ; CHECK-DAG: st.w [[R3]], 0($4)1245 1246 ret void1247 ; CHECK: .size max_s_eq_v4i321248}1249 1250define void @max_s_eq_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1251 ; CHECK: max_s_eq_v2i64:1252 1253 %1 = load <2 x i64>, ptr %a1254 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1255 %2 = load <2 x i64>, ptr %b1256 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1257 %3 = icmp sge <2 x i64> %1, %21258 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21259 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1260 store <2 x i64> %4, ptr %c1261 ; CHECK-DAG: st.d [[R3]], 0($4)1262 1263 ret void1264 ; CHECK: .size max_s_eq_v2i641265}1266 1267define void @max_u_eq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1268 ; CHECK: max_u_eq_v16i8:1269 1270 %1 = load <16 x i8>, ptr %a1271 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1272 %2 = load <16 x i8>, ptr %b1273 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1274 %3 = icmp uge <16 x i8> %1, %21275 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21276 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1277 store <16 x i8> %4, ptr %c1278 ; CHECK-DAG: st.b [[R3]], 0($4)1279 1280 ret void1281 ; CHECK: .size max_u_eq_v16i81282}1283 1284define void @max_u_eq_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1285 ; CHECK: max_u_eq_v8i16:1286 1287 %1 = load <8 x i16>, ptr %a1288 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1289 %2 = load <8 x i16>, ptr %b1290 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1291 %3 = icmp uge <8 x i16> %1, %21292 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21293 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1294 store <8 x i16> %4, ptr %c1295 ; CHECK-DAG: st.h [[R3]], 0($4)1296 1297 ret void1298 ; CHECK: .size max_u_eq_v8i161299}1300 1301define void @max_u_eq_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1302 ; CHECK: max_u_eq_v4i32:1303 1304 %1 = load <4 x i32>, ptr %a1305 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1306 %2 = load <4 x i32>, ptr %b1307 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1308 %3 = icmp uge <4 x i32> %1, %21309 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21310 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1311 store <4 x i32> %4, ptr %c1312 ; CHECK-DAG: st.w [[R3]], 0($4)1313 1314 ret void1315 ; CHECK: .size max_u_eq_v4i321316}1317 1318define void @max_u_eq_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1319 ; CHECK: max_u_eq_v2i64:1320 1321 %1 = load <2 x i64>, ptr %a1322 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1323 %2 = load <2 x i64>, ptr %b1324 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1325 %3 = icmp uge <2 x i64> %1, %21326 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21327 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1328 store <2 x i64> %4, ptr %c1329 ; CHECK-DAG: st.d [[R3]], 0($4)1330 1331 ret void1332 ; CHECK: .size max_u_eq_v2i641333}1334 1335define void @maxi_s_v16i8(ptr %c, ptr %a) nounwind {1336 ; CHECK: maxi_s_v16i8:1337 1338 %1 = load <16 x i8>, ptr %a1339 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1340 %2 = icmp sgt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1341 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1342 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 11343 store <16 x i8> %3, ptr %c1344 ; CHECK-DAG: st.b [[R3]], 0($4)1345 1346 ret void1347 ; CHECK: .size maxi_s_v16i81348}1349 1350define void @maxi_s_v8i16(ptr %c, ptr %a) nounwind {1351 ; CHECK: maxi_s_v8i16:1352 1353 %1 = load <8 x i16>, ptr %a1354 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1355 %2 = icmp sgt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1356 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1357 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 11358 store <8 x i16> %3, ptr %c1359 ; CHECK-DAG: st.h [[R3]], 0($4)1360 1361 ret void1362 ; CHECK: .size maxi_s_v8i161363}1364 1365define void @maxi_s_v4i32(ptr %c, ptr %a) nounwind {1366 ; CHECK: maxi_s_v4i32:1367 1368 %1 = load <4 x i32>, ptr %a1369 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1370 %2 = icmp sgt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1371 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1372 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 11373 store <4 x i32> %3, ptr %c1374 ; CHECK-DAG: st.w [[R3]], 0($4)1375 1376 ret void1377 ; CHECK: .size maxi_s_v4i321378}1379 1380define void @maxi_s_v2i64(ptr %c, ptr %a) nounwind {1381 ; CHECK: maxi_s_v2i64:1382 1383 %1 = load <2 x i64>, ptr %a1384 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1385 %2 = icmp sgt <2 x i64> %1, <i64 1, i64 1>1386 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1387 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 11388 store <2 x i64> %3, ptr %c1389 ; CHECK-DAG: st.d [[R3]], 0($4)1390 1391 ret void1392 ; CHECK: .size maxi_s_v2i641393}1394 1395define void @maxi_u_v16i8(ptr %c, ptr %a) nounwind {1396 ; CHECK: maxi_u_v16i8:1397 1398 %1 = load <16 x i8>, ptr %a1399 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1400 %2 = icmp ugt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1401 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1402 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 11403 store <16 x i8> %3, ptr %c1404 ; CHECK-DAG: st.b [[R3]], 0($4)1405 1406 ret void1407 ; CHECK: .size maxi_u_v16i81408}1409 1410define void @maxi_u_v8i16(ptr %c, ptr %a) nounwind {1411 ; CHECK: maxi_u_v8i16:1412 1413 %1 = load <8 x i16>, ptr %a1414 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1415 %2 = icmp ugt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1416 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1417 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 11418 store <8 x i16> %3, ptr %c1419 ; CHECK-DAG: st.h [[R3]], 0($4)1420 1421 ret void1422 ; CHECK: .size maxi_u_v8i161423}1424 1425define void @maxi_u_v4i32(ptr %c, ptr %a) nounwind {1426 ; CHECK: maxi_u_v4i32:1427 1428 %1 = load <4 x i32>, ptr %a1429 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1430 %2 = icmp ugt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1431 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1432 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 11433 store <4 x i32> %3, ptr %c1434 ; CHECK-DAG: st.w [[R3]], 0($4)1435 1436 ret void1437 ; CHECK: .size maxi_u_v4i321438}1439 1440define void @maxi_u_v2i64(ptr %c, ptr %a) nounwind {1441 ; CHECK: maxi_u_v2i64:1442 1443 %1 = load <2 x i64>, ptr %a1444 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1445 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>1446 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1447 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 11448 store <2 x i64> %3, ptr %c1449 ; CHECK-DAG: st.d [[R3]], 0($4)1450 1451 ret void1452 ; CHECK: .size maxi_u_v2i641453}1454 1455define void @maxi_s_eq_v16i8(ptr %c, ptr %a) nounwind {1456 ; CHECK: maxi_s_eq_v16i8:1457 1458 %1 = load <16 x i8>, ptr %a1459 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1460 %2 = icmp sge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1461 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1462 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 11463 store <16 x i8> %3, ptr %c1464 ; CHECK-DAG: st.b [[R3]], 0($4)1465 1466 ret void1467 ; CHECK: .size maxi_s_eq_v16i81468}1469 1470define void @maxi_s_eq_v8i16(ptr %c, ptr %a) nounwind {1471 ; CHECK: maxi_s_eq_v8i16:1472 1473 %1 = load <8 x i16>, ptr %a1474 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1475 %2 = icmp sge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1476 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1477 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 11478 store <8 x i16> %3, ptr %c1479 ; CHECK-DAG: st.h [[R3]], 0($4)1480 1481 ret void1482 ; CHECK: .size maxi_s_eq_v8i161483}1484 1485define void @maxi_s_eq_v4i32(ptr %c, ptr %a) nounwind {1486 ; CHECK: maxi_s_eq_v4i32:1487 1488 %1 = load <4 x i32>, ptr %a1489 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1490 %2 = icmp sge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1491 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1492 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 11493 store <4 x i32> %3, ptr %c1494 ; CHECK-DAG: st.w [[R3]], 0($4)1495 1496 ret void1497 ; CHECK: .size maxi_s_eq_v4i321498}1499 1500define void @maxi_s_eq_v2i64(ptr %c, ptr %a) nounwind {1501 ; CHECK: maxi_s_eq_v2i64:1502 1503 %1 = load <2 x i64>, ptr %a1504 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1505 %2 = icmp sge <2 x i64> %1, <i64 1, i64 1>1506 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1507 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 11508 store <2 x i64> %3, ptr %c1509 ; CHECK-DAG: st.d [[R3]], 0($4)1510 1511 ret void1512 ; CHECK: .size maxi_s_eq_v2i641513}1514 1515define void @maxi_u_eq_v16i8(ptr %c, ptr %a) nounwind {1516 ; CHECK: maxi_u_eq_v16i8:1517 1518 %1 = load <16 x i8>, ptr %a1519 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1520 %2 = icmp uge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1521 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1522 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 11523 store <16 x i8> %3, ptr %c1524 ; CHECK-DAG: st.b [[R3]], 0($4)1525 1526 ret void1527 ; CHECK: .size maxi_u_eq_v16i81528}1529 1530define void @maxi_u_eq_v8i16(ptr %c, ptr %a) nounwind {1531 ; CHECK: maxi_u_eq_v8i16:1532 1533 %1 = load <8 x i16>, ptr %a1534 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1535 %2 = icmp uge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1536 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1537 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 11538 store <8 x i16> %3, ptr %c1539 ; CHECK-DAG: st.h [[R3]], 0($4)1540 1541 ret void1542 ; CHECK: .size maxi_u_eq_v8i161543}1544 1545define void @maxi_u_eq_v4i32(ptr %c, ptr %a) nounwind {1546 ; CHECK: maxi_u_eq_v4i32:1547 1548 %1 = load <4 x i32>, ptr %a1549 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1550 %2 = icmp uge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1551 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1552 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 11553 store <4 x i32> %3, ptr %c1554 ; CHECK-DAG: st.w [[R3]], 0($4)1555 1556 ret void1557 ; CHECK: .size maxi_u_eq_v4i321558}1559 1560define void @maxi_u_eq_v2i64(ptr %c, ptr %a) nounwind {1561 ; CHECK: maxi_u_eq_v2i64:1562 1563 %1 = load <2 x i64>, ptr %a1564 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1565 %2 = icmp uge <2 x i64> %1, <i64 1, i64 1>1566 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1567 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 11568 store <2 x i64> %3, ptr %c1569 ; CHECK-DAG: st.d [[R3]], 0($4)1570 1571 ret void1572 ; CHECK: .size maxi_u_eq_v2i641573}1574 1575define void @min_s_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1576 ; CHECK: min_s_v16i8:1577 1578 %1 = load <16 x i8>, ptr %a1579 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1580 %2 = load <16 x i8>, ptr %b1581 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1582 %3 = icmp sle <16 x i8> %1, %21583 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21584 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1585 store <16 x i8> %4, ptr %c1586 ; CHECK-DAG: st.b [[R3]], 0($4)1587 1588 ret void1589 ; CHECK: .size min_s_v16i81590}1591 1592define void @min_s_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1593 ; CHECK: min_s_v8i16:1594 1595 %1 = load <8 x i16>, ptr %a1596 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1597 %2 = load <8 x i16>, ptr %b1598 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1599 %3 = icmp slt <8 x i16> %1, %21600 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21601 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1602 store <8 x i16> %4, ptr %c1603 ; CHECK-DAG: st.h [[R3]], 0($4)1604 1605 ret void1606 ; CHECK: .size min_s_v8i161607}1608 1609define void @min_s_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1610 ; CHECK: min_s_v4i32:1611 1612 %1 = load <4 x i32>, ptr %a1613 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1614 %2 = load <4 x i32>, ptr %b1615 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1616 %3 = icmp slt <4 x i32> %1, %21617 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21618 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1619 store <4 x i32> %4, ptr %c1620 ; CHECK-DAG: st.w [[R3]], 0($4)1621 1622 ret void1623 ; CHECK: .size min_s_v4i321624}1625 1626define void @min_s_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1627 ; CHECK: min_s_v2i64:1628 1629 %1 = load <2 x i64>, ptr %a1630 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1631 %2 = load <2 x i64>, ptr %b1632 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1633 %3 = icmp slt <2 x i64> %1, %21634 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21635 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1636 store <2 x i64> %4, ptr %c1637 ; CHECK-DAG: st.d [[R3]], 0($4)1638 1639 ret void1640 ; CHECK: .size min_s_v2i641641}1642 1643define void @min_u_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1644 ; CHECK: min_u_v16i8:1645 1646 %1 = load <16 x i8>, ptr %a1647 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1648 %2 = load <16 x i8>, ptr %b1649 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1650 %3 = icmp ult <16 x i8> %1, %21651 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21652 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1653 store <16 x i8> %4, ptr %c1654 ; CHECK-DAG: st.b [[R3]], 0($4)1655 1656 ret void1657 ; CHECK: .size min_u_v16i81658}1659 1660define void @min_u_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1661 ; CHECK: min_u_v8i16:1662 1663 %1 = load <8 x i16>, ptr %a1664 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1665 %2 = load <8 x i16>, ptr %b1666 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1667 %3 = icmp ult <8 x i16> %1, %21668 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21669 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1670 store <8 x i16> %4, ptr %c1671 ; CHECK-DAG: st.h [[R3]], 0($4)1672 1673 ret void1674 ; CHECK: .size min_u_v8i161675}1676 1677define void @min_u_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1678 ; CHECK: min_u_v4i32:1679 1680 %1 = load <4 x i32>, ptr %a1681 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1682 %2 = load <4 x i32>, ptr %b1683 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1684 %3 = icmp ult <4 x i32> %1, %21685 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21686 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1687 store <4 x i32> %4, ptr %c1688 ; CHECK-DAG: st.w [[R3]], 0($4)1689 1690 ret void1691 ; CHECK: .size min_u_v4i321692}1693 1694define void @min_u_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1695 ; CHECK: min_u_v2i64:1696 1697 %1 = load <2 x i64>, ptr %a1698 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1699 %2 = load <2 x i64>, ptr %b1700 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1701 %3 = icmp ult <2 x i64> %1, %21702 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21703 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1704 store <2 x i64> %4, ptr %c1705 ; CHECK-DAG: st.d [[R3]], 0($4)1706 1707 ret void1708 ; CHECK: .size min_u_v2i641709}1710 1711define void @min_s_eq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1712 ; CHECK: min_s_eq_v16i8:1713 1714 %1 = load <16 x i8>, ptr %a1715 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1716 %2 = load <16 x i8>, ptr %b1717 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1718 %3 = icmp sle <16 x i8> %1, %21719 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21720 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1721 store <16 x i8> %4, ptr %c1722 ; CHECK-DAG: st.b [[R3]], 0($4)1723 1724 ret void1725 ; CHECK: .size min_s_eq_v16i81726}1727 1728define void @min_s_eq_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1729 ; CHECK: min_s_eq_v8i16:1730 1731 %1 = load <8 x i16>, ptr %a1732 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1733 %2 = load <8 x i16>, ptr %b1734 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1735 %3 = icmp sle <8 x i16> %1, %21736 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21737 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1738 store <8 x i16> %4, ptr %c1739 ; CHECK-DAG: st.h [[R3]], 0($4)1740 1741 ret void1742 ; CHECK: .size min_s_eq_v8i161743}1744 1745define void @min_s_eq_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1746 ; CHECK: min_s_eq_v4i32:1747 1748 %1 = load <4 x i32>, ptr %a1749 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1750 %2 = load <4 x i32>, ptr %b1751 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1752 %3 = icmp sle <4 x i32> %1, %21753 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21754 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1755 store <4 x i32> %4, ptr %c1756 ; CHECK-DAG: st.w [[R3]], 0($4)1757 1758 ret void1759 ; CHECK: .size min_s_eq_v4i321760}1761 1762define void @min_s_eq_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1763 ; CHECK: min_s_eq_v2i64:1764 1765 %1 = load <2 x i64>, ptr %a1766 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1767 %2 = load <2 x i64>, ptr %b1768 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1769 %3 = icmp sle <2 x i64> %1, %21770 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21771 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1772 store <2 x i64> %4, ptr %c1773 ; CHECK-DAG: st.d [[R3]], 0($4)1774 1775 ret void1776 ; CHECK: .size min_s_eq_v2i641777}1778 1779define void @min_u_eq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {1780 ; CHECK: min_u_eq_v16i8:1781 1782 %1 = load <16 x i8>, ptr %a1783 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1784 %2 = load <16 x i8>, ptr %b1785 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)1786 %3 = icmp ule <16 x i8> %1, %21787 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %21788 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]1789 store <16 x i8> %4, ptr %c1790 ; CHECK-DAG: st.b [[R3]], 0($4)1791 1792 ret void1793 ; CHECK: .size min_u_eq_v16i81794}1795 1796define void @min_u_eq_v8i16(ptr %c, ptr %a, ptr %b) nounwind {1797 ; CHECK: min_u_eq_v8i16:1798 1799 %1 = load <8 x i16>, ptr %a1800 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1801 %2 = load <8 x i16>, ptr %b1802 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)1803 %3 = icmp ule <8 x i16> %1, %21804 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %21805 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]1806 store <8 x i16> %4, ptr %c1807 ; CHECK-DAG: st.h [[R3]], 0($4)1808 1809 ret void1810 ; CHECK: .size min_u_eq_v8i161811}1812 1813define void @min_u_eq_v4i32(ptr %c, ptr %a, ptr %b) nounwind {1814 ; CHECK: min_u_eq_v4i32:1815 1816 %1 = load <4 x i32>, ptr %a1817 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1818 %2 = load <4 x i32>, ptr %b1819 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)1820 %3 = icmp ule <4 x i32> %1, %21821 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %21822 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]1823 store <4 x i32> %4, ptr %c1824 ; CHECK-DAG: st.w [[R3]], 0($4)1825 1826 ret void1827 ; CHECK: .size min_u_eq_v4i321828}1829 1830define void @min_u_eq_v2i64(ptr %c, ptr %a, ptr %b) nounwind {1831 ; CHECK: min_u_eq_v2i64:1832 1833 %1 = load <2 x i64>, ptr %a1834 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1835 %2 = load <2 x i64>, ptr %b1836 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)1837 %3 = icmp ule <2 x i64> %1, %21838 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %21839 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]1840 store <2 x i64> %4, ptr %c1841 ; CHECK-DAG: st.d [[R3]], 0($4)1842 1843 ret void1844 ; CHECK: .size min_u_eq_v2i641845}1846 1847define void @mini_s_v16i8(ptr %c, ptr %a) nounwind {1848 ; CHECK: mini_s_v16i8:1849 1850 %1 = load <16 x i8>, ptr %a1851 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1852 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1853 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1854 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 11855 store <16 x i8> %3, ptr %c1856 ; CHECK-DAG: st.b [[R3]], 0($4)1857 1858 ret void1859 ; CHECK: .size mini_s_v16i81860}1861 1862define void @mini_s_v8i16(ptr %c, ptr %a) nounwind {1863 ; CHECK: mini_s_v8i16:1864 1865 %1 = load <8 x i16>, ptr %a1866 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1867 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1868 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1869 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 11870 store <8 x i16> %3, ptr %c1871 ; CHECK-DAG: st.h [[R3]], 0($4)1872 1873 ret void1874 ; CHECK: .size mini_s_v8i161875}1876 1877define void @mini_s_v4i32(ptr %c, ptr %a) nounwind {1878 ; CHECK: mini_s_v4i32:1879 1880 %1 = load <4 x i32>, ptr %a1881 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1882 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1883 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1884 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 11885 store <4 x i32> %3, ptr %c1886 ; CHECK-DAG: st.w [[R3]], 0($4)1887 1888 ret void1889 ; CHECK: .size mini_s_v4i321890}1891 1892define void @mini_s_v2i64(ptr %c, ptr %a) nounwind {1893 ; CHECK: mini_s_v2i64:1894 1895 %1 = load <2 x i64>, ptr %a1896 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1897 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>1898 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1899 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 11900 store <2 x i64> %3, ptr %c1901 ; CHECK-DAG: st.d [[R3]], 0($4)1902 1903 ret void1904 ; CHECK: .size mini_s_v2i641905}1906 1907define void @mini_u_v16i8(ptr %c, ptr %a) nounwind {1908 ; CHECK: mini_u_v16i8:1909 1910 %1 = load <16 x i8>, ptr %a1911 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1912 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1913 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1914 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 11915 store <16 x i8> %3, ptr %c1916 ; CHECK-DAG: st.b [[R3]], 0($4)1917 1918 ret void1919 ; CHECK: .size mini_u_v16i81920}1921 1922define void @mini_u_v8i16(ptr %c, ptr %a) nounwind {1923 ; CHECK: mini_u_v8i16:1924 1925 %1 = load <8 x i16>, ptr %a1926 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1927 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1928 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1929 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 11930 store <8 x i16> %3, ptr %c1931 ; CHECK-DAG: st.h [[R3]], 0($4)1932 1933 ret void1934 ; CHECK: .size mini_u_v8i161935}1936 1937define void @mini_u_v4i32(ptr %c, ptr %a) nounwind {1938 ; CHECK: mini_u_v4i32:1939 1940 %1 = load <4 x i32>, ptr %a1941 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)1942 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>1943 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1944 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 11945 store <4 x i32> %3, ptr %c1946 ; CHECK-DAG: st.w [[R3]], 0($4)1947 1948 ret void1949 ; CHECK: .size mini_u_v4i321950}1951 1952define void @mini_u_v2i64(ptr %c, ptr %a) nounwind {1953 ; CHECK: mini_u_v2i64:1954 1955 %1 = load <2 x i64>, ptr %a1956 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)1957 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>1958 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>1959 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 11960 store <2 x i64> %3, ptr %c1961 ; CHECK-DAG: st.d [[R3]], 0($4)1962 1963 ret void1964 ; CHECK: .size mini_u_v2i641965}1966 1967define void @mini_s_eq_v16i8(ptr %c, ptr %a) nounwind {1968 ; CHECK: mini_s_eq_v16i8:1969 1970 %1 = load <16 x i8>, ptr %a1971 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)1972 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1973 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1974 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 11975 store <16 x i8> %3, ptr %c1976 ; CHECK-DAG: st.b [[R3]], 0($4)1977 1978 ret void1979 ; CHECK: .size mini_s_eq_v16i81980}1981 1982define void @mini_s_eq_v8i16(ptr %c, ptr %a) nounwind {1983 ; CHECK: mini_s_eq_v8i16:1984 1985 %1 = load <8 x i16>, ptr %a1986 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)1987 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1988 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1989 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 11990 store <8 x i16> %3, ptr %c1991 ; CHECK-DAG: st.h [[R3]], 0($4)1992 1993 ret void1994 ; CHECK: .size mini_s_eq_v8i161995}1996 1997define void @mini_s_eq_v4i32(ptr %c, ptr %a) nounwind {1998 ; CHECK: mini_s_eq_v4i32:1999 2000 %1 = load <4 x i32>, ptr %a2001 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)2002 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>2003 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>2004 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 12005 store <4 x i32> %3, ptr %c2006 ; CHECK-DAG: st.w [[R3]], 0($4)2007 2008 ret void2009 ; CHECK: .size mini_s_eq_v4i322010}2011 2012define void @mini_s_eq_v2i64(ptr %c, ptr %a) nounwind {2013 ; CHECK: mini_s_eq_v2i64:2014 2015 %1 = load <2 x i64>, ptr %a2016 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)2017 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>2018 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>2019 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 12020 store <2 x i64> %3, ptr %c2021 ; CHECK-DAG: st.d [[R3]], 0($4)2022 2023 ret void2024 ; CHECK: .size mini_s_eq_v2i642025}2026 2027define void @mini_u_eq_v16i8(ptr %c, ptr %a) nounwind {2028 ; CHECK: mini_u_eq_v16i8:2029 2030 %1 = load <16 x i8>, ptr %a2031 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)2032 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>2033 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>2034 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 12035 store <16 x i8> %3, ptr %c2036 ; CHECK-DAG: st.b [[R3]], 0($4)2037 2038 ret void2039 ; CHECK: .size mini_u_eq_v16i82040}2041 2042define void @mini_u_eq_v8i16(ptr %c, ptr %a) nounwind {2043 ; CHECK: mini_u_eq_v8i16:2044 2045 %1 = load <8 x i16>, ptr %a2046 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)2047 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2048 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2049 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 12050 store <8 x i16> %3, ptr %c2051 ; CHECK-DAG: st.h [[R3]], 0($4)2052 2053 ret void2054 ; CHECK: .size mini_u_eq_v8i162055}2056 2057define void @mini_u_eq_v4i32(ptr %c, ptr %a) nounwind {2058 ; CHECK: mini_u_eq_v4i32:2059 2060 %1 = load <4 x i32>, ptr %a2061 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)2062 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>2063 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>2064 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 12065 store <4 x i32> %3, ptr %c2066 ; CHECK-DAG: st.w [[R3]], 0($4)2067 2068 ret void2069 ; CHECK: .size mini_u_eq_v4i322070}2071 2072define void @mini_u_eq_v2i64(ptr %c, ptr %a) nounwind {2073 ; CHECK: mini_u_eq_v2i64:2074 2075 %1 = load <2 x i64>, ptr %a2076 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)2077 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>2078 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>2079 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 12080 store <2 x i64> %3, ptr %c2081 ; CHECK-DAG: st.d [[R3]], 0($4)2082 2083 ret void2084 ; CHECK: .size mini_u_eq_v2i642085}2086