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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s3; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s4 5declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind6declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind7declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind8declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind9 10; (setcc $a, $b, SETFALSE) is always folded, so we won't get fcaf11define void @false_v4f32(ptr %c, ptr %a, ptr %b) nounwind {12; CHECK-LABEL: false_v4f32:13; CHECK: # %bb.0:14; CHECK-NEXT: ldi.b $w0, 015; CHECK-NEXT: jr $ra16; CHECK-NEXT: st.w $w0, 0($4)17 %1 = load <4 x float>, ptr %a18 %2 = load <4 x float>, ptr %b19 %3 = fcmp false <4 x float> %1, %220 %4 = sext <4 x i1> %3 to <4 x i32>21 store <4 x i32> %4, ptr %c22 ret void23}24 25; (setcc $a, $b, SETFALSE) is always folded26define void @false_v2f64(ptr %c, ptr %a, ptr %b) nounwind {27; CHECK-LABEL: false_v2f64:28; CHECK: # %bb.0:29; CHECK-NEXT: ldi.b $w0, 030; CHECK-NEXT: jr $ra31; CHECK-NEXT: st.w $w0, 0($4)32 %1 = load <2 x double>, ptr %a33 %2 = load <2 x double>, ptr %b34 %3 = fcmp false <2 x double> %1, %235 %4 = sext <2 x i1> %3 to <2 x i64>36 store <2 x i64> %4, ptr %c37 ret void38}39 40define void @oeq_v4f32(ptr %c, ptr %a, ptr %b) nounwind {41; CHECK-LABEL: oeq_v4f32:42; CHECK: # %bb.0:43; CHECK-NEXT: ld.w $w0, 0($6)44; CHECK-NEXT: ld.w $w1, 0($5)45; CHECK-NEXT: fceq.w $w0, $w1, $w046; CHECK-NEXT: jr $ra47; CHECK-NEXT: st.w $w0, 0($4)48 %1 = load <4 x float>, ptr %a49 %2 = load <4 x float>, ptr %b50 %3 = fcmp oeq <4 x float> %1, %251 %4 = sext <4 x i1> %3 to <4 x i32>52 store <4 x i32> %4, ptr %c53 ret void54}55 56define void @oeq_v2f64(ptr %c, ptr %a, ptr %b) nounwind {57; CHECK-LABEL: oeq_v2f64:58; CHECK: # %bb.0:59; CHECK-NEXT: ld.d $w0, 0($6)60; CHECK-NEXT: ld.d $w1, 0($5)61; CHECK-NEXT: fceq.d $w0, $w1, $w062; CHECK-NEXT: jr $ra63; CHECK-NEXT: st.d $w0, 0($4)64 %1 = load <2 x double>, ptr %a65 %2 = load <2 x double>, ptr %b66 %3 = fcmp oeq <2 x double> %1, %267 %4 = sext <2 x i1> %3 to <2 x i64>68 store <2 x i64> %4, ptr %c69 ret void70}71 72define void @oge_v4f32(ptr %c, ptr %a, ptr %b) nounwind {73; CHECK-LABEL: oge_v4f32:74; CHECK: # %bb.0:75; CHECK-NEXT: ld.w $w0, 0($5)76; CHECK-NEXT: ld.w $w1, 0($6)77; CHECK-NEXT: fcle.w $w0, $w1, $w078; CHECK-NEXT: jr $ra79; CHECK-NEXT: st.w $w0, 0($4)80 %1 = load <4 x float>, ptr %a81 %2 = load <4 x float>, ptr %b82 %3 = fcmp oge <4 x float> %1, %283 %4 = sext <4 x i1> %3 to <4 x i32>84 store <4 x i32> %4, ptr %c85 ret void86}87 88define void @oge_v2f64(ptr %c, ptr %a, ptr %b) nounwind {89; CHECK-LABEL: oge_v2f64:90; CHECK: # %bb.0:91; CHECK-NEXT: ld.d $w0, 0($5)92; CHECK-NEXT: ld.d $w1, 0($6)93; CHECK-NEXT: fcle.d $w0, $w1, $w094; CHECK-NEXT: jr $ra95; CHECK-NEXT: st.d $w0, 0($4)96 %1 = load <2 x double>, ptr %a97 %2 = load <2 x double>, ptr %b98 %3 = fcmp oge <2 x double> %1, %299 %4 = sext <2 x i1> %3 to <2 x i64>100 store <2 x i64> %4, ptr %c101 ret void102}103 104define void @ogt_v4f32(ptr %c, ptr %a, ptr %b) nounwind {105; CHECK-LABEL: ogt_v4f32:106; CHECK: # %bb.0:107; CHECK-NEXT: ld.w $w0, 0($5)108; CHECK-NEXT: ld.w $w1, 0($6)109; CHECK-NEXT: fclt.w $w0, $w1, $w0110; CHECK-NEXT: jr $ra111; CHECK-NEXT: st.w $w0, 0($4)112 %1 = load <4 x float>, ptr %a113 %2 = load <4 x float>, ptr %b114 %3 = fcmp ogt <4 x float> %1, %2115 %4 = sext <4 x i1> %3 to <4 x i32>116 store <4 x i32> %4, ptr %c117 ret void118}119 120define void @ogt_v2f64(ptr %c, ptr %a, ptr %b) nounwind {121; CHECK-LABEL: ogt_v2f64:122; CHECK: # %bb.0:123; CHECK-NEXT: ld.d $w0, 0($5)124; CHECK-NEXT: ld.d $w1, 0($6)125; CHECK-NEXT: fclt.d $w0, $w1, $w0126; CHECK-NEXT: jr $ra127; CHECK-NEXT: st.d $w0, 0($4)128 %1 = load <2 x double>, ptr %a129 %2 = load <2 x double>, ptr %b130 %3 = fcmp ogt <2 x double> %1, %2131 %4 = sext <2 x i1> %3 to <2 x i64>132 store <2 x i64> %4, ptr %c133 ret void134}135 136define void @ole_v4f32(ptr %c, ptr %a, ptr %b) nounwind {137; CHECK-LABEL: ole_v4f32:138; CHECK: # %bb.0:139; CHECK-NEXT: ld.w $w0, 0($6)140; CHECK-NEXT: ld.w $w1, 0($5)141; CHECK-NEXT: fcle.w $w0, $w1, $w0142; CHECK-NEXT: jr $ra143; CHECK-NEXT: st.w $w0, 0($4)144 %1 = load <4 x float>, ptr %a145 %2 = load <4 x float>, ptr %b146 %3 = fcmp ole <4 x float> %1, %2147 %4 = sext <4 x i1> %3 to <4 x i32>148 store <4 x i32> %4, ptr %c149 ret void150}151 152define void @ole_v2f64(ptr %c, ptr %a, ptr %b) nounwind {153; CHECK-LABEL: ole_v2f64:154; CHECK: # %bb.0:155; CHECK-NEXT: ld.d $w0, 0($6)156; CHECK-NEXT: ld.d $w1, 0($5)157; CHECK-NEXT: fcle.d $w0, $w1, $w0158; CHECK-NEXT: jr $ra159; CHECK-NEXT: st.d $w0, 0($4)160 %1 = load <2 x double>, ptr %a161 %2 = load <2 x double>, ptr %b162 %3 = fcmp ole <2 x double> %1, %2163 %4 = sext <2 x i1> %3 to <2 x i64>164 store <2 x i64> %4, ptr %c165 ret void166}167 168define void @olt_v4f32(ptr %c, ptr %a, ptr %b) nounwind {169; CHECK-LABEL: olt_v4f32:170; CHECK: # %bb.0:171; CHECK-NEXT: ld.w $w0, 0($6)172; CHECK-NEXT: ld.w $w1, 0($5)173; CHECK-NEXT: fclt.w $w0, $w1, $w0174; CHECK-NEXT: jr $ra175; CHECK-NEXT: st.w $w0, 0($4)176 %1 = load <4 x float>, ptr %a177 %2 = load <4 x float>, ptr %b178 %3 = fcmp olt <4 x float> %1, %2179 %4 = sext <4 x i1> %3 to <4 x i32>180 store <4 x i32> %4, ptr %c181 ret void182}183 184define void @olt_v2f64(ptr %c, ptr %a, ptr %b) nounwind {185; CHECK-LABEL: olt_v2f64:186; CHECK: # %bb.0:187; CHECK-NEXT: ld.d $w0, 0($6)188; CHECK-NEXT: ld.d $w1, 0($5)189; CHECK-NEXT: fclt.d $w0, $w1, $w0190; CHECK-NEXT: jr $ra191; CHECK-NEXT: st.d $w0, 0($4)192 %1 = load <2 x double>, ptr %a193 %2 = load <2 x double>, ptr %b194 %3 = fcmp olt <2 x double> %1, %2195 %4 = sext <2 x i1> %3 to <2 x i64>196 store <2 x i64> %4, ptr %c197 ret void198}199 200define void @one_v4f32(ptr %c, ptr %a, ptr %b) nounwind {201; CHECK-LABEL: one_v4f32:202; CHECK: # %bb.0:203; CHECK-NEXT: ld.w $w0, 0($6)204; CHECK-NEXT: ld.w $w1, 0($5)205; CHECK-NEXT: fcne.w $w0, $w1, $w0206; CHECK-NEXT: jr $ra207; CHECK-NEXT: st.w $w0, 0($4)208 %1 = load <4 x float>, ptr %a209 %2 = load <4 x float>, ptr %b210 %3 = fcmp one <4 x float> %1, %2211 %4 = sext <4 x i1> %3 to <4 x i32>212 store <4 x i32> %4, ptr %c213 ret void214}215 216define void @one_v2f64(ptr %c, ptr %a, ptr %b) nounwind {217; CHECK-LABEL: one_v2f64:218; CHECK: # %bb.0:219; CHECK-NEXT: ld.d $w0, 0($6)220; CHECK-NEXT: ld.d $w1, 0($5)221; CHECK-NEXT: fcne.d $w0, $w1, $w0222; CHECK-NEXT: jr $ra223; CHECK-NEXT: st.d $w0, 0($4)224 %1 = load <2 x double>, ptr %a225 %2 = load <2 x double>, ptr %b226 %3 = fcmp one <2 x double> %1, %2227 %4 = sext <2 x i1> %3 to <2 x i64>228 store <2 x i64> %4, ptr %c229 ret void230}231 232define void @ord_v4f32(ptr %c, ptr %a, ptr %b) nounwind {233; CHECK-LABEL: ord_v4f32:234; CHECK: # %bb.0:235; CHECK-NEXT: ld.w $w0, 0($6)236; CHECK-NEXT: ld.w $w1, 0($5)237; CHECK-NEXT: fcor.w $w0, $w1, $w0238; CHECK-NEXT: jr $ra239; CHECK-NEXT: st.w $w0, 0($4)240 %1 = load <4 x float>, ptr %a241 %2 = load <4 x float>, ptr %b242 %3 = fcmp ord <4 x float> %1, %2243 %4 = sext <4 x i1> %3 to <4 x i32>244 store <4 x i32> %4, ptr %c245 ret void246}247 248define void @ord_v2f64(ptr %c, ptr %a, ptr %b) nounwind {249; CHECK-LABEL: ord_v2f64:250; CHECK: # %bb.0:251; CHECK-NEXT: ld.d $w0, 0($6)252; CHECK-NEXT: ld.d $w1, 0($5)253; CHECK-NEXT: fcor.d $w0, $w1, $w0254; CHECK-NEXT: jr $ra255; CHECK-NEXT: st.d $w0, 0($4)256 %1 = load <2 x double>, ptr %a257 %2 = load <2 x double>, ptr %b258 %3 = fcmp ord <2 x double> %1, %2259 %4 = sext <2 x i1> %3 to <2 x i64>260 store <2 x i64> %4, ptr %c261 ret void262}263 264define void @ueq_v4f32(ptr %c, ptr %a, ptr %b) nounwind {265; CHECK-LABEL: ueq_v4f32:266; CHECK: # %bb.0:267; CHECK-NEXT: ld.w $w0, 0($6)268; CHECK-NEXT: ld.w $w1, 0($5)269; CHECK-NEXT: fcueq.w $w0, $w1, $w0270; CHECK-NEXT: jr $ra271; CHECK-NEXT: st.w $w0, 0($4)272 %1 = load <4 x float>, ptr %a273 %2 = load <4 x float>, ptr %b274 %3 = fcmp ueq <4 x float> %1, %2275 %4 = sext <4 x i1> %3 to <4 x i32>276 store <4 x i32> %4, ptr %c277 ret void278}279 280define void @ueq_v2f64(ptr %c, ptr %a, ptr %b) nounwind {281; CHECK-LABEL: ueq_v2f64:282; CHECK: # %bb.0:283; CHECK-NEXT: ld.d $w0, 0($6)284; CHECK-NEXT: ld.d $w1, 0($5)285; CHECK-NEXT: fcueq.d $w0, $w1, $w0286; CHECK-NEXT: jr $ra287; CHECK-NEXT: st.d $w0, 0($4)288 %1 = load <2 x double>, ptr %a289 %2 = load <2 x double>, ptr %b290 %3 = fcmp ueq <2 x double> %1, %2291 %4 = sext <2 x i1> %3 to <2 x i64>292 store <2 x i64> %4, ptr %c293 ret void294}295 296define void @uge_v4f32(ptr %c, ptr %a, ptr %b) nounwind {297; CHECK-LABEL: uge_v4f32:298; CHECK: # %bb.0:299; CHECK-NEXT: ld.w $w0, 0($5)300; CHECK-NEXT: ld.w $w1, 0($6)301; CHECK-NEXT: fcule.w $w0, $w1, $w0302; CHECK-NEXT: jr $ra303; CHECK-NEXT: st.w $w0, 0($4)304 %1 = load <4 x float>, ptr %a305 %2 = load <4 x float>, ptr %b306 %3 = fcmp uge <4 x float> %1, %2307 %4 = sext <4 x i1> %3 to <4 x i32>308 store <4 x i32> %4, ptr %c309 ret void310}311 312define void @uge_v2f64(ptr %c, ptr %a, ptr %b) nounwind {313; CHECK-LABEL: uge_v2f64:314; CHECK: # %bb.0:315; CHECK-NEXT: ld.d $w0, 0($5)316; CHECK-NEXT: ld.d $w1, 0($6)317; CHECK-NEXT: fcule.d $w0, $w1, $w0318; CHECK-NEXT: jr $ra319; CHECK-NEXT: st.d $w0, 0($4)320 %1 = load <2 x double>, ptr %a321 %2 = load <2 x double>, ptr %b322 %3 = fcmp uge <2 x double> %1, %2323 %4 = sext <2 x i1> %3 to <2 x i64>324 store <2 x i64> %4, ptr %c325 ret void326}327 328define void @ugt_v4f32(ptr %c, ptr %a, ptr %b) nounwind {329; CHECK-LABEL: ugt_v4f32:330; CHECK: # %bb.0:331; CHECK-NEXT: ld.w $w0, 0($5)332; CHECK-NEXT: ld.w $w1, 0($6)333; CHECK-NEXT: fcult.w $w0, $w1, $w0334; CHECK-NEXT: jr $ra335; CHECK-NEXT: st.w $w0, 0($4)336 %1 = load <4 x float>, ptr %a337 %2 = load <4 x float>, ptr %b338 %3 = fcmp ugt <4 x float> %1, %2339 %4 = sext <4 x i1> %3 to <4 x i32>340 store <4 x i32> %4, ptr %c341 ret void342}343 344define void @ugt_v2f64(ptr %c, ptr %a, ptr %b) nounwind {345; CHECK-LABEL: ugt_v2f64:346; CHECK: # %bb.0:347; CHECK-NEXT: ld.d $w0, 0($5)348; CHECK-NEXT: ld.d $w1, 0($6)349; CHECK-NEXT: fcult.d $w0, $w1, $w0350; CHECK-NEXT: jr $ra351; CHECK-NEXT: st.d $w0, 0($4)352 %1 = load <2 x double>, ptr %a353 %2 = load <2 x double>, ptr %b354 %3 = fcmp ugt <2 x double> %1, %2355 %4 = sext <2 x i1> %3 to <2 x i64>356 store <2 x i64> %4, ptr %c357 ret void358}359 360define void @ule_v4f32(ptr %c, ptr %a, ptr %b) nounwind {361; CHECK-LABEL: ule_v4f32:362; CHECK: # %bb.0:363; CHECK-NEXT: ld.w $w0, 0($6)364; CHECK-NEXT: ld.w $w1, 0($5)365; CHECK-NEXT: fcule.w $w0, $w1, $w0366; CHECK-NEXT: jr $ra367; CHECK-NEXT: st.w $w0, 0($4)368 %1 = load <4 x float>, ptr %a369 %2 = load <4 x float>, ptr %b370 %3 = fcmp ule <4 x float> %1, %2371 %4 = sext <4 x i1> %3 to <4 x i32>372 store <4 x i32> %4, ptr %c373 ret void374}375 376define void @ule_v2f64(ptr %c, ptr %a, ptr %b) nounwind {377; CHECK-LABEL: ule_v2f64:378; CHECK: # %bb.0:379; CHECK-NEXT: ld.d $w0, 0($6)380; CHECK-NEXT: ld.d $w1, 0($5)381; CHECK-NEXT: fcule.d $w0, $w1, $w0382; CHECK-NEXT: jr $ra383; CHECK-NEXT: st.d $w0, 0($4)384 %1 = load <2 x double>, ptr %a385 %2 = load <2 x double>, ptr %b386 %3 = fcmp ule <2 x double> %1, %2387 %4 = sext <2 x i1> %3 to <2 x i64>388 store <2 x i64> %4, ptr %c389 ret void390}391 392define void @ult_v4f32(ptr %c, ptr %a, ptr %b) nounwind {393; CHECK-LABEL: ult_v4f32:394; CHECK: # %bb.0:395; CHECK-NEXT: ld.w $w0, 0($6)396; CHECK-NEXT: ld.w $w1, 0($5)397; CHECK-NEXT: fcult.w $w0, $w1, $w0398; CHECK-NEXT: jr $ra399; CHECK-NEXT: st.w $w0, 0($4)400 %1 = load <4 x float>, ptr %a401 %2 = load <4 x float>, ptr %b402 %3 = fcmp ult <4 x float> %1, %2403 %4 = sext <4 x i1> %3 to <4 x i32>404 store <4 x i32> %4, ptr %c405 ret void406}407 408define void @ult_v2f64(ptr %c, ptr %a, ptr %b) nounwind {409; CHECK-LABEL: ult_v2f64:410; CHECK: # %bb.0:411; CHECK-NEXT: ld.d $w0, 0($6)412; CHECK-NEXT: ld.d $w1, 0($5)413; CHECK-NEXT: fcult.d $w0, $w1, $w0414; CHECK-NEXT: jr $ra415; CHECK-NEXT: st.d $w0, 0($4)416 %1 = load <2 x double>, ptr %a417 %2 = load <2 x double>, ptr %b418 %3 = fcmp ult <2 x double> %1, %2419 %4 = sext <2 x i1> %3 to <2 x i64>420 store <2 x i64> %4, ptr %c421 ret void422}423 424define void @uno_v4f32(ptr %c, ptr %a, ptr %b) nounwind {425; CHECK-LABEL: uno_v4f32:426; CHECK: # %bb.0:427; CHECK-NEXT: ld.w $w0, 0($6)428; CHECK-NEXT: ld.w $w1, 0($5)429; CHECK-NEXT: fcun.w $w0, $w1, $w0430; CHECK-NEXT: jr $ra431; CHECK-NEXT: st.w $w0, 0($4)432 %1 = load <4 x float>, ptr %a433 %2 = load <4 x float>, ptr %b434 %3 = fcmp uno <4 x float> %1, %2435 %4 = sext <4 x i1> %3 to <4 x i32>436 store <4 x i32> %4, ptr %c437 ret void438}439 440define void @uno_v2f64(ptr %c, ptr %a, ptr %b) nounwind {441; CHECK-LABEL: uno_v2f64:442; CHECK: # %bb.0:443; CHECK-NEXT: ld.d $w0, 0($6)444; CHECK-NEXT: ld.d $w1, 0($5)445; CHECK-NEXT: fcun.d $w0, $w1, $w0446; CHECK-NEXT: jr $ra447; CHECK-NEXT: st.d $w0, 0($4)448 %1 = load <2 x double>, ptr %a449 %2 = load <2 x double>, ptr %b450 %3 = fcmp uno <2 x double> %1, %2451 %4 = sext <2 x i1> %3 to <2 x i64>452 store <2 x i64> %4, ptr %c453 ret void454}455 456; (setcc $a, $b, SETTRUE) is always folded, so we won't get fcaf457define void @true_v4f32(ptr %c, ptr %a, ptr %b) nounwind {458; CHECK-LABEL: true_v4f32:459; CHECK: # %bb.0:460; CHECK-NEXT: ldi.b $w0, -1461; CHECK-NEXT: jr $ra462; CHECK-NEXT: st.w $w0, 0($4)463 %1 = load <4 x float>, ptr %a464 %2 = load <4 x float>, ptr %b465 %3 = fcmp true <4 x float> %1, %2466 %4 = sext <4 x i1> %3 to <4 x i32>467 store <4 x i32> %4, ptr %c468 ret void469}470 471; (setcc $a, $b, SETTRUE) is always folded.472define void @true_v2f64(ptr %c, ptr %a, ptr %b) nounwind {473; CHECK-LABEL: true_v2f64:474; CHECK: # %bb.0:475; CHECK-NEXT: ldi.b $w0, -1476; CHECK-NEXT: jr $ra477; CHECK-NEXT: st.w $w0, 0($4)478 %1 = load <2 x double>, ptr %a479 %2 = load <2 x double>, ptr %b480 %3 = fcmp true <2 x double> %1, %2481 %4 = sext <2 x i1> %3 to <2 x i64>482 store <2 x i64> %4, ptr %c483 ret void484}485 486; Note that IfSet and IfClr are swapped since the condition is inverted487define void @bsel_v4f32(ptr %d, ptr %a, ptr %b, ptr %c) nounwind {488; CHECK-LABEL: bsel_v4f32:489; CHECK: # %bb.0:490; CHECK-NEXT: ld.w $w0, 0($5)491; CHECK-NEXT: ld.w $w1, 0($6)492; CHECK-NEXT: fclt.w $w1, $w1, $w0493; CHECK-NEXT: ld.w $w2, 0($7)494; CHECK-NEXT: bsel.v $w1, $w2, $w0495; CHECK-NEXT: jr $ra496; CHECK-NEXT: st.w $w1, 0($4)497 %1 = load <4 x float>, ptr %a498 %2 = load <4 x float>, ptr %b499 %3 = load <4 x float>, ptr %c500 %4 = fcmp ogt <4 x float> %1, %2501 %5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %3502 store <4 x float> %5, ptr %d503 ret void504}505 506; Note that IfSet and IfClr are swapped since the condition is inverted507define void @bsel_v2f64(ptr %d, ptr %a, ptr %b, ptr %c) nounwind {508; CHECK-LABEL: bsel_v2f64:509; CHECK: # %bb.0:510; CHECK-NEXT: ld.d $w0, 0($5)511; CHECK-NEXT: ld.d $w1, 0($6)512; CHECK-NEXT: fclt.d $w1, $w1, $w0513; CHECK-NEXT: ld.d $w2, 0($7)514; CHECK-NEXT: bsel.v $w1, $w2, $w0515; CHECK-NEXT: jr $ra516; CHECK-NEXT: st.d $w1, 0($4)517 %1 = load <2 x double>, ptr %a518 %2 = load <2 x double>, ptr %b519 %3 = load <2 x double>, ptr %c520 %4 = fcmp ogt <2 x double> %1, %2521 %5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %3522 store <2 x double> %5, ptr %d523 ret void524}525 526; Note that IfSet and IfClr are swapped since the condition is inverted527define void @bseli_v4f32(ptr %d, ptr %a, ptr %b, ptr %c) nounwind {528; CHECK-LABEL: bseli_v4f32:529; CHECK: # %bb.0:530; CHECK-NEXT: ld.w $w0, 0($5)531; CHECK-NEXT: ld.w $w1, 0($6)532; CHECK-NEXT: fclt.w $w1, $w1, $w0533; CHECK-NEXT: and.v $w0, $w1, $w0534; CHECK-NEXT: jr $ra535; CHECK-NEXT: st.w $w0, 0($4)536 %1 = load <4 x float>, ptr %a537 %2 = load <4 x float>, ptr %b538 %3 = fcmp ogt <4 x float> %1, %2539 %4 = select <4 x i1> %3, <4 x float> %1, <4 x float> zeroinitializer540 store <4 x float> %4, ptr %d541 ret void542}543 544; Note that IfSet and IfClr are swapped since the condition is inverted545define void @bseli_v2f64(ptr %d, ptr %a, ptr %b, ptr %c) nounwind {546; CHECK-LABEL: bseli_v2f64:547; CHECK: # %bb.0:548; CHECK-NEXT: ld.d $w0, 0($5)549; CHECK-NEXT: ld.d $w1, 0($6)550; CHECK-NEXT: fclt.d $w1, $w1, $w0551; CHECK-NEXT: and.v $w0, $w1, $w0552; CHECK-NEXT: jr $ra553; CHECK-NEXT: st.d $w0, 0($4)554 %1 = load <2 x double>, ptr %a555 %2 = load <2 x double>, ptr %b556 %3 = fcmp ogt <2 x double> %1, %2557 %4 = select <2 x i1> %3, <2 x double> %1, <2 x double> zeroinitializer558 store <2 x double> %4, ptr %d559 ret void560}561 562define void @max_v4f32(ptr %c, ptr %a, ptr %b) nounwind {563; CHECK-LABEL: max_v4f32:564; CHECK: # %bb.0:565; CHECK-NEXT: ld.w $w0, 0($6)566; CHECK-NEXT: ld.w $w1, 0($5)567; CHECK-NEXT: fmax.w $w0, $w1, $w0568; CHECK-NEXT: jr $ra569; CHECK-NEXT: st.w $w0, 0($4)570 %1 = load <4 x float>, ptr %a571 %2 = load <4 x float>, ptr %b572 %3 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %1, <4 x float> %2)573 store <4 x float> %3, ptr %c574 ret void575}576 577define void @max_v2f64(ptr %c, ptr %a, ptr %b) nounwind {578; CHECK-LABEL: max_v2f64:579; CHECK: # %bb.0:580; CHECK-NEXT: ld.d $w0, 0($6)581; CHECK-NEXT: ld.d $w1, 0($5)582; CHECK-NEXT: fmax.d $w0, $w1, $w0583; CHECK-NEXT: jr $ra584; CHECK-NEXT: st.d $w0, 0($4)585 %1 = load <2 x double>, ptr %a586 %2 = load <2 x double>, ptr %b587 %3 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %1, <2 x double> %2)588 store <2 x double> %3, ptr %c589 ret void590}591 592define void @min_v4f32(ptr %c, ptr %a, ptr %b) nounwind {593; CHECK-LABEL: min_v4f32:594; CHECK: # %bb.0:595; CHECK-NEXT: ld.w $w0, 0($6)596; CHECK-NEXT: ld.w $w1, 0($5)597; CHECK-NEXT: fmin.w $w0, $w1, $w0598; CHECK-NEXT: jr $ra599; CHECK-NEXT: st.w $w0, 0($4)600 %1 = load <4 x float>, ptr %a601 %2 = load <4 x float>, ptr %b602 %3 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %1, <4 x float> %2)603 store <4 x float> %3, ptr %c604 ret void605}606 607define void @min_v2f64(ptr %c, ptr %a, ptr %b) nounwind {608; CHECK-LABEL: min_v2f64:609; CHECK: # %bb.0:610; CHECK-NEXT: ld.d $w0, 0($6)611; CHECK-NEXT: ld.d $w1, 0($5)612; CHECK-NEXT: fmin.d $w0, $w1, $w0613; CHECK-NEXT: jr $ra614; CHECK-NEXT: st.d $w0, 0($4)615 %1 = load <2 x double>, ptr %a616 %2 = load <2 x double>, ptr %b617 %3 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %1, <2 x double> %2)618 store <2 x double> %3, ptr %c619 ret void620}621