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1; Test the MSA intrinsics that are encoded with the ELM instruction format and2; are element extraction operations.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \5; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS326; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \7; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS328; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \9; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6410; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \11; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6412 13@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1614@llvm_mips_copy_s_b_RES = global i32 0, align 1615 16define void @llvm_mips_copy_s_b_test() nounwind {17entry:18 %0 = load <16 x i8>, ptr @llvm_mips_copy_s_b_ARG119 %1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1)20 store i32 %1, ptr @llvm_mips_copy_s_b_RES21 ret void22}23 24declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind25 26; MIPS-ANY: llvm_mips_copy_s_b_test:27; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1)28; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_ARG1)29; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])30; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1]31; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)32; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES)33; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])34; MIPS-ANY: .size llvm_mips_copy_s_b_test35;36@llvm_mips_copy_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1637@llvm_mips_copy_s_h_RES = global i32 0, align 1638 39define void @llvm_mips_copy_s_h_test() nounwind {40entry:41 %0 = load <8 x i16>, ptr @llvm_mips_copy_s_h_ARG142 %1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1)43 store i32 %1, ptr @llvm_mips_copy_s_h_RES44 ret void45}46 47declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind48 49; MIPS-ANY: llvm_mips_copy_s_h_test:50; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1)51; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_ARG1)52; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])53; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1]54; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)55; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES)56; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])57; MIPS-ANY: .size llvm_mips_copy_s_h_test58;59@llvm_mips_copy_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1660@llvm_mips_copy_s_w_RES = global i32 0, align 1661 62define void @llvm_mips_copy_s_w_test() nounwind {63entry:64 %0 = load <4 x i32>, ptr @llvm_mips_copy_s_w_ARG165 %1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1)66 store i32 %1, ptr @llvm_mips_copy_s_w_RES67 ret void68}69 70declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind71 72; MIPS-ANY: llvm_mips_copy_s_w_test:73; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1)74; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_ARG1)75; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])76; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]77; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)78; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES)79; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])80; MIPS-ANY: .size llvm_mips_copy_s_w_test81;82@llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1683@llvm_mips_copy_s_d_RES = global i64 0, align 1684 85define void @llvm_mips_copy_s_d_test() nounwind {86entry:87 %0 = load <2 x i64>, ptr @llvm_mips_copy_s_d_ARG188 %1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1)89 store i64 %1, ptr @llvm_mips_copy_s_d_RES90 ret void91}92 93declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind94 95; MIPS-ANY: llvm_mips_copy_s_d_test:96; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1)97; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_ARG1)98; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])99; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])100; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]101; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]102; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]103; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)104; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_RES)105; MIPS32-DAG: sw [[RD1]], 0([[RES]])106; MIPS32-DAG: sw [[RD2]], 4([[RES]])107; MIPS64-DAG: sd [[RD]], 0([[RES]])108; MIPS-ANY: .size llvm_mips_copy_s_d_test109;110@llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16111@llvm_mips_copy_u_b_RES = global i32 0, align 16112 113define void @llvm_mips_copy_u_b_test() nounwind {114entry:115 %0 = load <16 x i8>, ptr @llvm_mips_copy_u_b_ARG1116 %1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1)117 store i32 %1, ptr @llvm_mips_copy_u_b_RES118 ret void119}120 121declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind122 123; MIPS-ANY: llvm_mips_copy_u_b_test:124; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1)125; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_ARG1)126; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])127; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1]128; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES)129; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_RES)130; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])131; MIPS-ANY: .size llvm_mips_copy_u_b_test132;133@llvm_mips_copy_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16134@llvm_mips_copy_u_h_RES = global i32 0, align 16135 136define void @llvm_mips_copy_u_h_test() nounwind {137entry:138 %0 = load <8 x i16>, ptr @llvm_mips_copy_u_h_ARG1139 %1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1)140 store i32 %1, ptr @llvm_mips_copy_u_h_RES141 ret void142}143 144declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind145 146; MIPS-ANY: llvm_mips_copy_u_h_test:147; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1)148; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_ARG1)149; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])150; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1]151; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES)152; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_RES)153; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])154; MIPS-ANY: .size llvm_mips_copy_u_h_test155;156@llvm_mips_copy_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16157@llvm_mips_copy_u_w_RES = global i32 0, align 16158 159define void @llvm_mips_copy_u_w_test() nounwind {160entry:161 %0 = load <4 x i32>, ptr @llvm_mips_copy_u_w_ARG1162 %1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1)163 store i32 %1, ptr @llvm_mips_copy_u_w_RES164 ret void165}166 167declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind168 169; MIPS-ANY: llvm_mips_copy_u_w_test:170; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)171; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1)172; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])173; MIPS32-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]174; MIPS64-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]175; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)176; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES)177; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])178; MIPS-ANY: .size llvm_mips_copy_u_w_test179;180@llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16181@llvm_mips_copy_u_d_RES = global i64 0, align 16182 183define void @llvm_mips_copy_u_d_test() nounwind {184entry:185 %0 = load <2 x i64>, ptr @llvm_mips_copy_u_d_ARG1186 %1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1)187 store i64 %1, ptr @llvm_mips_copy_u_d_RES188 ret void189}190 191declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind192 193; MIPS-ANY: llvm_mips_copy_u_d_test:194; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1)195; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_ARG1)196; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])197; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])198; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]199; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]200; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]201; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)202; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES)203; MIPS32-DAG: sw [[RD1]], 0([[RES]])204; MIPS32-DAG: sw [[RD2]], 4([[RES]])205; MIPS64-DAG: sd [[RD]], 0([[RES]])206; MIPS-ANY: .size llvm_mips_copy_u_d_test207;208