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1; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM2; instruction format).3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s6 7define i32 @msa_ir_cfcmsa_test() nounwind {8entry:9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)10 ret i32 %011}12 13; CHECK: msa_ir_cfcmsa_test:14; CHECK: cfcmsa $[[R1:[0-9]+]], $015; CHECK: .size msa_ir_cfcmsa_test16;17define i32 @msa_csr_cfcmsa_test() nounwind {18entry:19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)20 ret i32 %021}22 23; CHECK: msa_csr_cfcmsa_test:24; CHECK: cfcmsa $[[R1:[0-9]+]], $125; CHECK: .size msa_csr_cfcmsa_test26;27define i32 @msa_access_cfcmsa_test() nounwind {28entry:29 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2)30 ret i32 %031}32 33; CHECK: msa_access_cfcmsa_test:34; CHECK: cfcmsa $[[R1:[0-9]+]], $235; CHECK: .size msa_access_cfcmsa_test36;37define i32 @msa_save_cfcmsa_test() nounwind {38entry:39 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3)40 ret i32 %041}42 43; CHECK: msa_save_cfcmsa_test:44; CHECK: cfcmsa $[[R1:[0-9]+]], $345; CHECK: .size msa_save_cfcmsa_test46;47define i32 @msa_modify_cfcmsa_test() nounwind {48entry:49 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4)50 ret i32 %051}52 53; CHECK: msa_modify_cfcmsa_test:54; CHECK: cfcmsa $[[R1:[0-9]+]], $455; CHECK: .size msa_modify_cfcmsa_test56;57define i32 @msa_request_cfcmsa_test() nounwind {58entry:59 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5)60 ret i32 %061}62 63; CHECK: msa_request_cfcmsa_test:64; CHECK: cfcmsa $[[R1:[0-9]+]], $565; CHECK: .size msa_request_cfcmsa_test66;67define i32 @msa_map_cfcmsa_test() nounwind {68entry:69 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6)70 ret i32 %071}72 73; CHECK: msa_map_cfcmsa_test:74; CHECK: cfcmsa $[[R1:[0-9]+]], $675; CHECK: .size msa_map_cfcmsa_test76;77define i32 @msa_unmap_cfcmsa_test() nounwind {78entry:79 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)80 ret i32 %081}82 83; CHECK: msa_unmap_cfcmsa_test:84; CHECK: cfcmsa $[[R1:[0-9]+]], $785; CHECK: .size msa_unmap_cfcmsa_test86;87define i32 @msa_invalid_reg_cfcmsa_test() nounwind {88entry:89 %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)90 ret i32 %091}92 93; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:94; CHECK: cfcmsa ${{[0-9]+}}, $895;96define void @msa_ir_ctcmsa_test() nounwind {97entry:98 tail call void @llvm.mips.ctcmsa(i32 0, i32 1)99 ret void100}101 102; CHECK: msa_ir_ctcmsa_test:103; CHECK: ctcmsa $0104; CHECK: .size msa_ir_ctcmsa_test105;106define void @msa_csr_ctcmsa_test() nounwind {107entry:108 tail call void @llvm.mips.ctcmsa(i32 1, i32 1)109 ret void110}111 112; CHECK: msa_csr_ctcmsa_test:113; CHECK: ctcmsa $1114; CHECK: .size msa_csr_ctcmsa_test115;116define void @msa_access_ctcmsa_test() nounwind {117entry:118 tail call void @llvm.mips.ctcmsa(i32 2, i32 1)119 ret void120}121 122; CHECK: msa_access_ctcmsa_test:123; CHECK: ctcmsa $2124; CHECK: .size msa_access_ctcmsa_test125;126define void @msa_save_ctcmsa_test() nounwind {127entry:128 tail call void @llvm.mips.ctcmsa(i32 3, i32 1)129 ret void130}131 132; CHECK: msa_save_ctcmsa_test:133; CHECK: ctcmsa $3134; CHECK: .size msa_save_ctcmsa_test135;136define void @msa_modify_ctcmsa_test() nounwind {137entry:138 tail call void @llvm.mips.ctcmsa(i32 4, i32 1)139 ret void140}141 142; CHECK: msa_modify_ctcmsa_test:143; CHECK: ctcmsa $4144; CHECK: .size msa_modify_ctcmsa_test145;146define void @msa_request_ctcmsa_test() nounwind {147entry:148 tail call void @llvm.mips.ctcmsa(i32 5, i32 1)149 ret void150}151 152; CHECK: msa_request_ctcmsa_test:153; CHECK: ctcmsa $5154; CHECK: .size msa_request_ctcmsa_test155;156define void @msa_map_ctcmsa_test() nounwind {157entry:158 tail call void @llvm.mips.ctcmsa(i32 6, i32 1)159 ret void160}161 162; CHECK: msa_map_ctcmsa_test:163; CHECK: ctcmsa $6164; CHECK: .size msa_map_ctcmsa_test165;166define void @msa_unmap_ctcmsa_test() nounwind {167entry:168 tail call void @llvm.mips.ctcmsa(i32 7, i32 1)169 ret void170}171 172; CHECK: msa_unmap_ctcmsa_test:173; CHECK: ctcmsa $7174; CHECK: .size msa_unmap_ctcmsa_test175;176define void @msa_invalid_reg_ctcmsa_test() nounwind {177entry:178 tail call void @llvm.mips.ctcmsa(i32 8, i32 1)179 ret void180}181 182; CHECK: msa_invalid_reg_ctcmsa_test:183; CHECK: ctcmsa $8184;185declare i32 @llvm.mips.cfcmsa(i32) nounwind186declare void @llvm.mips.ctcmsa(i32, i32) nounwind187