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1; Test the MSA element insertion intrinsics that are encoded with the ELM2; instruction format.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \5; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS326; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \7; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS328; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \9; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6410; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \11; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6412 13@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1614@llvm_mips_insert_b_ARG3 = global i32 27, align 1615@llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1616 17define void @llvm_mips_insert_b_test() nounwind {18entry:19 %0 = load <16 x i8>, ptr @llvm_mips_insert_b_ARG120 %1 = load i32, ptr @llvm_mips_insert_b_ARG321 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1)22 store <16 x i8> %2, ptr @llvm_mips_insert_b_RES23 ret void24}25 26declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind27 28; MIPS-ANY: llvm_mips_insert_b_test:29; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(30; MIPS-ANY-DAG: ld.b [[R2:\$w[0-9]+]], 0(31; MIPS-ANY-DAG: insert.b [[R2]][1], [[R1]]32; MIPS-ANY-DAG: st.b [[R2]], 0(33; MIPS-ANY: .size llvm_mips_insert_b_test34;35@llvm_mips_insert_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1636@llvm_mips_insert_h_ARG3 = global i32 27, align 1637@llvm_mips_insert_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1638 39define void @llvm_mips_insert_h_test() nounwind {40entry:41 %0 = load <8 x i16>, ptr @llvm_mips_insert_h_ARG142 %1 = load i32, ptr @llvm_mips_insert_h_ARG343 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1)44 store <8 x i16> %2, ptr @llvm_mips_insert_h_RES45 ret void46}47 48declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind49 50; MIPS-ANY: llvm_mips_insert_h_test:51; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(52; MIPS-ANY-DAG: ld.h [[R2:\$w[0-9]+]], 0(53; MIPS-ANY-DAG: insert.h [[R2]][1], [[R1]]54; MIPS-ANY-DAG: st.h [[R2]], 0(55; MIPS-ANY: .size llvm_mips_insert_h_test56;57@llvm_mips_insert_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1658@llvm_mips_insert_w_ARG3 = global i32 27, align 1659@llvm_mips_insert_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1660 61define void @llvm_mips_insert_w_test() nounwind {62entry:63 %0 = load <4 x i32>, ptr @llvm_mips_insert_w_ARG164 %1 = load i32, ptr @llvm_mips_insert_w_ARG365 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1)66 store <4 x i32> %2, ptr @llvm_mips_insert_w_RES67 ret void68}69 70declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind71 72; MIPS-ANY: llvm_mips_insert_w_test:73; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(74; MIPS-ANY-DAG: ld.w [[R2:\$w[0-9]+]], 0(75; MIPS-ANY-DAG: insert.w [[R2]][1], [[R1]]76; MIPS-ANY-DAG: st.w [[R2]], 0(77; MIPS-ANY: .size llvm_mips_insert_w_test78;79@llvm_mips_insert_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1680@llvm_mips_insert_d_ARG3 = global i64 27, align 1681@llvm_mips_insert_d_RES = global <2 x i64> <i64 0, i64 0>, align 1682 83define void @llvm_mips_insert_d_test() nounwind {84entry:85 %0 = load <2 x i64>, ptr @llvm_mips_insert_d_ARG186 %1 = load i64, ptr @llvm_mips_insert_d_ARG387 %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1)88 store <2 x i64> %2, ptr @llvm_mips_insert_d_RES89 ret void90}91 92declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind93 94; MIPS-ANY: llvm_mips_insert_d_test:95; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(96; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(97; MIPS64-DAG: ld [[R1:\$[0-9]+]], 0(98; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]],99; MIPS64-DAG: ld.d [[W1:\$w[0-9]+]],100; MIPS32-DAG: insert.w [[R3]][2], [[R1]]101; MIPS32-DAG: insert.w [[R3]][3], [[R2]]102; MIPS64-DAG: insert.d [[W1]][1], [[R1]]103; MIPS32-DAG: st.w [[R3]],104; MIPS64-DAG: st.d [[W1]],105; MIPS-ANY: .size llvm_mips_insert_d_test106;107@llvm_mips_insve_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16108@llvm_mips_insve_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16109@llvm_mips_insve_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16110 111define void @llvm_mips_insve_b_test() nounwind {112entry:113 %0 = load <16 x i8>, ptr @llvm_mips_insve_b_ARG1114 %1 = load <16 x i8>, ptr @llvm_mips_insve_b_ARG3115 %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1)116 store <16 x i8> %2, ptr @llvm_mips_insve_b_RES117 ret void118}119 120declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind121 122; MIPS-ANY: llvm_mips_insve_b_test:123; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)(124; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)(125; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG1)(126; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG3)(127; MIPS-ANY-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])128; MIPS-ANY-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])129; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0]130; MIPS-ANY-DAG: st.b [[R3]],131; MIPS-ANY: .size llvm_mips_insve_b_test132;133@llvm_mips_insve_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16134@llvm_mips_insve_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16135@llvm_mips_insve_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16136 137define void @llvm_mips_insve_h_test() nounwind {138entry:139 %0 = load <8 x i16>, ptr @llvm_mips_insve_h_ARG1140 %1 = load <8 x i16>, ptr @llvm_mips_insve_h_ARG3141 %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1)142 store <8 x i16> %2, ptr @llvm_mips_insve_h_RES143 ret void144}145 146declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind147 148; MIPS-ANY: llvm_mips_insve_h_test:149; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)(150; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)(151; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG1)(152; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG3)(153; MIPS-ANY-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])154; MIPS-ANY-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])155; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0]156; MIPS-ANY-DAG: st.h [[R3]],157; MIPS-ANY: .size llvm_mips_insve_h_test158;159@llvm_mips_insve_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16160@llvm_mips_insve_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16161@llvm_mips_insve_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16162 163define void @llvm_mips_insve_w_test() nounwind {164entry:165 %0 = load <4 x i32>, ptr @llvm_mips_insve_w_ARG1166 %1 = load <4 x i32>, ptr @llvm_mips_insve_w_ARG3167 %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1)168 store <4 x i32> %2, ptr @llvm_mips_insve_w_RES169 ret void170}171 172declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind173 174; MIPS-ANY: llvm_mips_insve_w_test:175; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)(176; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)(177; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG1)(178; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG3)(179; MIPS-ANY-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])180; MIPS-ANY-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])181; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0]182; MIPS-ANY-DAG: st.w [[R3]],183; MIPS-ANY: .size llvm_mips_insve_w_test184;185@llvm_mips_insve_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16186@llvm_mips_insve_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16187@llvm_mips_insve_d_RES = global <2 x i64> <i64 0, i64 0>, align 16188 189define void @llvm_mips_insve_d_test() nounwind {190entry:191 %0 = load <2 x i64>, ptr @llvm_mips_insve_d_ARG1192 %1 = load <2 x i64>, ptr @llvm_mips_insve_d_ARG3193 %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1)194 store <2 x i64> %2, ptr @llvm_mips_insve_d_RES195 ret void196}197 198declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind199 200; MIPS-ANY: llvm_mips_insve_d_test:201; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)(202; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)(203; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG1)(204; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG3)(205; MIPS-ANY-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])206; MIPS-ANY-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])207; MIPS-ANY-DAG: insve.d [[R3]][1], [[R4]][0]208; MIPS-ANY-DAG: st.d [[R3]],209; MIPS-ANY: .size llvm_mips_insve_d_test210;211