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1; Test the MSA intrinsics that are encoded with the ELM instruction format and2; are either shifts or slides.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 169@llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_sldi_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_sldi_b_ARG114 %1 = load <16 x i8>, ptr @llvm_mips_sldi_b_ARG215 %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)16 store <16 x i8> %2, ptr @llvm_mips_sldi_b_RES17 ret void18}19 20declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind21 22; CHECK: llvm_mips_sldi_b_test:23; CHECK: ld.b24; CHECK: sldi.b25; CHECK: st.b26; CHECK: .size llvm_mips_sldi_b_test27;28@llvm_mips_sldi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1629@llvm_mips_sldi_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1630@llvm_mips_sldi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1631 32define void @llvm_mips_sldi_h_test() nounwind {33entry:34 %0 = load <8 x i16>, ptr @llvm_mips_sldi_h_ARG135 %1 = load <8 x i16>, ptr @llvm_mips_sldi_h_ARG236 %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)37 store <8 x i16> %2, ptr @llvm_mips_sldi_h_RES38 ret void39}40 41declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind42 43; CHECK: llvm_mips_sldi_h_test:44; CHECK: ld.h45; CHECK: sldi.h46; CHECK: st.h47; CHECK: .size llvm_mips_sldi_h_test48;49@llvm_mips_sldi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1650@llvm_mips_sldi_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1651@llvm_mips_sldi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1652 53define void @llvm_mips_sldi_w_test() nounwind {54entry:55 %0 = load <4 x i32>, ptr @llvm_mips_sldi_w_ARG156 %1 = load <4 x i32>, ptr @llvm_mips_sldi_w_ARG257 %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)58 store <4 x i32> %2, ptr @llvm_mips_sldi_w_RES59 ret void60}61 62declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind63 64; CHECK: llvm_mips_sldi_w_test:65; CHECK: ld.w66; CHECK: sldi.w67; CHECK: st.w68; CHECK: .size llvm_mips_sldi_w_test69;70@llvm_mips_sldi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1671@llvm_mips_sldi_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 1672@llvm_mips_sldi_d_RES = global <2 x i64> <i64 0, i64 0>, align 1673 74define void @llvm_mips_sldi_d_test() nounwind {75entry:76 %0 = load <2 x i64>, ptr @llvm_mips_sldi_d_ARG177 %1 = load <2 x i64>, ptr @llvm_mips_sldi_d_ARG278 %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)79 store <2 x i64> %2, ptr @llvm_mips_sldi_d_RES80 ret void81}82 83declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind84 85; CHECK: llvm_mips_sldi_d_test:86; CHECK: ld.d87; CHECK: sldi.d88; CHECK: st.d89; CHECK: .size llvm_mips_sldi_d_test90;91@llvm_mips_splati_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1692@llvm_mips_splati_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1693 94define void @llvm_mips_splati_b_test() nounwind {95entry:96 %0 = load <16 x i8>, ptr @llvm_mips_splati_b_ARG197 %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1)98 store <16 x i8> %1, ptr @llvm_mips_splati_b_RES99 ret void100}101 102declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind103 104; CHECK: llvm_mips_splati_b_test:105; CHECK: ld.b106; CHECK: splati.b107; CHECK: st.b108; CHECK: .size llvm_mips_splati_b_test109;110@llvm_mips_splati_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16111@llvm_mips_splati_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16112 113define void @llvm_mips_splati_h_test() nounwind {114entry:115 %0 = load <8 x i16>, ptr @llvm_mips_splati_h_ARG1116 %1 = tail call <8 x i16> @llvm.mips.splati.h(<8 x i16> %0, i32 1)117 store <8 x i16> %1, ptr @llvm_mips_splati_h_RES118 ret void119}120 121declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind122 123; CHECK: llvm_mips_splati_h_test:124; CHECK: ld.h125; CHECK: splati.h126; CHECK: st.h127; CHECK: .size llvm_mips_splati_h_test128;129@llvm_mips_splati_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16130@llvm_mips_splati_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16131 132define void @llvm_mips_splati_w_test() nounwind {133entry:134 %0 = load <4 x i32>, ptr @llvm_mips_splati_w_ARG1135 %1 = tail call <4 x i32> @llvm.mips.splati.w(<4 x i32> %0, i32 1)136 store <4 x i32> %1, ptr @llvm_mips_splati_w_RES137 ret void138}139 140declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind141 142; CHECK: llvm_mips_splati_w_test:143; CHECK: ld.w144; CHECK: splati.w145; CHECK: st.w146; CHECK: .size llvm_mips_splati_w_test147;148@llvm_mips_splati_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16149@llvm_mips_splati_d_RES = global <2 x i64> <i64 0, i64 0>, align 16150 151define void @llvm_mips_splati_d_test() nounwind {152entry:153 %0 = load <2 x i64>, ptr @llvm_mips_splati_d_ARG1154 %1 = tail call <2 x i64> @llvm.mips.splati.d(<2 x i64> %0, i32 1)155 store <2 x i64> %1, ptr @llvm_mips_splati_d_RES156 ret void157}158 159declare <2 x i64> @llvm.mips.splati.d(<2 x i64>, i32) nounwind160 161; CHECK: llvm_mips_splati_d_test:162; CHECK: ld.d163; CHECK: splati.d164; CHECK: st.d165; CHECK: .size llvm_mips_splati_d_test166;167