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1# RUN: llc %s -start-after=shrink-wrap -mtriple=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null2 3# Test that estimated size of the stack leads to the creation of an emergency4# spill when MSA is in use. Previously, this test case would fail during5# register scavenging due to the lack of a spill slot.6--- |7 define inreg { i64, i64 } @test(i64 inreg %a.coerce0, i64 inreg %a.coerce1, i64 inreg %b.coerce0, i64 inreg %b.coerce1, i32 signext %c) #0 {8 entry:9 %retval = alloca <16 x i8>, align 1610 %a = alloca <16 x i8>, align 1611 %b = alloca <16 x i8>, align 1612 %a.addr = alloca <16 x i8>, align 1613 %b.addr = alloca <16 x i8>, align 1614 %c.addr = alloca i32, align 415 %g = alloca ptr, align 816 %d = alloca ptr, align 817 %0 = bitcast ptr %a to ptr18 %1 = getelementptr inbounds { i64, i64 }, ptr %0, i32 0, i32 019 store i64 %a.coerce0, ptr %1, align 1620 %2 = getelementptr inbounds { i64, i64 }, ptr %0, i32 0, i32 121 store i64 %a.coerce1, ptr %2, align 822 %a1 = load <16 x i8>, ptr %a, align 1623 %3 = bitcast ptr %b to ptr24 %4 = getelementptr inbounds { i64, i64 }, ptr %3, i32 0, i32 025 store i64 %b.coerce0, ptr %4, align 1626 %5 = getelementptr inbounds { i64, i64 }, ptr %3, i32 0, i32 127 store i64 %b.coerce1, ptr %5, align 828 %b2 = load <16 x i8>, ptr %b, align 1629 store <16 x i8> %a1, ptr %a.addr, align 1630 store <16 x i8> %b2, ptr %b.addr, align 1631 store i32 %c, ptr %c.addr, align 432 %6 = alloca i8, i64 6400, align 1633 %7 = bitcast ptr %6 to ptr34 store ptr %7, ptr %g, align 835 %8 = load ptr, ptr %g, align 836 call void @h(ptr %b.addr, ptr %8)37 %9 = load ptr, ptr %g, align 838 %10 = bitcast ptr %9 to ptr39 store ptr %10, ptr %d, align 840 %11 = load <16 x i8>, ptr %a.addr, align 1641 %12 = load ptr, ptr %d, align 842 %arrayidx = getelementptr inbounds i8, ptr %12, i64 043 %13 = load i8, ptr %arrayidx, align 144 %conv = sext i8 %13 to i3245 %14 = call <16 x i8> @llvm.mips.fill.b(i32 %conv)46 %add = add <16 x i8> %11, %1447 %15 = load ptr, ptr %d, align 848 %arrayidx3 = getelementptr inbounds i8, ptr %15, i64 149 %16 = load i8, ptr %arrayidx3, align 150 %conv4 = sext i8 %16 to i3251 %17 = call <16 x i8> @llvm.mips.fill.b(i32 %conv4)52 %add5 = add <16 x i8> %add, %1753 %18 = load <16 x i8>, ptr %b.addr, align 1654 %add6 = add <16 x i8> %18, %add555 store <16 x i8> %add6, ptr %b.addr, align 1656 %19 = load <16 x i8>, ptr %b.addr, align 1657 store <16 x i8> %19, ptr %retval, align 1658 %20 = bitcast ptr %retval to ptr59 %21 = load { i64, i64 }, ptr %20, align 1660 ret { i64, i64 } %2161 }62 63 declare void @h(ptr, ptr)64 65 declare <16 x i8> @llvm.mips.fill.b(i32)66 67 declare void @llvm.stackprotector(ptr, ptr)68 69...70---71name: test72alignment: 873exposesReturnsTwice: false74legalized: false75regBankSelected: false76selected: false77tracksRegLiveness: true78registers:79liveins:80 - { reg: '$a0_64', virtual-reg: '' }81 - { reg: '$a1_64', virtual-reg: '' }82 - { reg: '$a2_64', virtual-reg: '' }83 - { reg: '$a3_64', virtual-reg: '' }84 - { reg: '$t0_64', virtual-reg: '' }85frameInfo:86 isFrameAddressTaken: false87 isReturnAddressTaken: false88 hasStackMap: false89 hasPatchPoint: false90 stackSize: 091 offsetAdjustment: 092 maxAlignment: 1693 adjustsStack: true94 hasCalls: true95 stackProtector: ''96 maxCallFrameSize: 429496729597 hasOpaqueSPAdjustment: false98 hasVAStart: false99 hasMustTailInVarArgFunc: false100 savePoint: []101 restorePoint: []102fixedStack:103stack:104 - { id: 0, name: retval, type: default, offset: 0, size: 16, alignment: 16,105 callee-saved-register: '', debug-info-variable: '',106 debug-info-expression: '', debug-info-location: '' }107 - { id: 1, name: a, type: default, offset: 0, size: 16, alignment: 16,108 callee-saved-register: '', debug-info-variable: '',109 debug-info-expression: '', debug-info-location: '' }110 - { id: 2, name: b, type: default, offset: 0, size: 16, alignment: 16,111 callee-saved-register: '', debug-info-variable: '',112 debug-info-expression: '', debug-info-location: '' }113 - { id: 3, name: a.addr, type: default, offset: 0, size: 16, alignment: 16,114 callee-saved-register: '', debug-info-variable: '',115 debug-info-expression: '', debug-info-location: '' }116 - { id: 4, name: b.addr, type: default, offset: 0, size: 16, alignment: 16,117 callee-saved-register: '', debug-info-variable: '',118 debug-info-expression: '', debug-info-location: '' }119 - { id: 5, name: c.addr, type: default, offset: 0, size: 4, alignment: 4,120 callee-saved-register: '', debug-info-variable: '',121 debug-info-expression: '', debug-info-location: '' }122 - { id: 6, name: g, type: default, offset: 0, size: 8, alignment: 8,123 callee-saved-register: '', debug-info-variable: '',124 debug-info-expression: '', debug-info-location: '' }125 - { id: 7, name: d, type: default, offset: 0, size: 8, alignment: 8,126 callee-saved-register: '', debug-info-variable: '',127 debug-info-expression: '', debug-info-location: '' }128 - { id: 8, name: '', type: default, offset: 0, size: 6400,129 alignment: 16, callee-saved-register: '', debug-info-variable: '',130 debug-info-expression: '', debug-info-location: '' }131constants:132body: |133 bb.0.entry:134 liveins: $a0_64, $a1_64, $a2_64, $a3_64, $t0_64135 136 SD killed $a0_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)137 SD killed $a1_64, %stack.1.a, 8 :: (store (s64) into %ir.2)138 $w0 = LD_B %stack.1.a, 0 :: (dereferenceable load (s128) from %ir.a)139 SD killed $a2_64, %stack.2.b, 0 :: (store (s64) into %ir.4, align 16)140 SD killed $a3_64, %stack.2.b, 8 :: (store (s64) into %ir.5)141 $w1 = LD_B %stack.2.b, 0 :: (dereferenceable load (s128) from %ir.b)142 ST_B killed $w0, %stack.3.a.addr, 0 :: (store (s128) into %ir.a.addr)143 ST_B killed $w1, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)144 SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store (s32) into %ir.c.addr)145 $at_64 = LEA_ADDiu64 %stack.8, 0146 SD killed $at_64, %stack.6.g, 0 :: (store (s64) into %ir.g)147 $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)148 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp149 $a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0150 JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp151 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp152 $at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)153 $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)154 $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)155 $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)156 $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)157 $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)158 $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)159 $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)160 $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)161 $t2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)162 $t3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)163 $t4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)164 $t5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)165 $t6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)166 $t7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)167 $s0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)168 $s1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)169 $s2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)170 $s3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)171 $s4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)172 $s5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)173 $s6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)174 $s7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)175 $t8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)176 $t9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)177 $ra_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)178 $w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load (s128) from %ir.a.addr)179 SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)180 SD $v0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)181 SD $v1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)182 SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)183 SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)184 SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)185 SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)186 SD $t0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)187 SD $t1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)188 SD $t2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)189 SD $t3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)190 SD $t4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)191 SD $t5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)192 SD $t6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)193 SD $t7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)194 SD $s0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)195 SD $s1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)196 SD $s2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)197 SD $s3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)198 SD $s4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)199 SD $s5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)200 SD $s6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)201 SD $s7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)202 SD $t8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)203 SD $t9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)204 SD $ra_64, %stack.7.d, 0 :: (store (s64) into %ir.d)205 $at_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)206 $v0 = LB $at_64, 0 :: (load (s8) from %ir.arrayidx)207 $w1 = FILL_B killed $v0208 $w0 = ADDV_B killed $w0, killed $w1209 $at = LB killed $at_64, 1 :: (load (s8) from %ir.arrayidx3)210 $w1 = FILL_B killed $at211 $w0 = ADDV_B killed $w0, killed $w1212 $w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)213 $w0 = ADDV_B killed $w1, killed $w0214 ST_B killed $w0, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)215 $w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)216 ST_B killed $w0, %stack.0.retval, 0 :: (store (s128) into %ir.retval)217 $v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load (s64) from %ir.20, basealign 16)218 $v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load (s64) from %ir.20 + 8, basealign 16)219 RetRA implicit $v0_64, implicit $v1_64220 221...222