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1; Test the MSA intrinsics that are encoded with the I5 instruction format.2; There are lots of these so this covers those beginning with 'a'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 169 10define void @llvm_mips_addvi_b_test() nounwind {11entry:12 %0 = load <16 x i8>, ptr @llvm_mips_addvi_b_ARG113 %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 14)14 store <16 x i8> %1, ptr @llvm_mips_addvi_b_RES15 ret void16}17 18declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32) nounwind19 20; CHECK: llvm_mips_addvi_b_test:21; CHECK: ld.b22; CHECK: addvi.b23; CHECK: st.b24; CHECK: .size llvm_mips_addvi_b_test25;26@llvm_mips_addvi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1627@llvm_mips_addvi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1628 29define void @llvm_mips_addvi_h_test() nounwind {30entry:31 %0 = load <8 x i16>, ptr @llvm_mips_addvi_h_ARG132 %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 14)33 store <8 x i16> %1, ptr @llvm_mips_addvi_h_RES34 ret void35}36 37declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32) nounwind38 39; CHECK: llvm_mips_addvi_h_test:40; CHECK: ld.h41; CHECK: addvi.h42; CHECK: st.h43; CHECK: .size llvm_mips_addvi_h_test44;45@llvm_mips_addvi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1646@llvm_mips_addvi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1647 48define void @llvm_mips_addvi_w_test() nounwind {49entry:50 %0 = load <4 x i32>, ptr @llvm_mips_addvi_w_ARG151 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 14)52 store <4 x i32> %1, ptr @llvm_mips_addvi_w_RES53 ret void54}55 56declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32) nounwind57 58; CHECK: llvm_mips_addvi_w_test:59; CHECK: ld.w60; CHECK: addvi.w61; CHECK: st.w62; CHECK: .size llvm_mips_addvi_w_test63;64@llvm_mips_addvi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1665@llvm_mips_addvi_d_RES = global <2 x i64> <i64 0, i64 0>, align 1666 67define void @llvm_mips_addvi_d_test() nounwind {68entry:69 %0 = load <2 x i64>, ptr @llvm_mips_addvi_d_ARG170 %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 14)71 store <2 x i64> %1, ptr @llvm_mips_addvi_d_RES72 ret void73}74 75declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32) nounwind76 77; CHECK: llvm_mips_addvi_d_test:78; CHECK: ld.d79; CHECK: addvi.d80; CHECK: st.d81; CHECK: .size llvm_mips_addvi_d_test82;83