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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test the MSA intrinsics that are encoded with the I5 instruction format.3; There are lots of these so this covers those beginning with 'b'4 5; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s7 8@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 169@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_bclri_b_test() nounwind {12; CHECK-LABEL: llvm_mips_bclri_b_test:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: lui $2, %hi(_gp_disp)15; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)16; CHECK-NEXT: addu $1, $2, $2517; CHECK-NEXT: lw $2, %got(llvm_mips_bclri_b_ARG1)($1)18; CHECK-NEXT: ld.b $w0, 0($2)19; CHECK-NEXT: andi.b $w0, $w0, 12720; CHECK-NEXT: lw $1, %got(llvm_mips_bclri_b_RES)($1)21; CHECK-NEXT: jr $ra22; CHECK-NEXT: st.b $w0, 0($1)23entry:24 %0 = load <16 x i8>, ptr @llvm_mips_bclri_b_ARG125 %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)26 store <16 x i8> %1, ptr @llvm_mips_bclri_b_RES27 ret void28}29declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind30 31@llvm_mips_bclri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1632@llvm_mips_bclri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1633 34define void @llvm_mips_bclri_h_test() nounwind {35; CHECK-LABEL: llvm_mips_bclri_h_test:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: lui $2, %hi(_gp_disp)38; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)39; CHECK-NEXT: addu $1, $2, $2540; CHECK-NEXT: lw $2, %got(llvm_mips_bclri_h_ARG1)($1)41; CHECK-NEXT: ld.h $w0, 0($2)42; CHECK-NEXT: bclri.h $w0, $w0, 743; CHECK-NEXT: lw $1, %got(llvm_mips_bclri_h_RES)($1)44; CHECK-NEXT: jr $ra45; CHECK-NEXT: st.h $w0, 0($1)46entry:47 %0 = load <8 x i16>, ptr @llvm_mips_bclri_h_ARG148 %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)49 store <8 x i16> %1, ptr @llvm_mips_bclri_h_RES50 ret void51}52declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind53 54@llvm_mips_bclri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1655@llvm_mips_bclri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1656 57define void @llvm_mips_bclri_w_test() nounwind {58; CHECK-LABEL: llvm_mips_bclri_w_test:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: lui $2, %hi(_gp_disp)61; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)62; CHECK-NEXT: addu $1, $2, $2563; CHECK-NEXT: lw $2, %got(llvm_mips_bclri_w_ARG1)($1)64; CHECK-NEXT: ld.w $w0, 0($2)65; CHECK-NEXT: bclri.w $w0, $w0, 766; CHECK-NEXT: lw $1, %got(llvm_mips_bclri_w_RES)($1)67; CHECK-NEXT: jr $ra68; CHECK-NEXT: st.w $w0, 0($1)69entry:70 %0 = load <4 x i32>, ptr @llvm_mips_bclri_w_ARG171 %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)72 store <4 x i32> %1, ptr @llvm_mips_bclri_w_RES73 ret void74}75declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind76 77@llvm_mips_bclri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1678@llvm_mips_bclri_d_RES = global <2 x i64> <i64 0, i64 0>, align 1679 80define void @llvm_mips_bclri_d_test() nounwind {81; CHECK-LABEL: llvm_mips_bclri_d_test:82; CHECK: # %bb.0: # %entry83; CHECK-NEXT: lui $2, %hi(_gp_disp)84; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)85; CHECK-NEXT: addu $1, $2, $2586; CHECK-NEXT: lw $2, %got(llvm_mips_bclri_d_ARG1)($1)87; CHECK-NEXT: ld.d $w0, 0($2)88; CHECK-NEXT: bclri.d $w0, $w0, 789; CHECK-NEXT: lw $1, %got(llvm_mips_bclri_d_RES)($1)90; CHECK-NEXT: jr $ra91; CHECK-NEXT: st.d $w0, 0($1)92entry:93 %0 = load <2 x i64>, ptr @llvm_mips_bclri_d_ARG194 %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)95 store <2 x i64> %1, ptr @llvm_mips_bclri_d_RES96 ret void97}98declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind99 100@llvm_mips_binsli_b_ARG1 = global <16 x i8> zeroinitializer, align 16101@llvm_mips_binsli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16102@llvm_mips_binsli_b_RES = global <16 x i8> zeroinitializer, align 16103 104define void @llvm_mips_binsli_b_test() nounwind {105; CHECK-LABEL: llvm_mips_binsli_b_test:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: lui $2, %hi(_gp_disp)108; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)109; CHECK-NEXT: addu $1, $2, $25110; CHECK-NEXT: lw $2, %got(llvm_mips_binsli_b_ARG1)($1)111; CHECK-NEXT: lw $3, %got(llvm_mips_binsli_b_ARG2)($1)112; CHECK-NEXT: ld.b $w0, 0($3)113; CHECK-NEXT: ld.b $w1, 0($2)114; CHECK-NEXT: binsli.b $w1, $w0, 6115; CHECK-NEXT: lw $1, %got(llvm_mips_binsli_b_RES)($1)116; CHECK-NEXT: jr $ra117; CHECK-NEXT: st.b $w1, 0($1)118entry:119 %0 = load <16 x i8>, ptr @llvm_mips_binsli_b_ARG1120 %1 = load <16 x i8>, ptr @llvm_mips_binsli_b_ARG2121 %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 6)122 store <16 x i8> %2, ptr @llvm_mips_binsli_b_RES123 ret void124}125declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind126 127@llvm_mips_binsli_h_ARG1 = global <8 x i16> zeroinitializer, align 16128@llvm_mips_binsli_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16129@llvm_mips_binsli_h_RES = global <8 x i16> zeroinitializer, align 16130 131define void @llvm_mips_binsli_h_test() nounwind {132; CHECK-LABEL: llvm_mips_binsli_h_test:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: lui $2, %hi(_gp_disp)135; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)136; CHECK-NEXT: addu $1, $2, $25137; CHECK-NEXT: lw $2, %got(llvm_mips_binsli_h_ARG1)($1)138; CHECK-NEXT: lw $3, %got(llvm_mips_binsli_h_ARG2)($1)139; CHECK-NEXT: ld.h $w0, 0($3)140; CHECK-NEXT: ld.h $w1, 0($2)141; CHECK-NEXT: binsli.h $w1, $w0, 7142; CHECK-NEXT: lw $1, %got(llvm_mips_binsli_h_RES)($1)143; CHECK-NEXT: jr $ra144; CHECK-NEXT: st.h $w1, 0($1)145entry:146 %0 = load <8 x i16>, ptr @llvm_mips_binsli_h_ARG1147 %1 = load <8 x i16>, ptr @llvm_mips_binsli_h_ARG2148 %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7)149 store <8 x i16> %2, ptr @llvm_mips_binsli_h_RES150 ret void151}152declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind153 154@llvm_mips_binsli_w_ARG1 = global <4 x i32> zeroinitializer, align 16155@llvm_mips_binsli_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16156@llvm_mips_binsli_w_RES = global <4 x i32> zeroinitializer, align 16157 158define void @llvm_mips_binsli_w_test() nounwind {159; CHECK-LABEL: llvm_mips_binsli_w_test:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: lui $2, %hi(_gp_disp)162; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)163; CHECK-NEXT: addu $1, $2, $25164; CHECK-NEXT: lw $2, %got(llvm_mips_binsli_w_ARG1)($1)165; CHECK-NEXT: lw $3, %got(llvm_mips_binsli_w_ARG2)($1)166; CHECK-NEXT: ld.w $w0, 0($3)167; CHECK-NEXT: ld.w $w1, 0($2)168; CHECK-NEXT: binsli.w $w1, $w0, 7169; CHECK-NEXT: lw $1, %got(llvm_mips_binsli_w_RES)($1)170; CHECK-NEXT: jr $ra171; CHECK-NEXT: st.w $w1, 0($1)172entry:173 %0 = load <4 x i32>, ptr @llvm_mips_binsli_w_ARG1174 %1 = load <4 x i32>, ptr @llvm_mips_binsli_w_ARG2175 %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7)176 store <4 x i32> %2, ptr @llvm_mips_binsli_w_RES177 ret void178}179declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind180 181@llvm_mips_binsli_d_ARG1 = global <2 x i64> zeroinitializer, align 16182@llvm_mips_binsli_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16183@llvm_mips_binsli_d_RES = global <2 x i64> zeroinitializer, align 16184 185define void @llvm_mips_binsli_d_test() nounwind {186; CHECK-LABEL: llvm_mips_binsli_d_test:187; CHECK: # %bb.0: # %entry188; CHECK-NEXT: lui $2, %hi(_gp_disp)189; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)190; CHECK-NEXT: addu $1, $2, $25191; CHECK-NEXT: lw $2, %got(llvm_mips_binsli_d_ARG1)($1)192; CHECK-NEXT: lw $3, %got(llvm_mips_binsli_d_ARG2)($1)193; CHECK-NEXT: ld.d $w0, 0($3)194; CHECK-NEXT: ld.d $w1, 0($2)195; CHECK-NEXT: binsli.d $w1, $w0, 61196; CHECK-NEXT: lw $1, %got(llvm_mips_binsli_d_RES)($1)197; CHECK-NEXT: jr $ra198; CHECK-NEXT: st.d $w1, 0($1)199entry:200 %0 = load <2 x i64>, ptr @llvm_mips_binsli_d_ARG1201 %1 = load <2 x i64>, ptr @llvm_mips_binsli_d_ARG2202 ; TODO: We use a particularly wide mask here to work around a legalization203 ; issue. If the mask doesn't fit within a 10-bit immediate, it gets204 ; legalized into a constant pool. We should add a test to cover the205 ; other cases once they correctly select binsli.d.206 %2 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, <2 x i64> %1, i32 61)207 store <2 x i64> %2, ptr @llvm_mips_binsli_d_RES208 ret void209}210declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind211 212@llvm_mips_binsri_b_ARG1 = global <16 x i8> zeroinitializer, align 16213@llvm_mips_binsri_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16214@llvm_mips_binsri_b_RES = global <16 x i8> zeroinitializer, align 16215 216define void @llvm_mips_binsri_b_test() nounwind {217; CHECK-LABEL: llvm_mips_binsri_b_test:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: lui $2, %hi(_gp_disp)220; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)221; CHECK-NEXT: addu $1, $2, $25222; CHECK-NEXT: lw $2, %got(llvm_mips_binsri_b_ARG1)($1)223; CHECK-NEXT: lw $3, %got(llvm_mips_binsri_b_ARG2)($1)224; CHECK-NEXT: ld.b $w0, 0($3)225; CHECK-NEXT: ld.b $w1, 0($2)226; CHECK-NEXT: binsri.b $w1, $w0, 6227; CHECK-NEXT: lw $1, %got(llvm_mips_binsri_b_RES)($1)228; CHECK-NEXT: jr $ra229; CHECK-NEXT: st.b $w1, 0($1)230entry:231 %0 = load <16 x i8>, ptr @llvm_mips_binsri_b_ARG1232 %1 = load <16 x i8>, ptr @llvm_mips_binsri_b_ARG2233 %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 6)234 store <16 x i8> %2, ptr @llvm_mips_binsri_b_RES235 ret void236}237declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind238 239@llvm_mips_binsri_h_ARG1 = global <8 x i16> zeroinitializer, align 16240@llvm_mips_binsri_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16241@llvm_mips_binsri_h_RES = global <8 x i16> zeroinitializer, align 16242 243define void @llvm_mips_binsri_h_test() nounwind {244; CHECK-LABEL: llvm_mips_binsri_h_test:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: lui $2, %hi(_gp_disp)247; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)248; CHECK-NEXT: addu $1, $2, $25249; CHECK-NEXT: lw $2, %got(llvm_mips_binsri_h_ARG1)($1)250; CHECK-NEXT: lw $3, %got(llvm_mips_binsri_h_ARG2)($1)251; CHECK-NEXT: ld.h $w0, 0($3)252; CHECK-NEXT: ld.h $w1, 0($2)253; CHECK-NEXT: binsri.h $w1, $w0, 7254; CHECK-NEXT: lw $1, %got(llvm_mips_binsri_h_RES)($1)255; CHECK-NEXT: jr $ra256; CHECK-NEXT: st.h $w1, 0($1)257entry:258 %0 = load <8 x i16>, ptr @llvm_mips_binsri_h_ARG1259 %1 = load <8 x i16>, ptr @llvm_mips_binsri_h_ARG2260 %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7)261 store <8 x i16> %2, ptr @llvm_mips_binsri_h_RES262 ret void263}264declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind265 266@llvm_mips_binsri_w_ARG1 = global <4 x i32> zeroinitializer, align 16267@llvm_mips_binsri_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16268@llvm_mips_binsri_w_RES = global <4 x i32> zeroinitializer, align 16269 270define void @llvm_mips_binsri_w_test() nounwind {271; CHECK-LABEL: llvm_mips_binsri_w_test:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: lui $2, %hi(_gp_disp)274; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)275; CHECK-NEXT: addu $1, $2, $25276; CHECK-NEXT: lw $2, %got(llvm_mips_binsri_w_ARG1)($1)277; CHECK-NEXT: lw $3, %got(llvm_mips_binsri_w_ARG2)($1)278; CHECK-NEXT: ld.w $w0, 0($3)279; CHECK-NEXT: ld.w $w1, 0($2)280; CHECK-NEXT: binsri.w $w1, $w0, 7281; CHECK-NEXT: lw $1, %got(llvm_mips_binsri_w_RES)($1)282; CHECK-NEXT: jr $ra283; CHECK-NEXT: st.w $w1, 0($1)284entry:285 %0 = load <4 x i32>, ptr @llvm_mips_binsri_w_ARG1286 %1 = load <4 x i32>, ptr @llvm_mips_binsri_w_ARG2287 %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7)288 store <4 x i32> %2, ptr @llvm_mips_binsri_w_RES289 ret void290}291declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind292 293@llvm_mips_binsri_d_ARG1 = global <2 x i64> zeroinitializer, align 16294@llvm_mips_binsri_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16295@llvm_mips_binsri_d_RES = global <2 x i64> zeroinitializer, align 16296 297define void @llvm_mips_binsri_d_test() nounwind {298; CHECK-LABEL: llvm_mips_binsri_d_test:299; CHECK: # %bb.0: # %entry300; CHECK-NEXT: lui $2, %hi(_gp_disp)301; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)302; CHECK-NEXT: addu $1, $2, $25303; CHECK-NEXT: lw $2, %got(llvm_mips_binsri_d_ARG1)($1)304; CHECK-NEXT: lw $3, %got(llvm_mips_binsri_d_ARG2)($1)305; CHECK-NEXT: ld.d $w0, 0($3)306; CHECK-NEXT: ld.d $w1, 0($2)307; CHECK-NEXT: binsri.d $w1, $w0, 7308; CHECK-NEXT: lw $1, %got(llvm_mips_binsri_d_RES)($1)309; CHECK-NEXT: jr $ra310; CHECK-NEXT: st.d $w1, 0($1)311entry:312 %0 = load <2 x i64>, ptr @llvm_mips_binsri_d_ARG1313 %1 = load <2 x i64>, ptr @llvm_mips_binsri_d_ARG2314 %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7)315 store <2 x i64> %2, ptr @llvm_mips_binsri_d_RES316 ret void317}318declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind319 320@llvm_mips_bnegi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16321@llvm_mips_bnegi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16322 323define void @llvm_mips_bnegi_b_test() nounwind {324; CHECK-LABEL: llvm_mips_bnegi_b_test:325; CHECK: # %bb.0: # %entry326; CHECK-NEXT: lui $2, %hi(_gp_disp)327; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)328; CHECK-NEXT: addu $1, $2, $25329; CHECK-NEXT: lw $2, %got(llvm_mips_bnegi_b_ARG1)($1)330; CHECK-NEXT: ld.b $w0, 0($2)331; CHECK-NEXT: bnegi.b $w0, $w0, 7332; CHECK-NEXT: lw $1, %got(llvm_mips_bnegi_b_RES)($1)333; CHECK-NEXT: jr $ra334; CHECK-NEXT: st.b $w0, 0($1)335entry:336 %0 = load <16 x i8>, ptr @llvm_mips_bnegi_b_ARG1337 %1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7)338 store <16 x i8> %1, ptr @llvm_mips_bnegi_b_RES339 ret void340}341declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind342 343@llvm_mips_bnegi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16344@llvm_mips_bnegi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16345 346define void @llvm_mips_bnegi_h_test() nounwind {347; CHECK-LABEL: llvm_mips_bnegi_h_test:348; CHECK: # %bb.0: # %entry349; CHECK-NEXT: lui $2, %hi(_gp_disp)350; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)351; CHECK-NEXT: addu $1, $2, $25352; CHECK-NEXT: lw $2, %got(llvm_mips_bnegi_h_ARG1)($1)353; CHECK-NEXT: ld.h $w0, 0($2)354; CHECK-NEXT: bnegi.h $w0, $w0, 7355; CHECK-NEXT: lw $1, %got(llvm_mips_bnegi_h_RES)($1)356; CHECK-NEXT: jr $ra357; CHECK-NEXT: st.h $w0, 0($1)358entry:359 %0 = load <8 x i16>, ptr @llvm_mips_bnegi_h_ARG1360 %1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7)361 store <8 x i16> %1, ptr @llvm_mips_bnegi_h_RES362 ret void363}364declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind365 366@llvm_mips_bnegi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16367@llvm_mips_bnegi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16368 369define void @llvm_mips_bnegi_w_test() nounwind {370; CHECK-LABEL: llvm_mips_bnegi_w_test:371; CHECK: # %bb.0: # %entry372; CHECK-NEXT: lui $2, %hi(_gp_disp)373; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)374; CHECK-NEXT: addu $1, $2, $25375; CHECK-NEXT: lw $2, %got(llvm_mips_bnegi_w_ARG1)($1)376; CHECK-NEXT: ld.w $w0, 0($2)377; CHECK-NEXT: bnegi.w $w0, $w0, 7378; CHECK-NEXT: lw $1, %got(llvm_mips_bnegi_w_RES)($1)379; CHECK-NEXT: jr $ra380; CHECK-NEXT: st.w $w0, 0($1)381entry:382 %0 = load <4 x i32>, ptr @llvm_mips_bnegi_w_ARG1383 %1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7)384 store <4 x i32> %1, ptr @llvm_mips_bnegi_w_RES385 ret void386}387declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind388 389@llvm_mips_bnegi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16390@llvm_mips_bnegi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16391 392define void @llvm_mips_bnegi_d_test() nounwind {393; CHECK-LABEL: llvm_mips_bnegi_d_test:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: lui $2, %hi(_gp_disp)396; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)397; CHECK-NEXT: addu $1, $2, $25398; CHECK-NEXT: lw $2, %got(llvm_mips_bnegi_d_ARG1)($1)399; CHECK-NEXT: ld.d $w0, 0($2)400; CHECK-NEXT: bnegi.d $w0, $w0, 7401; CHECK-NEXT: lw $1, %got(llvm_mips_bnegi_d_RES)($1)402; CHECK-NEXT: jr $ra403; CHECK-NEXT: st.d $w0, 0($1)404entry:405 %0 = load <2 x i64>, ptr @llvm_mips_bnegi_d_ARG1406 %1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7)407 store <2 x i64> %1, ptr @llvm_mips_bnegi_d_RES408 ret void409}410declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind411 412@llvm_mips_bseti_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16413@llvm_mips_bseti_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16414 415define void @llvm_mips_bseti_b_test() nounwind {416; CHECK-LABEL: llvm_mips_bseti_b_test:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: lui $2, %hi(_gp_disp)419; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)420; CHECK-NEXT: addu $1, $2, $25421; CHECK-NEXT: lw $2, %got(llvm_mips_bseti_b_ARG1)($1)422; CHECK-NEXT: ld.b $w0, 0($2)423; CHECK-NEXT: bseti.b $w0, $w0, 7424; CHECK-NEXT: lw $1, %got(llvm_mips_bseti_b_RES)($1)425; CHECK-NEXT: jr $ra426; CHECK-NEXT: st.b $w0, 0($1)427entry:428 %0 = load <16 x i8>, ptr @llvm_mips_bseti_b_ARG1429 %1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7)430 store <16 x i8> %1, ptr @llvm_mips_bseti_b_RES431 ret void432}433declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind434 435@llvm_mips_bseti_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16436@llvm_mips_bseti_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16437 438define void @llvm_mips_bseti_h_test() nounwind {439; CHECK-LABEL: llvm_mips_bseti_h_test:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: lui $2, %hi(_gp_disp)442; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)443; CHECK-NEXT: addu $1, $2, $25444; CHECK-NEXT: lw $2, %got(llvm_mips_bseti_h_ARG1)($1)445; CHECK-NEXT: ld.h $w0, 0($2)446; CHECK-NEXT: bseti.h $w0, $w0, 7447; CHECK-NEXT: lw $1, %got(llvm_mips_bseti_h_RES)($1)448; CHECK-NEXT: jr $ra449; CHECK-NEXT: st.h $w0, 0($1)450entry:451 %0 = load <8 x i16>, ptr @llvm_mips_bseti_h_ARG1452 %1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7)453 store <8 x i16> %1, ptr @llvm_mips_bseti_h_RES454 ret void455}456declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind457 458@llvm_mips_bseti_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16459@llvm_mips_bseti_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16460 461define void @llvm_mips_bseti_w_test() nounwind {462; CHECK-LABEL: llvm_mips_bseti_w_test:463; CHECK: # %bb.0: # %entry464; CHECK-NEXT: lui $2, %hi(_gp_disp)465; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)466; CHECK-NEXT: addu $1, $2, $25467; CHECK-NEXT: lw $2, %got(llvm_mips_bseti_w_ARG1)($1)468; CHECK-NEXT: ld.w $w0, 0($2)469; CHECK-NEXT: bseti.w $w0, $w0, 7470; CHECK-NEXT: lw $1, %got(llvm_mips_bseti_w_RES)($1)471; CHECK-NEXT: jr $ra472; CHECK-NEXT: st.w $w0, 0($1)473entry:474 %0 = load <4 x i32>, ptr @llvm_mips_bseti_w_ARG1475 %1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7)476 store <4 x i32> %1, ptr @llvm_mips_bseti_w_RES477 ret void478}479declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind480 481@llvm_mips_bseti_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16482@llvm_mips_bseti_d_RES = global <2 x i64> <i64 0, i64 0>, align 16483 484define void @llvm_mips_bseti_d_test() nounwind {485; CHECK-LABEL: llvm_mips_bseti_d_test:486; CHECK: # %bb.0: # %entry487; CHECK-NEXT: lui $2, %hi(_gp_disp)488; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)489; CHECK-NEXT: addu $1, $2, $25490; CHECK-NEXT: lw $2, %got(llvm_mips_bseti_d_ARG1)($1)491; CHECK-NEXT: ld.d $w0, 0($2)492; CHECK-NEXT: bseti.d $w0, $w0, 7493; CHECK-NEXT: lw $1, %got(llvm_mips_bseti_d_RES)($1)494; CHECK-NEXT: jr $ra495; CHECK-NEXT: st.d $w0, 0($1)496entry:497 %0 = load <2 x i64>, ptr @llvm_mips_bseti_d_ARG1498 %1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7)499 store <2 x i64> %1, ptr @llvm_mips_bseti_d_RES500 ret void501}502declare <2 x i64> @llvm.mips.bseti.d(<2 x i64>, i32) nounwind503