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1; Test the MSA intrinsics that are encoded with the I5 instruction format.2; There are lots of these so this covers those beginning with 'c'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 169@llvm_mips_ceqi_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_ceqi_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_ceqi_b_ARG114 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14)15 store <16 x i8> %1, ptr @llvm_mips_ceqi_b_RES116 %2 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 -14)17 store <16 x i8> %2, ptr @llvm_mips_ceqi_b_RES218 ret void19}20 21declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind22 23; CHECK: llvm_mips_ceqi_b_test:24; CHECK: ld.b [[RS:\$w[0-9]+]]25; CHECK: ceqi.b [[RD1:\$w[0-9]]], [[RS]], 1426; CHECK: st.b [[RD1]]27; CHECK: ceqi.b [[RD2:\$w[0-9]]], [[RS]], -1428; CHECK: st.b [[RD2]]29; CHECK: .size llvm_mips_ceqi_b_test30;31@llvm_mips_ceqi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1632@llvm_mips_ceqi_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1633@llvm_mips_ceqi_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1634 35define void @llvm_mips_ceqi_h_test() nounwind {36entry:37 %0 = load <8 x i16>, ptr @llvm_mips_ceqi_h_ARG138 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14)39 store <8 x i16> %1, ptr @llvm_mips_ceqi_h_RES140 %2 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 -14)41 store <8 x i16> %2, ptr @llvm_mips_ceqi_h_RES242 ret void43}44 45declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind46 47; CHECK: llvm_mips_ceqi_h_test:48; CHECK: ld.h [[RS:\$w[0-9]+]]49; CHECK: ceqi.h [[RD1:\$w[0-9]]], [[RS]], 1450; CHECK: st.h [[RD1]]51; CHECK: ceqi.h [[RD2:\$w[0-9]]], [[RS]], -1452; CHECK: st.h [[RD2]]53; CHECK: .size llvm_mips_ceqi_h_test54;55@llvm_mips_ceqi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1656@llvm_mips_ceqi_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1657@llvm_mips_ceqi_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1658 59define void @llvm_mips_ceqi_w_test() nounwind {60entry:61 %0 = load <4 x i32>, ptr @llvm_mips_ceqi_w_ARG162 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14)63 store <4 x i32> %1, ptr @llvm_mips_ceqi_w_RES164 %2 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 -14)65 store <4 x i32> %2, ptr @llvm_mips_ceqi_w_RES266 ret void67}68 69declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind70 71; CHECK: llvm_mips_ceqi_w_test:72; CHECK: ld.w [[RS:\$w[0-9]+]]73; CHECK: ceqi.w [[RD1:\$w[0-9]]], [[RS]], 1474; CHECK: st.w [[RD1]]75; CHECK: ceqi.w [[RD2:\$w[0-9]]], [[RS]], -1476; CHECK: st.w [[RD2]]77; CHECK: .size llvm_mips_ceqi_w_test78;79@llvm_mips_ceqi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1680@llvm_mips_ceqi_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 1681@llvm_mips_ceqi_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 1682 83define void @llvm_mips_ceqi_d_test() nounwind {84entry:85 %0 = load <2 x i64>, ptr @llvm_mips_ceqi_d_ARG186 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14)87 store <2 x i64> %1, ptr @llvm_mips_ceqi_d_RES188 %2 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 -14)89 store <2 x i64> %2, ptr @llvm_mips_ceqi_d_RES290 ret void91}92 93declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind94 95; CHECK: llvm_mips_ceqi_d_test:96; CHECK: ld.d [[RS:\$w[0-9]+]]97; CHECK: ceqi.d [[RD1:\$w[0-9]]], [[RS]], 1498; CHECK: st.d [[RD1]]99; CHECK: ceqi.d [[RD2:\$w[0-9]]], [[RS]], -14100; CHECK: st.d [[RD2]]101; CHECK: .size llvm_mips_ceqi_d_test102;103@llvm_mips_clei_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16104@llvm_mips_clei_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16105@llvm_mips_clei_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16106 107define void @llvm_mips_clei_s_b_test() nounwind {108entry:109 %0 = load <16 x i8>, ptr @llvm_mips_clei_s_b_ARG1110 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14)111 store <16 x i8> %1, ptr @llvm_mips_clei_s_b_RES1112 %2 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 -14)113 store <16 x i8> %2, ptr @llvm_mips_clei_s_b_RES2114 ret void115}116 117declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind118 119; CHECK: llvm_mips_clei_s_b_test:120; CHECK: ld.b [[RS:\$w[0-9]+]]121; CHECK: clei_s.b [[RD1:\$w[0-9]]], [[RS]], 14122; CHECK: st.b [[RD1]]123; CHECK: clei_s.b [[RD2:\$w[0-9]]], [[RS]], -14124; CHECK: st.b [[RD2]]125; CHECK: .size llvm_mips_clei_s_b_test126;127@llvm_mips_clei_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16128@llvm_mips_clei_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16129@llvm_mips_clei_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16130 131define void @llvm_mips_clei_s_h_test() nounwind {132entry:133 %0 = load <8 x i16>, ptr @llvm_mips_clei_s_h_ARG1134 %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14)135 store <8 x i16> %1, ptr @llvm_mips_clei_s_h_RES1136 %2 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 -14)137 store <8 x i16> %2, ptr @llvm_mips_clei_s_h_RES2138 ret void139}140 141declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind142 143; CHECK: llvm_mips_clei_s_h_test:144; CHECK: ld.h [[RS:\$w[0-9]+]]145; CHECK: clei_s.h [[RD1:\$w[0-9]]], [[RS]], 14146; CHECK: st.h [[RD1]]147; CHECK: clei_s.h [[RD2:\$w[0-9]]], [[RS]], -14148; CHECK: st.h [[RD2]]149; CHECK: .size llvm_mips_clei_s_h_test150;151@llvm_mips_clei_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16152@llvm_mips_clei_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16153@llvm_mips_clei_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16154 155define void @llvm_mips_clei_s_w_test() nounwind {156entry:157 %0 = load <4 x i32>, ptr @llvm_mips_clei_s_w_ARG1158 %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14)159 store <4 x i32> %1, ptr @llvm_mips_clei_s_w_RES1160 %2 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 -14)161 store <4 x i32> %2, ptr @llvm_mips_clei_s_w_RES2162 ret void163}164 165declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind166 167; CHECK: llvm_mips_clei_s_w_test:168; CHECK: ld.w [[RS:\$w[0-9]+]]169; CHECK: clei_s.w [[RD1:\$w[0-9]]], [[RS]], 14170; CHECK: st.w [[RD1]]171; CHECK: clei_s.w [[RD2:\$w[0-9]]], [[RS]], -14172; CHECK: st.w [[RD2]]173; CHECK: .size llvm_mips_clei_s_w_test174;175@llvm_mips_clei_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16176@llvm_mips_clei_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16177@llvm_mips_clei_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16178 179define void @llvm_mips_clei_s_d_test() nounwind {180entry:181 %0 = load <2 x i64>, ptr @llvm_mips_clei_s_d_ARG1182 %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14)183 store <2 x i64> %1, ptr @llvm_mips_clei_s_d_RES1184 %2 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 -14)185 store <2 x i64> %2, ptr @llvm_mips_clei_s_d_RES2186 ret void187}188 189declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind190 191; CHECK: llvm_mips_clei_s_d_test:192; CHECK: ld.d [[RS:\$w[0-9]+]]193; CHECK: clei_s.d [[RD1:\$w[0-9]]], [[RS]], 14194; CHECK: st.d [[RD1]]195; CHECK: clei_s.d [[RD2:\$w[0-9]]], [[RS]], -14196; CHECK: st.d [[RD2]]197; CHECK: .size llvm_mips_clei_s_d_test198;199@llvm_mips_clei_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16200@llvm_mips_clei_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16201 202define void @llvm_mips_clei_u_b_test() nounwind {203entry:204 %0 = load <16 x i8>, ptr @llvm_mips_clei_u_b_ARG1205 %1 = tail call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %0, i32 14)206 store <16 x i8> %1, ptr @llvm_mips_clei_u_b_RES207 ret void208}209 210declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32) nounwind211 212; CHECK: llvm_mips_clei_u_b_test:213; CHECK: ld.b214; CHECK: clei_u.b215; CHECK: st.b216; CHECK: .size llvm_mips_clei_u_b_test217;218@llvm_mips_clei_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16219@llvm_mips_clei_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16220 221define void @llvm_mips_clei_u_h_test() nounwind {222entry:223 %0 = load <8 x i16>, ptr @llvm_mips_clei_u_h_ARG1224 %1 = tail call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %0, i32 14)225 store <8 x i16> %1, ptr @llvm_mips_clei_u_h_RES226 ret void227}228 229declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32) nounwind230 231; CHECK: llvm_mips_clei_u_h_test:232; CHECK: ld.h233; CHECK: clei_u.h234; CHECK: st.h235; CHECK: .size llvm_mips_clei_u_h_test236;237@llvm_mips_clei_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16238@llvm_mips_clei_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16239 240define void @llvm_mips_clei_u_w_test() nounwind {241entry:242 %0 = load <4 x i32>, ptr @llvm_mips_clei_u_w_ARG1243 %1 = tail call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %0, i32 14)244 store <4 x i32> %1, ptr @llvm_mips_clei_u_w_RES245 ret void246}247 248declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32) nounwind249 250; CHECK: llvm_mips_clei_u_w_test:251; CHECK: ld.w252; CHECK: clei_u.w253; CHECK: st.w254; CHECK: .size llvm_mips_clei_u_w_test255;256@llvm_mips_clei_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16257@llvm_mips_clei_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16258 259define void @llvm_mips_clei_u_d_test() nounwind {260entry:261 %0 = load <2 x i64>, ptr @llvm_mips_clei_u_d_ARG1262 %1 = tail call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %0, i32 14)263 store <2 x i64> %1, ptr @llvm_mips_clei_u_d_RES264 ret void265}266 267declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32) nounwind268 269; CHECK: llvm_mips_clei_u_d_test:270; CHECK: ld.d271; CHECK: clei_u.d272; CHECK: st.d273; CHECK: .size llvm_mips_clei_u_d_test274;275@llvm_mips_clti_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16276@llvm_mips_clti_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16277@llvm_mips_clti_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16278 279define void @llvm_mips_clti_s_b_test() nounwind {280entry:281 %0 = load <16 x i8>, ptr @llvm_mips_clti_s_b_ARG1282 %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14)283 store <16 x i8> %1, ptr @llvm_mips_clti_s_b_RES1284 %2 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 -14)285 store <16 x i8> %2, ptr @llvm_mips_clti_s_b_RES2286 ret void287}288 289declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind290 291; CHECK: llvm_mips_clti_s_b_test:292; CHECK: ld.b [[RS:\$w[0-9]+]]293; CHECK: clti_s.b [[RD1:\$w[0-9]]], [[RS]], 14294; CHECK: st.b [[RD1]]295; CHECK: clti_s.b [[RD2:\$w[0-9]]], [[RS]], -14296; CHECK: st.b [[RD2]]297; CHECK: .size llvm_mips_clti_s_b_test298;299@llvm_mips_clti_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16300@llvm_mips_clti_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16301@llvm_mips_clti_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16302 303define void @llvm_mips_clti_s_h_test() nounwind {304entry:305 %0 = load <8 x i16>, ptr @llvm_mips_clti_s_h_ARG1306 %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14)307 store <8 x i16> %1, ptr @llvm_mips_clti_s_h_RES1308 %2 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 -14)309 store <8 x i16> %2, ptr @llvm_mips_clti_s_h_RES2310 ret void311}312 313declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind314 315; CHECK: llvm_mips_clti_s_h_test:316; CHECK: ld.h [[RS:\$w[0-9]+]]317; CHECK: clti_s.h [[RD1:\$w[0-9]]], [[RS]], 14318; CHECK: st.h [[RD1]]319; CHECK: clti_s.h [[RD2:\$w[0-9]]], [[RS]], -14320; CHECK: st.h [[RD2]]321; CHECK: .size llvm_mips_clti_s_h_test322;323@llvm_mips_clti_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16324@llvm_mips_clti_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16325@llvm_mips_clti_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16326 327define void @llvm_mips_clti_s_w_test() nounwind {328entry:329 %0 = load <4 x i32>, ptr @llvm_mips_clti_s_w_ARG1330 %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14)331 store <4 x i32> %1, ptr @llvm_mips_clti_s_w_RES1332 %2 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 -14)333 store <4 x i32> %2, ptr @llvm_mips_clti_s_w_RES2334 ret void335}336 337declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind338 339; CHECK: llvm_mips_clti_s_w_test:340; CHECK: ld.w [[RS:\$w[0-9]+]]341; CHECK: clti_s.w [[RD1:\$w[0-9]]], [[RS]], 14342; CHECK: st.w [[RD1]]343; CHECK: clti_s.w [[RD2:\$w[0-9]]], [[RS]], -14344; CHECK: st.w [[RD2]]345; CHECK: .size llvm_mips_clti_s_w_test346;347@llvm_mips_clti_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16348@llvm_mips_clti_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16349@llvm_mips_clti_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16350 351define void @llvm_mips_clti_s_d_test() nounwind {352entry:353 %0 = load <2 x i64>, ptr @llvm_mips_clti_s_d_ARG1354 %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14)355 store <2 x i64> %1, ptr @llvm_mips_clti_s_d_RES1356 %2 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 -14)357 store <2 x i64> %2, ptr @llvm_mips_clti_s_d_RES2358 ret void359}360 361declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind362 363; CHECK: llvm_mips_clti_s_d_test:364; CHECK: ld.d [[RS:\$w[0-9]+]]365; CHECK: clti_s.d [[RD1:\$w[0-9]]], [[RS]], 14366; CHECK: st.d [[RD1]]367; CHECK: clti_s.d [[RD2:\$w[0-9]]], [[RS]], -14368; CHECK: st.d [[RD2]]369; CHECK: .size llvm_mips_clti_s_d_test370;371@llvm_mips_clti_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16372@llvm_mips_clti_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16373 374define void @llvm_mips_clti_u_b_test() nounwind {375entry:376 %0 = load <16 x i8>, ptr @llvm_mips_clti_u_b_ARG1377 %1 = tail call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %0, i32 14)378 store <16 x i8> %1, ptr @llvm_mips_clti_u_b_RES379 ret void380}381 382declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32) nounwind383 384; CHECK: llvm_mips_clti_u_b_test:385; CHECK: ld.b386; CHECK: clti_u.b387; CHECK: st.b388; CHECK: .size llvm_mips_clti_u_b_test389;390@llvm_mips_clti_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16391@llvm_mips_clti_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16392 393define void @llvm_mips_clti_u_h_test() nounwind {394entry:395 %0 = load <8 x i16>, ptr @llvm_mips_clti_u_h_ARG1396 %1 = tail call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %0, i32 14)397 store <8 x i16> %1, ptr @llvm_mips_clti_u_h_RES398 ret void399}400 401declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32) nounwind402 403; CHECK: llvm_mips_clti_u_h_test:404; CHECK: ld.h405; CHECK: clti_u.h406; CHECK: st.h407; CHECK: .size llvm_mips_clti_u_h_test408;409@llvm_mips_clti_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16410@llvm_mips_clti_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16411 412define void @llvm_mips_clti_u_w_test() nounwind {413entry:414 %0 = load <4 x i32>, ptr @llvm_mips_clti_u_w_ARG1415 %1 = tail call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %0, i32 14)416 store <4 x i32> %1, ptr @llvm_mips_clti_u_w_RES417 ret void418}419 420declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32) nounwind421 422; CHECK: llvm_mips_clti_u_w_test:423; CHECK: ld.w424; CHECK: clti_u.w425; CHECK: st.w426; CHECK: .size llvm_mips_clti_u_w_test427;428@llvm_mips_clti_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16429@llvm_mips_clti_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16430 431define void @llvm_mips_clti_u_d_test() nounwind {432entry:433 %0 = load <2 x i64>, ptr @llvm_mips_clti_u_d_ARG1434 %1 = tail call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %0, i32 14)435 store <2 x i64> %1, ptr @llvm_mips_clti_u_d_RES436 ret void437}438 439declare <2 x i64> @llvm.mips.clti.u.d(<2 x i64>, i32) nounwind440 441; CHECK: llvm_mips_clti_u_d_test:442; CHECK: ld.d443; CHECK: clti_u.d444; CHECK: st.d445; CHECK: .size llvm_mips_clti_u_d_test446;447