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1; Test the MSA intrinsics that are encoded with the I5 instruction format.2; There are lots of these so this covers those beginning with 'm'3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_maxi_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 169@llvm_mips_maxi_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_maxi_s_b_test() nounwind {12entry:13 %0 = load <16 x i8>, ptr @llvm_mips_maxi_s_b_ARG114 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)15 store <16 x i8> %1, ptr @llvm_mips_maxi_s_b_RES116 %2 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 -14)17 store <16 x i8> %2, ptr @llvm_mips_maxi_s_b_RES218 ret void19}20 21declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind22 23; CHECK: llvm_mips_maxi_s_b_test:24; CHECK: ld.b [[RS:\$w[0-9]+]]25; CHECK: maxi_s.b [[RD1:\$w[0-9]]], [[RS]], 1426; CHECK: st.b [[RD1]]27; CHECK: maxi_s.b [[RD2:\$w[0-9]]], [[RS]], -1428; CHECK: st.b [[RD2]]29; CHECK: .size llvm_mips_maxi_s_b_test30;31@llvm_mips_maxi_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1632@llvm_mips_maxi_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1633@llvm_mips_maxi_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1634 35define void @llvm_mips_maxi_s_h_test() nounwind {36entry:37 %0 = load <8 x i16>, ptr @llvm_mips_maxi_s_h_ARG138 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14)39 store <8 x i16> %1, ptr @llvm_mips_maxi_s_h_RES140 %2 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 -14)41 store <8 x i16> %2, ptr @llvm_mips_maxi_s_h_RES242 ret void43}44 45declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind46 47; CHECK: llvm_mips_maxi_s_h_test:48; CHECK: ld.h [[RS:\$w[0-9]+]]49; CHECK: maxi_s.h [[RD1:\$w[0-9]]], [[RS]], 1450; CHECK: st.h [[RD1]]51; CHECK: maxi_s.h [[RD2:\$w[0-9]]], [[RS]], -1452; CHECK: st.h [[RD2]]53; CHECK: .size llvm_mips_maxi_s_h_test54;55@llvm_mips_maxi_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1656@llvm_mips_maxi_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1657@llvm_mips_maxi_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1658 59define void @llvm_mips_maxi_s_w_test() nounwind {60entry:61 %0 = load <4 x i32>, ptr @llvm_mips_maxi_s_w_ARG162 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14)63 store <4 x i32> %1, ptr @llvm_mips_maxi_s_w_RES164 %2 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 -14)65 store <4 x i32> %2, ptr @llvm_mips_maxi_s_w_RES266 ret void67}68 69declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind70 71; CHECK: llvm_mips_maxi_s_w_test:72; CHECK: ld.w [[RS:\$w[0-9]+]]73; CHECK: maxi_s.w [[RD1:\$w[0-9]]], [[RS]], 1474; CHECK: st.w [[RD1]]75; CHECK: maxi_s.w [[RD2:\$w[0-9]]], [[RS]], -1476; CHECK: st.w [[RD2]]77; CHECK: .size llvm_mips_maxi_s_w_test78;79@llvm_mips_maxi_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1680@llvm_mips_maxi_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 1681@llvm_mips_maxi_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 1682 83define void @llvm_mips_maxi_s_d_test() nounwind {84entry:85 %0 = load <2 x i64>, ptr @llvm_mips_maxi_s_d_ARG186 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14)87 store <2 x i64> %1, ptr @llvm_mips_maxi_s_d_RES188 %2 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 -14)89 store <2 x i64> %2, ptr @llvm_mips_maxi_s_d_RES290 ret void91}92 93declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind94 95; CHECK: llvm_mips_maxi_s_d_test:96; CHECK: ld.d [[RS:\$w[0-9]+]]97; CHECK: maxi_s.d [[RD1:\$w[0-9]]], [[RS]], 1498; CHECK: st.d [[RD1]]99; CHECK: maxi_s.d [[RD2:\$w[0-9]]], [[RS]], -14100; CHECK: st.d [[RD2]]101; CHECK: .size llvm_mips_maxi_s_d_test102;103@llvm_mips_maxi_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16104@llvm_mips_maxi_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16105 106define void @llvm_mips_maxi_u_b_test() nounwind {107entry:108 %0 = load <16 x i8>, ptr @llvm_mips_maxi_u_b_ARG1109 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14)110 store <16 x i8> %1, ptr @llvm_mips_maxi_u_b_RES111 ret void112}113 114declare <16 x i8> @llvm.mips.maxi.u.b(<16 x i8>, i32) nounwind115 116; CHECK: llvm_mips_maxi_u_b_test:117; CHECK: ld.b118; CHECK: maxi_u.b119; CHECK: st.b120; CHECK: .size llvm_mips_maxi_u_b_test121;122@llvm_mips_maxi_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16123@llvm_mips_maxi_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16124 125define void @llvm_mips_maxi_u_h_test() nounwind {126entry:127 %0 = load <8 x i16>, ptr @llvm_mips_maxi_u_h_ARG1128 %1 = tail call <8 x i16> @llvm.mips.maxi.u.h(<8 x i16> %0, i32 14)129 store <8 x i16> %1, ptr @llvm_mips_maxi_u_h_RES130 ret void131}132 133declare <8 x i16> @llvm.mips.maxi.u.h(<8 x i16>, i32) nounwind134 135; CHECK: llvm_mips_maxi_u_h_test:136; CHECK: ld.h137; CHECK: maxi_u.h138; CHECK: st.h139; CHECK: .size llvm_mips_maxi_u_h_test140;141@llvm_mips_maxi_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16142@llvm_mips_maxi_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16143 144define void @llvm_mips_maxi_u_w_test() nounwind {145entry:146 %0 = load <4 x i32>, ptr @llvm_mips_maxi_u_w_ARG1147 %1 = tail call <4 x i32> @llvm.mips.maxi.u.w(<4 x i32> %0, i32 14)148 store <4 x i32> %1, ptr @llvm_mips_maxi_u_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.maxi.u.w(<4 x i32>, i32) nounwind153 154; CHECK: llvm_mips_maxi_u_w_test:155; CHECK: ld.w156; CHECK: maxi_u.w157; CHECK: st.w158; CHECK: .size llvm_mips_maxi_u_w_test159;160@llvm_mips_maxi_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16161@llvm_mips_maxi_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16162 163define void @llvm_mips_maxi_u_d_test() nounwind {164entry:165 %0 = load <2 x i64>, ptr @llvm_mips_maxi_u_d_ARG1166 %1 = tail call <2 x i64> @llvm.mips.maxi.u.d(<2 x i64> %0, i32 14)167 store <2 x i64> %1, ptr @llvm_mips_maxi_u_d_RES168 ret void169}170 171declare <2 x i64> @llvm.mips.maxi.u.d(<2 x i64>, i32) nounwind172 173; CHECK: llvm_mips_maxi_u_d_test:174; CHECK: ld.d175; CHECK: maxi_u.d176; CHECK: st.d177; CHECK: .size llvm_mips_maxi_u_d_test178;179@llvm_mips_mini_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16180@llvm_mips_mini_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16181@llvm_mips_mini_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16182 183define void @llvm_mips_mini_s_b_test() nounwind {184entry:185 %0 = load <16 x i8>, ptr @llvm_mips_mini_s_b_ARG1186 %1 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 14)187 store <16 x i8> %1, ptr @llvm_mips_mini_s_b_RES1188 %2 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 -14)189 store <16 x i8> %2, ptr @llvm_mips_mini_s_b_RES2190 ret void191}192 193declare <16 x i8> @llvm.mips.mini.s.b(<16 x i8>, i32) nounwind194 195; CHECK: llvm_mips_mini_s_b_test:196; CHECK: ld.b [[RS:\$w[0-9]+]]197; CHECK: mini_s.b [[RD1:\$w[0-9]]], [[RS]], 14198; CHECK: st.b [[RD1]]199; CHECK: mini_s.b [[RD2:\$w[0-9]]], [[RS]], -14200; CHECK: st.b [[RD2]]201; CHECK: .size llvm_mips_mini_s_b_test202;203@llvm_mips_mini_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16204@llvm_mips_mini_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16205@llvm_mips_mini_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16206 207define void @llvm_mips_mini_s_h_test() nounwind {208entry:209 %0 = load <8 x i16>, ptr @llvm_mips_mini_s_h_ARG1210 %1 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 14)211 store <8 x i16> %1, ptr @llvm_mips_mini_s_h_RES1212 %2 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 -14)213 store <8 x i16> %2, ptr @llvm_mips_mini_s_h_RES2214 ret void215}216 217declare <8 x i16> @llvm.mips.mini.s.h(<8 x i16>, i32) nounwind218 219; CHECK: llvm_mips_mini_s_h_test:220; CHECK: ld.h [[RS:\$w[0-9]+]]221; CHECK: mini_s.h [[RD1:\$w[0-9]]], [[RS]], 14222; CHECK: st.h [[RD1]]223; CHECK: mini_s.h [[RD2:\$w[0-9]]], [[RS]], -14224; CHECK: st.h [[RD2]]225; CHECK: .size llvm_mips_mini_s_h_test226;227@llvm_mips_mini_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16228@llvm_mips_mini_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16229@llvm_mips_mini_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16230 231define void @llvm_mips_mini_s_w_test() nounwind {232entry:233 %0 = load <4 x i32>, ptr @llvm_mips_mini_s_w_ARG1234 %1 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 14)235 store <4 x i32> %1, ptr @llvm_mips_mini_s_w_RES1236 %2 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 -14)237 store <4 x i32> %2, ptr @llvm_mips_mini_s_w_RES2238 ret void239}240 241declare <4 x i32> @llvm.mips.mini.s.w(<4 x i32>, i32) nounwind242 243; CHECK: llvm_mips_mini_s_w_test:244; CHECK: ld.w [[RS:\$w[0-9]+]]245; CHECK: mini_s.w [[RD1:\$w[0-9]]], [[RS]], 14246; CHECK: st.w [[RD1]]247; CHECK: mini_s.w [[RD2:\$w[0-9]]], [[RS]], -14248; CHECK: st.w [[RD2]]249; CHECK: .size llvm_mips_mini_s_w_test250;251@llvm_mips_mini_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16252@llvm_mips_mini_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16253@llvm_mips_mini_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16254 255define void @llvm_mips_mini_s_d_test() nounwind {256entry:257 %0 = load <2 x i64>, ptr @llvm_mips_mini_s_d_ARG1258 %1 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 14)259 store <2 x i64> %1, ptr @llvm_mips_mini_s_d_RES1260 %2 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 -14)261 store <2 x i64> %2, ptr @llvm_mips_mini_s_d_RES2262 ret void263}264 265declare <2 x i64> @llvm.mips.mini.s.d(<2 x i64>, i32) nounwind266 267; CHECK: llvm_mips_mini_s_d_test:268; CHECK: ld.d [[RS:\$w[0-9]+]]269; CHECK: mini_s.d [[RD1:\$w[0-9]]], [[RS]], 14270; CHECK: st.d [[RD1]]271; CHECK: mini_s.d [[RD2:\$w[0-9]]], [[RS]], -14272; CHECK: st.d [[RD2]]273; CHECK: .size llvm_mips_mini_s_d_test274;275@llvm_mips_mini_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16276@llvm_mips_mini_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16277 278define void @llvm_mips_mini_u_b_test() nounwind {279entry:280 %0 = load <16 x i8>, ptr @llvm_mips_mini_u_b_ARG1281 %1 = tail call <16 x i8> @llvm.mips.mini.u.b(<16 x i8> %0, i32 14)282 store <16 x i8> %1, ptr @llvm_mips_mini_u_b_RES283 ret void284}285 286declare <16 x i8> @llvm.mips.mini.u.b(<16 x i8>, i32) nounwind287 288; CHECK: llvm_mips_mini_u_b_test:289; CHECK: ld.b290; CHECK: mini_u.b291; CHECK: st.b292; CHECK: .size llvm_mips_mini_u_b_test293;294@llvm_mips_mini_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16295@llvm_mips_mini_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16296 297define void @llvm_mips_mini_u_h_test() nounwind {298entry:299 %0 = load <8 x i16>, ptr @llvm_mips_mini_u_h_ARG1300 %1 = tail call <8 x i16> @llvm.mips.mini.u.h(<8 x i16> %0, i32 14)301 store <8 x i16> %1, ptr @llvm_mips_mini_u_h_RES302 ret void303}304 305declare <8 x i16> @llvm.mips.mini.u.h(<8 x i16>, i32) nounwind306 307; CHECK: llvm_mips_mini_u_h_test:308; CHECK: ld.h309; CHECK: mini_u.h310; CHECK: st.h311; CHECK: .size llvm_mips_mini_u_h_test312;313@llvm_mips_mini_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16314@llvm_mips_mini_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16315 316define void @llvm_mips_mini_u_w_test() nounwind {317entry:318 %0 = load <4 x i32>, ptr @llvm_mips_mini_u_w_ARG1319 %1 = tail call <4 x i32> @llvm.mips.mini.u.w(<4 x i32> %0, i32 14)320 store <4 x i32> %1, ptr @llvm_mips_mini_u_w_RES321 ret void322}323 324declare <4 x i32> @llvm.mips.mini.u.w(<4 x i32>, i32) nounwind325 326; CHECK: llvm_mips_mini_u_w_test:327; CHECK: ld.w328; CHECK: mini_u.w329; CHECK: st.w330; CHECK: .size llvm_mips_mini_u_w_test331;332@llvm_mips_mini_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16333@llvm_mips_mini_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16334 335define void @llvm_mips_mini_u_d_test() nounwind {336entry:337 %0 = load <2 x i64>, ptr @llvm_mips_mini_u_d_ARG1338 %1 = tail call <2 x i64> @llvm.mips.mini.u.d(<2 x i64> %0, i32 14)339 store <2 x i64> %1, ptr @llvm_mips_mini_u_d_RES340 ret void341}342 343declare <2 x i64> @llvm.mips.mini.u.d(<2 x i64>, i32) nounwind344 345; CHECK: llvm_mips_mini_u_d_test:346; CHECK: ld.d347; CHECK: mini_u.d348; CHECK: st.d349; CHECK: .size llvm_mips_mini_u_d_test350;351