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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s3; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s4 5; Test the MSA intrinsics that are encoded with the I5 instruction format.6; There are lots of these so this covers those beginning with 's'7 8@llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 169@llvm_mips_subvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1610 11define void @llvm_mips_subvi_b_test() nounwind {12; CHECK-LABEL: llvm_mips_subvi_b_test:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_b_RES)15; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_b_RES)16; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_b_ARG1)17; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1)18; CHECK-NEXT: ld.b $w0, 0($2)19; CHECK-NEXT: subvi.b $w0, $w0, 1420; CHECK-NEXT: jr $ra21; CHECK-NEXT: st.b $w0, 0($1)22entry:23 %0 = load <16 x i8>, ptr @llvm_mips_subvi_b_ARG124 %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14)25 store <16 x i8> %1, ptr @llvm_mips_subvi_b_RES26 ret void27}28 29declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind30 31@llvm_mips_subvi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1632@llvm_mips_subvi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1633 34define void @llvm_mips_subvi_h_test() nounwind {35; CHECK-LABEL: llvm_mips_subvi_h_test:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_h_RES)38; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_h_RES)39; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_h_ARG1)40; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1)41; CHECK-NEXT: ld.h $w0, 0($2)42; CHECK-NEXT: subvi.h $w0, $w0, 1443; CHECK-NEXT: jr $ra44; CHECK-NEXT: st.h $w0, 0($1)45entry:46 %0 = load <8 x i16>, ptr @llvm_mips_subvi_h_ARG147 %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14)48 store <8 x i16> %1, ptr @llvm_mips_subvi_h_RES49 ret void50}51 52declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind53 54@llvm_mips_subvi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1655@llvm_mips_subvi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1656 57define void @llvm_mips_subvi_w_test() nounwind {58; CHECK-LABEL: llvm_mips_subvi_w_test:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_w_RES)61; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_w_RES)62; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_w_ARG1)63; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1)64; CHECK-NEXT: ld.w $w0, 0($2)65; CHECK-NEXT: subvi.w $w0, $w0, 1466; CHECK-NEXT: jr $ra67; CHECK-NEXT: st.w $w0, 0($1)68entry:69 %0 = load <4 x i32>, ptr @llvm_mips_subvi_w_ARG170 %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14)71 store <4 x i32> %1, ptr @llvm_mips_subvi_w_RES72 ret void73}74 75declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind76 77@llvm_mips_subvi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1678@llvm_mips_subvi_d_RES = global <2 x i64> <i64 0, i64 0>, align 1679 80define void @llvm_mips_subvi_d_test() nounwind {81; CHECK-LABEL: llvm_mips_subvi_d_test:82; CHECK: # %bb.0: # %entry83; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_d_RES)84; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_d_RES)85; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_d_ARG1)86; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1)87; CHECK-NEXT: ld.d $w0, 0($2)88; CHECK-NEXT: subvi.d $w0, $w0, 1489; CHECK-NEXT: jr $ra90; CHECK-NEXT: st.d $w0, 0($1)91entry:92 %0 = load <2 x i64>, ptr @llvm_mips_subvi_d_ARG193 %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14)94 store <2 x i64> %1, ptr @llvm_mips_subvi_d_RES95 ret void96}97 98declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32) nounwind99