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1; Test the MSA intrinsics that are encoded with the I5 instruction format and2; are loads or stores.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 168@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 169 10define void @llvm_mips_ld_b_test() nounwind {11entry:12 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 16)13 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES14 ret void15}16 17declare <16 x i8> @llvm.mips.ld.b(ptr, i32) nounwind18 19; CHECK: llvm_mips_ld_b_test:20; CHECK: ld.b [[R1:\$w[0-9]+]], 16(21; CHECK: st.b22; CHECK: .size llvm_mips_ld_b_test23;24 25define void @llvm_mips_ld_b_unaligned_test() nounwind {26entry:27 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 9)28 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES29 ret void30}31 32; CHECK: llvm_mips_ld_b_unaligned_test:33; CHECK: ld.b [[R1:\$w[0-9]+]], 9(34; CHECK: st.b35; CHECK: .size llvm_mips_ld_b_unaligned_test36;37 38define void @llvm_mips_ld_b_valid_range_tests() nounwind {39entry:40 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 -512)41 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES42 %1 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 511)43 store <16 x i8> %1, ptr @llvm_mips_ld_b_RES44 ret void45}46 47; CHECK: llvm_mips_ld_b_valid_range_tests:48; CHECK: ld.b [[R1:\$w[0-9]+]], -512(49; CHECK: st.b50; CHECK: ld.b [[R1:\$w[0-9]+]], 511(51; CHECK: st.b52; CHECK: .size llvm_mips_ld_b_valid_range_tests53;54 55define void @llvm_mips_ld_b_invalid_range_tests() nounwind {56entry:57 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 -513)58 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES59 %1 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 512)60 store <16 x i8> %1, ptr @llvm_mips_ld_b_RES61 ret void62}63 64; CHECK: llvm_mips_ld_b_invalid_range_tests:65; CHECK: addiu $3, $2, -51366; CHECK: ld.b [[R1:\$w[0-9]+]], 0(67; CHECK: st.b68; CHECK: addiu $2, $2, 51269; CHECK: ld.b [[R1:\$w[0-9]+]], 0(70; CHECK: st.b71; CHECK: .size llvm_mips_ld_b_invalid_range_tests72;73 74@llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1675@llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1676 77define void @llvm_mips_ld_h_test() nounwind {78entry:79 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 16)80 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES81 ret void82}83 84declare <8 x i16> @llvm.mips.ld.h(ptr, i32) nounwind85 86; CHECK: llvm_mips_ld_h_test:87; CHECK: ld.h [[R1:\$w[0-9]+]], 16(88; CHECK: st.h89; CHECK: .size llvm_mips_ld_h_test90;91 92define void @llvm_mips_ld_h_unaligned_test() nounwind {93entry:94 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 9)95 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES96 ret void97}98 99; CHECK: llvm_mips_ld_h_unaligned_test:100; CHECK: addiu $2, $2, 9101; CHECK: ld.h [[R1:\$w[0-9]+]], 0($2)102; CHECK: st.h103; CHECK: .size llvm_mips_ld_h_unaligned_test104;105 106define void @llvm_mips_ld_h_valid_range_tests() nounwind {107entry:108 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 -1024)109 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES110 %1 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 1022)111 store <8 x i16> %1, ptr @llvm_mips_ld_h_RES112 ret void113}114 115; CHECK: llvm_mips_ld_h_valid_range_tests:116; CHECK: ld.h [[R1:\$w[0-9]+]], -1024(117; CHECK: st.h118; CHECK: ld.h [[R1:\$w[0-9]+]], 1022(119; CHECK: st.h120; CHECK: .size llvm_mips_ld_h_valid_range_tests121;122 123define void @llvm_mips_ld_h_invalid_range_tests() nounwind {124entry:125 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 -1026)126 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES127 %1 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 1024)128 store <8 x i16> %1, ptr @llvm_mips_ld_h_RES129 ret void130}131 132; CHECK: llvm_mips_ld_h_invalid_range_tests:133; CHECK: addiu $3, $2, -1026134; CHECK: ld.h [[R1:\$w[0-9]+]], 0(135; CHECK: st.h136; CHECK: addiu $2, $2, 1024137; CHECK: ld.h [[R1:\$w[0-9]+]], 0(138; CHECK: st.h139; CHECK: .size llvm_mips_ld_h_invalid_range_tests140;141 142@llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16143@llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16144 145define void @llvm_mips_ld_w_test() nounwind {146entry:147 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 16)148 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES149 ret void150}151 152declare <4 x i32> @llvm.mips.ld.w(ptr, i32) nounwind153 154; CHECK: llvm_mips_ld_w_test:155; CHECK: ld.w [[R1:\$w[0-9]+]], 16(156; CHECK: st.w157; CHECK: .size llvm_mips_ld_w_test158;159@llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16160@llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16161 162define void @llvm_mips_ld_w_unaligned_test() nounwind {163entry:164 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 9)165 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES166 ret void167}168 169; CHECK: llvm_mips_ld_w_unaligned_test:170; CHECK: addiu $2, $2, 9171; CHECK: ld.w [[R1:\$w[0-9]+]], 0($2)172; CHECK: st.w173; CHECK: .size llvm_mips_ld_w_unaligned_test174;175 176define void @llvm_mips_ld_w_valid_range_tests() nounwind {177entry:178 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 -2048)179 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES180 %1 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 2044)181 store <4 x i32> %1, ptr @llvm_mips_ld_w_RES182 ret void183}184 185; CHECK: llvm_mips_ld_w_valid_range_tests:186; CHECK: ld.w [[R1:\$w[0-9]+]], -2048(187; CHECK: st.w188; CHECK: ld.w [[R1:\$w[0-9]+]], 2044(189; CHECK: st.w190; CHECK: .size llvm_mips_ld_w_valid_range_tests191;192 193define void @llvm_mips_ld_w_invalid_range_tests() nounwind {194entry:195 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 -2052)196 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES197 %1 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 2048)198 store <4 x i32> %1, ptr @llvm_mips_ld_w_RES199 ret void200}201 202; CHECK: llvm_mips_ld_w_invalid_range_tests:203; CHECK: addiu $3, $2, -2052204; CHECK: ld.w [[R1:\$w[0-9]+]], 0(205; CHECK: st.w206; CHECK: addiu $2, $2, 2048207; CHECK: ld.w [[R1:\$w[0-9]+]], 0(208; CHECK: st.w209; CHECK: .size llvm_mips_ld_w_invalid_range_tests210;211 212define void @llvm_mips_ld_d_test() nounwind {213entry:214 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 16)215 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES216 ret void217}218 219declare <2 x i64> @llvm.mips.ld.d(ptr, i32) nounwind220 221; CHECK: llvm_mips_ld_d_test:222; CHECK: ld.d [[R1:\$w[0-9]+]], 16(223; CHECK: st.d224; CHECK: .size llvm_mips_ld_d_test225;226 227define void @llvm_mips_ld_d_unaligned_test() nounwind {228entry:229 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 9)230 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES231 ret void232}233 234; CHECK: llvm_mips_ld_d_unaligned_test:235; CHECK: addiu $2, $2, 9236; CHECK: ld.d [[R1:\$w[0-9]+]], 0($2)237; CHECK: st.d238; CHECK: .size llvm_mips_ld_d_unaligned_test239;240 241define void @llvm_mips_ld_d_valid_range_tests() nounwind {242entry:243 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 -4096)244 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES245 %1 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 4088)246 store <2 x i64> %1, ptr @llvm_mips_ld_d_RES247 ret void248}249 250; CHECK: llvm_mips_ld_d_valid_range_tests:251; CHECK: ld.d [[R1:\$w[0-9]+]], -4096(252; CHECK: st.d253; CHECK: ld.d [[R1:\$w[0-9]+]], 4088(254; CHECK: st.d255; CHECK: .size llvm_mips_ld_d_valid_range_tests256;257 258define void @llvm_mips_ld_d_invalid_range_tests() nounwind {259entry:260 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 -4104)261 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES262 %1 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 4096)263 store <2 x i64> %1, ptr @llvm_mips_ld_d_RES264 ret void265}266 267; CHECK: llvm_mips_ld_d_invalid_range_tests:268; CHECK: addiu $3, $2, -4104269; CHECK: ld.d [[R1:\$w[0-9]+]], 0(270; CHECK: st.d271; CHECK: addiu $2, $2, 4096272; CHECK: ld.d [[R1:\$w[0-9]+]], 0(273; CHECK: st.d274; CHECK: .size llvm_mips_ld_d_invalid_range_tests275;276 277 278 279@llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16280@llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16281 282define void @llvm_mips_st_b_test() nounwind {283entry:284 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG285 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 16)286 ret void287}288 289declare void @llvm.mips.st.b(<16 x i8>, ptr, i32) nounwind290 291; CHECK: llvm_mips_st_b_test:292; CHECK: ld.b293; CHECK: st.b [[R1:\$w[0-9]+]], 16(294; CHECK: .size llvm_mips_st_b_test295;296 297define void @llvm_mips_st_b_unaligned_test() nounwind {298entry:299 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG300 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 9)301 ret void302}303 304; CHECK: llvm_mips_st_b_unaligned_test:305; CHECK: ld.b306; CHECK: st.b [[R1:\$w[0-9]+]], 9(307; CHECK: .size llvm_mips_st_b_unaligned_test308;309 310define void @llvm_mips_st_b_valid_range_tests() nounwind {311entry:312 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG313 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 -512)314 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 511)315 ret void316}317 318; CHECK: llvm_mips_st_b_valid_range_tests:319; CHECK: ld.b320; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512(321; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511(322; CHECK: .size llvm_mips_st_b_valid_range_tests323;324 325define void @llvm_mips_st_b_invalid_range_tests() nounwind {326entry:327 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG328 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 -513)329 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 512)330 ret void331}332 333; CHECK: llvm_mips_st_b_invalid_range_tests:334; CHECK: addiu $2, $1, 512335; CHECK: ld.b336; CHECK: st.b [[R1:\$w[0-9]+]], 0(337; CHECK: addiu $1, $1, -513338; CHECK: st.b [[R1:\$w[0-9]+]], 0(339; CHECK: .size llvm_mips_st_b_invalid_range_tests340;341 342@llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16343@llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16344 345define void @llvm_mips_st_h_test() nounwind {346entry:347 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG348 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 16)349 ret void350}351 352declare void @llvm.mips.st.h(<8 x i16>, ptr, i32) nounwind353 354; CHECK: llvm_mips_st_h_test:355; CHECK: ld.h356; CHECK: st.h [[R1:\$w[0-9]+]], 16(357; CHECK: .size llvm_mips_st_h_test358;359 360define void @llvm_mips_st_h_unaligned_test() nounwind {361entry:362 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG363 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 9)364 ret void365}366 367; CHECK: llvm_mips_st_h_unaligned_test:368; CHECK: addiu $1, $1, 9369; CHECK: ld.h370; CHECK: st.h [[R1:\$w[0-9]+]], 0($1)371; CHECK: .size llvm_mips_st_h_unaligned_test372;373 374define void @llvm_mips_st_h_valid_range_tests() nounwind {375entry:376 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG377 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 -1024)378 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 1022)379 ret void380}381 382; CHECK: llvm_mips_st_h_valid_range_tests:383; CHECK: ld.h384; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024(385; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022(386; CHECK: .size llvm_mips_st_h_valid_range_tests387;388 389define void @llvm_mips_st_h_invalid_range_tests() nounwind {390entry:391 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG392 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 -1026)393 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 1024)394 ret void395}396 397; CHECK: llvm_mips_st_h_invalid_range_tests:398; CHECK: addiu $2, $1, 1024399; CHECK: ld.h400; CHECK: st.h [[R1:\$w[0-9]+]], 0(401; CHECK: addiu $1, $1, -1026402; CHECK: st.h [[R1:\$w[0-9]+]], 0(403; CHECK: .size llvm_mips_st_h_invalid_range_tests404;405 406@llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16407@llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16408 409define void @llvm_mips_st_w_test() nounwind {410entry:411 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG412 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 16)413 ret void414}415 416declare void @llvm.mips.st.w(<4 x i32>, ptr, i32) nounwind417 418; CHECK: llvm_mips_st_w_test:419; CHECK: ld.w420; CHECK: st.w [[R1:\$w[0-9]+]], 16(421; CHECK: .size llvm_mips_st_w_test422;423 424define void @llvm_mips_st_w_unaligned_test() nounwind {425entry:426 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG427 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 9)428 ret void429}430 431; CHECK: llvm_mips_st_w_unaligned_test:432; CHECK: addiu $1, $1, 9433; CHECK: ld.w434; CHECK: st.w [[R1:\$w[0-9]+]], 0($1)435; CHECK: .size llvm_mips_st_w_unaligned_test436;437 438define void @llvm_mips_st_w_valid_range_tests() nounwind {439entry:440 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG441 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 -2048)442 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 2044)443 ret void444}445 446; CHECK: llvm_mips_st_w_valid_range_tests:447; CHECK: ld.w448; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048(449; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044(450; CHECK: .size llvm_mips_st_w_valid_range_tests451;452 453define void @llvm_mips_st_w_invalid_range_tests() nounwind {454entry:455 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG456 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 -2052)457 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 2048)458 ret void459}460 461; CHECK: llvm_mips_st_w_invalid_range_tests:462; CHECK: addiu $2, $1, 2048463; CHECK: ld.w464; CHECK: st.w [[R1:\$w[0-9]+]], 0(465; CHECK: addiu $1, $1, -2052466; CHECK: st.w [[R1:\$w[0-9]+]], 0(467; CHECK: .size llvm_mips_st_w_invalid_range_tests468;469 470@llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16471@llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16472 473define void @llvm_mips_st_d_test() nounwind {474entry:475 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG476 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 16)477 ret void478}479 480declare void @llvm.mips.st.d(<2 x i64>, ptr, i32) nounwind481 482; CHECK: llvm_mips_st_d_test:483; CHECK: ld.d484; CHECK: st.d [[R1:\$w[0-9]+]], 16(485; CHECK: .size llvm_mips_st_d_test486;487 488define void @llvm_mips_st_d_unaligned_test() nounwind {489entry:490 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG491 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 9)492 ret void493}494 495; CHECK: llvm_mips_st_d_unaligned_test:496; CHECK: addiu $1, $1, 9497; CHECK: ld.d498; CHECK: st.d [[R1:\$w[0-9]+]], 0($1)499; CHECK: .size llvm_mips_st_d_unaligned_test500;501 502define void @llvm_mips_st_d_valid_range_tests() nounwind {503entry:504 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG505 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 -4096)506 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 4088)507 ret void508}509 510; CHECK: llvm_mips_st_d_valid_range_tests:511; CHECK: ld.d512; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096(513; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088(514; CHECK: .size llvm_mips_st_d_valid_range_tests515;516 517define void @llvm_mips_st_d_invalid_range_tests() nounwind {518entry:519 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG520 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 -4104)521 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 4096)522 ret void523}524 525; CHECK: llvm_mips_st_d_invalid_range_tests:526; CHECK: addiu $2, $1, 4096527; CHECK: ld.d528; CHECK: st.d [[R1:\$w[0-9]+]], 0(529; CHECK: addiu $1, $1, -4104530; CHECK: st.d [[R1:\$w[0-9]+]], 0(531; CHECK: .size llvm_mips_st_d_invalid_range_tests532;533