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1; Test the MSA intrinsics that are encoded with the I8 instruction format.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s4; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5 6@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 167@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 168 9define void @llvm_mips_andi_b_test() nounwind {10entry:11 %0 = load <16 x i8>, ptr @llvm_mips_andi_b_ARG112 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)13 store <16 x i8> %1, ptr @llvm_mips_andi_b_RES14 ret void15}16 17declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind18 19; CHECK: llvm_mips_andi_b_test:20; CHECK: ld.b21; CHECK: andi.b22; CHECK: st.b23; CHECK: .size llvm_mips_andi_b_test24 25@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1626@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1627@llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1628 29define void @llvm_mips_bmnzi_b_test() nounwind {30entry:31 %0 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG132 %1 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG233 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)34 store <16 x i8> %2, ptr @llvm_mips_bmnzi_b_RES35 ret void36}37 38declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind39 40; CHECK: llvm_mips_bmnzi_b_test:41; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(42; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(43; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])44; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])45; CHECK-DAG: bmnzi.b [[R3]], [[R4]], 2546; CHECK-DAG: st.b [[R3]], 0(47; CHECK: .size llvm_mips_bmnzi_b_test48 49@llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1650@llvm_mips_bmzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1651@llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1652 53define void @llvm_mips_bmzi_b_test() nounwind {54entry:55 %0 = load <16 x i8>, ptr @llvm_mips_bmzi_b_ARG156 %1 = load <16 x i8>, ptr @llvm_mips_bmzi_b_ARG257 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)58 store <16 x i8> %2, ptr @llvm_mips_bmzi_b_RES59 ret void60}61 62declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind63 64; CHECK: llvm_mips_bmzi_b_test:65; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG1)(66; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG2)(67; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])68; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])69; bmnzi.b is the same as bmzi.b with ws and wd_in swapped70; CHECK-DAG: bmnzi.b [[R4]], [[R3]], 2571; CHECK-DAG: st.b [[R4]], 0(72; CHECK: .size llvm_mips_bmzi_b_test73 74@llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1675@llvm_mips_bseli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1676@llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1677 78define void @llvm_mips_bseli_b_test() nounwind {79entry:80 %0 = load <16 x i8>, ptr @llvm_mips_bseli_b_ARG181 %1 = load <16 x i8>, ptr @llvm_mips_bseli_b_ARG282 %2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25)83 store <16 x i8> %2, ptr @llvm_mips_bseli_b_RES84 ret void85}86 87declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind88 89; CHECK: llvm_mips_bseli_b_test:90; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG1)(91; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG2)(92; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])93; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])94; CHECK-DAG: bseli.b [[R3]], [[R4]], 2595; CHECK-DAG: st.b [[R3]], 0(96; CHECK: .size llvm_mips_bseli_b_test97 98@llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1699@llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16100 101define void @llvm_mips_nori_b_test() nounwind {102entry:103 %0 = load <16 x i8>, ptr @llvm_mips_nori_b_ARG1104 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)105 store <16 x i8> %1, ptr @llvm_mips_nori_b_RES106 ret void107}108 109declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind110 111; CHECK: llvm_mips_nori_b_test:112; CHECK: ld.b113; CHECK: nori.b114; CHECK: st.b115; CHECK: .size llvm_mips_nori_b_test116;117@llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16118@llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16119 120define void @llvm_mips_ori_b_test() nounwind {121entry:122 %0 = load <16 x i8>, ptr @llvm_mips_ori_b_ARG1123 %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)124 store <16 x i8> %1, ptr @llvm_mips_ori_b_RES125 ret void126}127 128declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind129 130; CHECK: llvm_mips_ori_b_test:131; CHECK: ld.b132; CHECK: ori.b133; CHECK: st.b134; CHECK: .size llvm_mips_ori_b_test135;136@llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16137@llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16138 139define void @llvm_mips_shf_b_test() nounwind {140entry:141 %0 = load <16 x i8>, ptr @llvm_mips_shf_b_ARG1142 %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)143 store <16 x i8> %1, ptr @llvm_mips_shf_b_RES144 ret void145}146 147declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind148 149; CHECK: llvm_mips_shf_b_test:150; CHECK: ld.b151; CHECK: shf.b152; CHECK: st.b153; CHECK: .size llvm_mips_shf_b_test154;155@llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16156@llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16157 158define void @llvm_mips_shf_h_test() nounwind {159entry:160 %0 = load <8 x i16>, ptr @llvm_mips_shf_h_ARG1161 %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)162 store <8 x i16> %1, ptr @llvm_mips_shf_h_RES163 ret void164}165 166declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind167 168; CHECK: llvm_mips_shf_h_test:169; CHECK: ld.h170; CHECK: shf.h171; CHECK: st.h172; CHECK: .size llvm_mips_shf_h_test173;174@llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16175@llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16176 177define void @llvm_mips_shf_w_test() nounwind {178entry:179 %0 = load <4 x i32>, ptr @llvm_mips_shf_w_ARG1180 %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)181 store <4 x i32> %1, ptr @llvm_mips_shf_w_RES182 ret void183}184 185declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind186 187; CHECK: llvm_mips_shf_w_test:188; CHECK: ld.w189; CHECK: shf.w190; CHECK: st.w191; CHECK: .size llvm_mips_shf_w_test192;193@llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16194@llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16195 196define void @llvm_mips_xori_b_test() nounwind {197entry:198 %0 = load <16 x i8>, ptr @llvm_mips_xori_b_ARG1199 %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)200 store <16 x i8> %1, ptr @llvm_mips_xori_b_RES201 ret void202}203 204declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind205 206; CHECK: llvm_mips_xori_b_test:207; CHECK: ld.b208; CHECK: xori.b209; CHECK: st.b210; CHECK: .size llvm_mips_xori_b_test211;212