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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \3; RUN: | FileCheck %s -check-prefixes=MSA,MSA324; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \5; RUN: | FileCheck %s -check-prefix=MSA64N326; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \7; RUN: | FileCheck %s -check-prefixes=MSA,MSA64N648 9; Test that the immediate intrinsics don't crash LLVM.10 11; Some of the intrinsics lower to equivalent forms.12 13define void @addvi_b(ptr %ptr) {14; MSA-LABEL: addvi_b:15; MSA: # %bb.0: # %entry16; MSA-NEXT: ld.b $w0, 0($4)17; MSA-NEXT: addvi.b $w0, $w0, 2518; MSA-NEXT: jr $ra19; MSA-NEXT: st.b $w0, 0($4)20;21; MSA64N32-LABEL: addvi_b:22; MSA64N32: # %bb.0: # %entry23; MSA64N32-NEXT: sll $1, $4, 024; MSA64N32-NEXT: ld.b $w0, 0($1)25; MSA64N32-NEXT: addvi.b $w0, $w0, 2526; MSA64N32-NEXT: jr $ra27; MSA64N32-NEXT: st.b $w0, 0($1)28entry:29 %a = load <16 x i8>, ptr %ptr, align 1630 %r = call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %a, i32 25)31 store <16 x i8> %r, ptr %ptr, align 1632 ret void33}34 35define void @andi_b(ptr %ptr) {36; MSA-LABEL: andi_b:37; MSA: # %bb.0: # %entry38; MSA-NEXT: ld.b $w0, 0($4)39; MSA-NEXT: andi.b $w0, $w0, 2540; MSA-NEXT: jr $ra41; MSA-NEXT: st.b $w0, 0($4)42;43; MSA64N32-LABEL: andi_b:44; MSA64N32: # %bb.0: # %entry45; MSA64N32-NEXT: sll $1, $4, 046; MSA64N32-NEXT: ld.b $w0, 0($1)47; MSA64N32-NEXT: andi.b $w0, $w0, 2548; MSA64N32-NEXT: jr $ra49; MSA64N32-NEXT: st.b $w0, 0($1)50entry:51 %a = load <16 x i8>, ptr %ptr, align 1652 %r = call <16 x i8> @llvm.mips.andi.b(<16 x i8> %a, i32 25)53 store <16 x i8> %r, ptr %ptr, align 1654 ret void55}56 57define void @bclri_b(ptr %ptr) {58; MSA-LABEL: bclri_b:59; MSA: # %bb.0: # %entry60; MSA-NEXT: ld.b $w0, 0($4)61; MSA-NEXT: andi.b $w0, $w0, 24762; MSA-NEXT: jr $ra63; MSA-NEXT: st.b $w0, 0($4)64;65; MSA64N32-LABEL: bclri_b:66; MSA64N32: # %bb.0: # %entry67; MSA64N32-NEXT: sll $1, $4, 068; MSA64N32-NEXT: ld.b $w0, 0($1)69; MSA64N32-NEXT: andi.b $w0, $w0, 24770; MSA64N32-NEXT: jr $ra71; MSA64N32-NEXT: st.b $w0, 0($1)72entry:73 %a = load <16 x i8>, ptr %ptr, align 1674 %r = call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %a, i32 3)75 store <16 x i8> %r, ptr %ptr, align 1676 ret void77}78 79define void @binsli_b(ptr %ptr, ptr %ptr2) {80; MSA-LABEL: binsli_b:81; MSA: # %bb.0: # %entry82; MSA-NEXT: ld.b $w0, 0($5)83; MSA-NEXT: ld.b $w1, 0($4)84; MSA-NEXT: binsli.b $w1, $w0, 385; MSA-NEXT: jr $ra86; MSA-NEXT: st.b $w1, 0($4)87;88; MSA64N32-LABEL: binsli_b:89; MSA64N32: # %bb.0: # %entry90; MSA64N32-NEXT: sll $1, $4, 091; MSA64N32-NEXT: sll $2, $5, 092; MSA64N32-NEXT: ld.b $w0, 0($2)93; MSA64N32-NEXT: ld.b $w1, 0($1)94; MSA64N32-NEXT: binsli.b $w1, $w0, 395; MSA64N32-NEXT: jr $ra96; MSA64N32-NEXT: st.b $w1, 0($1)97entry:98 %a = load <16 x i8>, ptr %ptr, align 1699 %b = load <16 x i8>, ptr %ptr2, align 16100 %r = call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %a, <16 x i8> %b, i32 3)101 store <16 x i8> %r, ptr %ptr, align 16102 ret void103}104 105define void @binsri_b(ptr %ptr, ptr %ptr2) {106; MSA-LABEL: binsri_b:107; MSA: # %bb.0: # %entry108; MSA-NEXT: ld.b $w0, 0($5)109; MSA-NEXT: ld.b $w1, 0($4)110; MSA-NEXT: binsri.b $w1, $w0, 5111; MSA-NEXT: jr $ra112; MSA-NEXT: st.b $w1, 0($4)113;114; MSA64N32-LABEL: binsri_b:115; MSA64N32: # %bb.0: # %entry116; MSA64N32-NEXT: sll $1, $4, 0117; MSA64N32-NEXT: sll $2, $5, 0118; MSA64N32-NEXT: ld.b $w0, 0($2)119; MSA64N32-NEXT: ld.b $w1, 0($1)120; MSA64N32-NEXT: binsri.b $w1, $w0, 5121; MSA64N32-NEXT: jr $ra122; MSA64N32-NEXT: st.b $w1, 0($1)123entry:124 %a = load <16 x i8>, ptr %ptr, align 16125 %b = load <16 x i8>, ptr %ptr2, align 16126 %r = call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %a, <16 x i8> %b, i32 5)127 store <16 x i8> %r, ptr %ptr, align 16128 ret void129}130 131define void @bmnzi_b(ptr %ptr, ptr %ptr2) {132; MSA-LABEL: bmnzi_b:133; MSA: # %bb.0: # %entry134; MSA-NEXT: ld.b $w0, 0($5)135; MSA-NEXT: ld.b $w1, 0($4)136; MSA-NEXT: bmnzi.b $w1, $w0, 25137; MSA-NEXT: jr $ra138; MSA-NEXT: st.b $w1, 0($4)139;140; MSA64N32-LABEL: bmnzi_b:141; MSA64N32: # %bb.0: # %entry142; MSA64N32-NEXT: sll $1, $4, 0143; MSA64N32-NEXT: sll $2, $5, 0144; MSA64N32-NEXT: ld.b $w0, 0($2)145; MSA64N32-NEXT: ld.b $w1, 0($1)146; MSA64N32-NEXT: bmnzi.b $w1, $w0, 25147; MSA64N32-NEXT: jr $ra148; MSA64N32-NEXT: st.b $w1, 0($1)149entry:150 %a = load <16 x i8>, ptr %ptr, align 16151 %b = load <16 x i8>, ptr %ptr2, align 16152 %r = call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %a, <16 x i8> %b, i32 25)153 store <16 x i8> %r, ptr %ptr, align 16154 ret void155}156 157define void @bmzi_b(ptr %ptr, ptr %ptr2) {158; MSA-LABEL: bmzi_b:159; MSA: # %bb.0: # %entry160; MSA-NEXT: ld.b $w0, 0($4)161; MSA-NEXT: ld.b $w1, 0($5)162; MSA-NEXT: bmnzi.b $w1, $w0, 25163; MSA-NEXT: jr $ra164; MSA-NEXT: st.b $w1, 0($4)165;166; MSA64N32-LABEL: bmzi_b:167; MSA64N32: # %bb.0: # %entry168; MSA64N32-NEXT: sll $1, $5, 0169; MSA64N32-NEXT: sll $2, $4, 0170; MSA64N32-NEXT: ld.b $w0, 0($2)171; MSA64N32-NEXT: ld.b $w1, 0($1)172; MSA64N32-NEXT: bmnzi.b $w1, $w0, 25173; MSA64N32-NEXT: jr $ra174; MSA64N32-NEXT: st.b $w1, 0($2)175entry:176 %a = load <16 x i8>, ptr %ptr, align 16177 %b = load <16 x i8>, ptr %ptr2, align 16178 %r = call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %a, <16 x i8> %b, i32 25)179 store <16 x i8> %r, ptr %ptr, align 16180 ret void181}182 183define void @bnegi_b(ptr %ptr) {184; MSA-LABEL: bnegi_b:185; MSA: # %bb.0: # %entry186; MSA-NEXT: ld.b $w0, 0($4)187; MSA-NEXT: bnegi.b $w0, $w0, 6188; MSA-NEXT: jr $ra189; MSA-NEXT: st.b $w0, 0($4)190;191; MSA64N32-LABEL: bnegi_b:192; MSA64N32: # %bb.0: # %entry193; MSA64N32-NEXT: sll $1, $4, 0194; MSA64N32-NEXT: ld.b $w0, 0($1)195; MSA64N32-NEXT: bnegi.b $w0, $w0, 6196; MSA64N32-NEXT: jr $ra197; MSA64N32-NEXT: st.b $w0, 0($1)198entry:199 %a = load <16 x i8>, ptr %ptr, align 16200 %r = call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %a, i32 6)201 store <16 x i8> %r, ptr %ptr, align 16202 ret void203}204 205define void @bseli_b(ptr %ptr) {206; MSA-LABEL: bseli_b:207; MSA: # %bb.0: # %entry208; MSA-NEXT: ld.b $w0, 0($4)209; MSA-NEXT: bseli.b $w0, $w0, 25210; MSA-NEXT: jr $ra211; MSA-NEXT: st.b $w0, 0($4)212;213; MSA64N32-LABEL: bseli_b:214; MSA64N32: # %bb.0: # %entry215; MSA64N32-NEXT: sll $1, $4, 0216; MSA64N32-NEXT: ld.b $w0, 0($1)217; MSA64N32-NEXT: bseli.b $w0, $w0, 25218; MSA64N32-NEXT: jr $ra219; MSA64N32-NEXT: st.b $w0, 0($1)220entry:221 %a = load <16 x i8>, ptr %ptr, align 16222 %r = call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %a, <16 x i8> %a, i32 25)223 store <16 x i8> %r, ptr %ptr, align 16224 ret void225}226 227define void @bseti_b(ptr %ptr) {228; MSA-LABEL: bseti_b:229; MSA: # %bb.0: # %entry230; MSA-NEXT: ld.b $w0, 0($4)231; MSA-NEXT: bseti.b $w0, $w0, 5232; MSA-NEXT: jr $ra233; MSA-NEXT: st.b $w0, 0($4)234;235; MSA64N32-LABEL: bseti_b:236; MSA64N32: # %bb.0: # %entry237; MSA64N32-NEXT: sll $1, $4, 0238; MSA64N32-NEXT: ld.b $w0, 0($1)239; MSA64N32-NEXT: bseti.b $w0, $w0, 5240; MSA64N32-NEXT: jr $ra241; MSA64N32-NEXT: st.b $w0, 0($1)242entry:243 %a = load <16 x i8>, ptr %ptr, align 16244 %r = call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %a, i32 5)245 store <16 x i8> %r, ptr %ptr, align 16246 ret void247}248 249define void @clei_s_b(ptr %ptr) {250; MSA-LABEL: clei_s_b:251; MSA: # %bb.0: # %entry252; MSA-NEXT: ld.b $w0, 0($4)253; MSA-NEXT: clei_s.b $w0, $w0, 12254; MSA-NEXT: jr $ra255; MSA-NEXT: st.b $w0, 0($4)256;257; MSA64N32-LABEL: clei_s_b:258; MSA64N32: # %bb.0: # %entry259; MSA64N32-NEXT: sll $1, $4, 0260; MSA64N32-NEXT: ld.b $w0, 0($1)261; MSA64N32-NEXT: clei_s.b $w0, $w0, 12262; MSA64N32-NEXT: jr $ra263; MSA64N32-NEXT: st.b $w0, 0($1)264entry:265 %a = load <16 x i8>, ptr %ptr, align 16266 %r = call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %a, i32 12)267 store <16 x i8> %r, ptr %ptr, align 16268 ret void269}270 271define void @clei_u_b(ptr %ptr) {272; MSA-LABEL: clei_u_b:273; MSA: # %bb.0: # %entry274; MSA-NEXT: ld.b $w0, 0($4)275; MSA-NEXT: clei_u.b $w0, $w0, 25276; MSA-NEXT: jr $ra277; MSA-NEXT: st.b $w0, 0($4)278;279; MSA64N32-LABEL: clei_u_b:280; MSA64N32: # %bb.0: # %entry281; MSA64N32-NEXT: sll $1, $4, 0282; MSA64N32-NEXT: ld.b $w0, 0($1)283; MSA64N32-NEXT: clei_u.b $w0, $w0, 25284; MSA64N32-NEXT: jr $ra285; MSA64N32-NEXT: st.b $w0, 0($1)286entry:287 %a = load <16 x i8>, ptr %ptr, align 16288 %r = call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %a, i32 25)289 store <16 x i8> %r, ptr %ptr, align 16290 ret void291}292 293define void @clti_s_b(ptr %ptr) {294; MSA-LABEL: clti_s_b:295; MSA: # %bb.0: # %entry296; MSA-NEXT: ld.b $w0, 0($4)297; MSA-NEXT: clti_s.b $w0, $w0, 15298; MSA-NEXT: jr $ra299; MSA-NEXT: st.b $w0, 0($4)300;301; MSA64N32-LABEL: clti_s_b:302; MSA64N32: # %bb.0: # %entry303; MSA64N32-NEXT: sll $1, $4, 0304; MSA64N32-NEXT: ld.b $w0, 0($1)305; MSA64N32-NEXT: clti_s.b $w0, $w0, 15306; MSA64N32-NEXT: jr $ra307; MSA64N32-NEXT: st.b $w0, 0($1)308entry:309 %a = load <16 x i8>, ptr %ptr, align 16310 %r = call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %a, i32 15)311 store <16 x i8> %r, ptr %ptr, align 16312 ret void313}314 315define void @clti_u_b(ptr %ptr) {316; MSA-LABEL: clti_u_b:317; MSA: # %bb.0: # %entry318; MSA-NEXT: ld.b $w0, 0($4)319; MSA-NEXT: clti_u.b $w0, $w0, 25320; MSA-NEXT: jr $ra321; MSA-NEXT: st.b $w0, 0($4)322;323; MSA64N32-LABEL: clti_u_b:324; MSA64N32: # %bb.0: # %entry325; MSA64N32-NEXT: sll $1, $4, 0326; MSA64N32-NEXT: ld.b $w0, 0($1)327; MSA64N32-NEXT: clti_u.b $w0, $w0, 25328; MSA64N32-NEXT: jr $ra329; MSA64N32-NEXT: st.b $w0, 0($1)330entry:331 %a = load <16 x i8>, ptr %ptr, align 16332 %r = call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %a, i32 25)333 store <16 x i8> %r, ptr %ptr, align 16334 ret void335}336 337define void @ldi_b(ptr %ptr) {338; MSA-LABEL: ldi_b:339; MSA: # %bb.0: # %entry340; MSA-NEXT: ldi.b $w0, 3341; MSA-NEXT: jr $ra342; MSA-NEXT: st.b $w0, 0($4)343;344; MSA64N32-LABEL: ldi_b:345; MSA64N32: # %bb.0: # %entry346; MSA64N32-NEXT: sll $1, $4, 0347; MSA64N32-NEXT: ldi.b $w0, 3348; MSA64N32-NEXT: jr $ra349; MSA64N32-NEXT: st.b $w0, 0($1)350entry:351 %r = call <16 x i8> @llvm.mips.ldi.b(i32 3)352 store <16 x i8> %r, ptr %ptr, align 16353 ret void354}355 356define void @maxi_s_b(ptr %ptr) {357; MSA-LABEL: maxi_s_b:358; MSA: # %bb.0: # %entry359; MSA-NEXT: ld.b $w0, 0($4)360; MSA-NEXT: maxi_s.b $w0, $w0, 2361; MSA-NEXT: jr $ra362; MSA-NEXT: st.b $w0, 0($4)363;364; MSA64N32-LABEL: maxi_s_b:365; MSA64N32: # %bb.0: # %entry366; MSA64N32-NEXT: sll $1, $4, 0367; MSA64N32-NEXT: ld.b $w0, 0($1)368; MSA64N32-NEXT: maxi_s.b $w0, $w0, 2369; MSA64N32-NEXT: jr $ra370; MSA64N32-NEXT: st.b $w0, 0($1)371entry:372 %a = load <16 x i8>, ptr %ptr, align 16373 %r = call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %a, i32 2)374 store <16 x i8> %r, ptr %ptr, align 16375 ret void376}377 378define void @maxi_u_b(ptr %ptr) {379; MSA-LABEL: maxi_u_b:380; MSA: # %bb.0: # %entry381; MSA-NEXT: ld.b $w0, 0($4)382; MSA-NEXT: maxi_u.b $w0, $w0, 2383; MSA-NEXT: jr $ra384; MSA-NEXT: st.b $w0, 0($4)385;386; MSA64N32-LABEL: maxi_u_b:387; MSA64N32: # %bb.0: # %entry388; MSA64N32-NEXT: sll $1, $4, 0389; MSA64N32-NEXT: ld.b $w0, 0($1)390; MSA64N32-NEXT: maxi_u.b $w0, $w0, 2391; MSA64N32-NEXT: jr $ra392; MSA64N32-NEXT: st.b $w0, 0($1)393entry:394 %a = load <16 x i8>, ptr %ptr, align 16395 %r = call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %a, i32 2)396 store <16 x i8> %r, ptr %ptr, align 16397 ret void398}399 400define void @mini_s_b(ptr %ptr) {401; MSA-LABEL: mini_s_b:402; MSA: # %bb.0: # %entry403; MSA-NEXT: ld.b $w0, 0($4)404; MSA-NEXT: mini_s.b $w0, $w0, 2405; MSA-NEXT: jr $ra406; MSA-NEXT: st.b $w0, 0($4)407;408; MSA64N32-LABEL: mini_s_b:409; MSA64N32: # %bb.0: # %entry410; MSA64N32-NEXT: sll $1, $4, 0411; MSA64N32-NEXT: ld.b $w0, 0($1)412; MSA64N32-NEXT: mini_s.b $w0, $w0, 2413; MSA64N32-NEXT: jr $ra414; MSA64N32-NEXT: st.b $w0, 0($1)415entry:416 %a = load <16 x i8>, ptr %ptr, align 16417 %r = call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %a, i32 2)418 store <16 x i8> %r, ptr %ptr, align 16419 ret void420}421 422define void @mini_u_b(ptr %ptr) {423; MSA-LABEL: mini_u_b:424; MSA: # %bb.0: # %entry425; MSA-NEXT: ld.b $w0, 0($4)426; MSA-NEXT: mini_u.b $w0, $w0, 2427; MSA-NEXT: jr $ra428; MSA-NEXT: st.b $w0, 0($4)429;430; MSA64N32-LABEL: mini_u_b:431; MSA64N32: # %bb.0: # %entry432; MSA64N32-NEXT: sll $1, $4, 0433; MSA64N32-NEXT: ld.b $w0, 0($1)434; MSA64N32-NEXT: mini_u.b $w0, $w0, 2435; MSA64N32-NEXT: jr $ra436; MSA64N32-NEXT: st.b $w0, 0($1)437entry:438 %a = load <16 x i8>, ptr %ptr, align 16439 %r = call <16 x i8> @llvm.mips.mini.u.b(<16 x i8> %a, i32 2)440 store <16 x i8> %r, ptr %ptr, align 16441 ret void442}443 444define void @nori_b(ptr %ptr) {445; MSA-LABEL: nori_b:446; MSA: # %bb.0: # %entry447; MSA-NEXT: ld.b $w0, 0($4)448; MSA-NEXT: nori.b $w0, $w0, 25449; MSA-NEXT: jr $ra450; MSA-NEXT: st.b $w0, 0($4)451;452; MSA64N32-LABEL: nori_b:453; MSA64N32: # %bb.0: # %entry454; MSA64N32-NEXT: sll $1, $4, 0455; MSA64N32-NEXT: ld.b $w0, 0($1)456; MSA64N32-NEXT: nori.b $w0, $w0, 25457; MSA64N32-NEXT: jr $ra458; MSA64N32-NEXT: st.b $w0, 0($1)459entry:460 %a = load <16 x i8>, ptr %ptr, align 16461 %r = call <16 x i8> @llvm.mips.nori.b(<16 x i8> %a, i32 25)462 store <16 x i8> %r, ptr %ptr, align 16463 ret void464}465 466define void @ori_b(ptr %ptr) {467; MSA-LABEL: ori_b:468; MSA: # %bb.0: # %entry469; MSA-NEXT: ld.b $w0, 0($4)470; MSA-NEXT: ori.b $w0, $w0, 25471; MSA-NEXT: jr $ra472; MSA-NEXT: st.b $w0, 0($4)473;474; MSA64N32-LABEL: ori_b:475; MSA64N32: # %bb.0: # %entry476; MSA64N32-NEXT: sll $1, $4, 0477; MSA64N32-NEXT: ld.b $w0, 0($1)478; MSA64N32-NEXT: ori.b $w0, $w0, 25479; MSA64N32-NEXT: jr $ra480; MSA64N32-NEXT: st.b $w0, 0($1)481entry:482 %a = load <16 x i8>, ptr %ptr, align 16483 %r = call <16 x i8> @llvm.mips.ori.b(<16 x i8> %a, i32 25)484 store <16 x i8> %r, ptr %ptr, align 16485 ret void486}487 488define void @sldi_b(ptr %ptr) {489; MSA-LABEL: sldi_b:490; MSA: # %bb.0: # %entry491; MSA-NEXT: ld.b $w0, 0($4)492; MSA-NEXT: sldi.b $w0, $w0[7]493; MSA-NEXT: jr $ra494; MSA-NEXT: st.b $w0, 0($4)495;496; MSA64N32-LABEL: sldi_b:497; MSA64N32: # %bb.0: # %entry498; MSA64N32-NEXT: sll $1, $4, 0499; MSA64N32-NEXT: ld.b $w0, 0($1)500; MSA64N32-NEXT: sldi.b $w0, $w0[7]501; MSA64N32-NEXT: jr $ra502; MSA64N32-NEXT: st.b $w0, 0($1)503entry:504 %a = load <16 x i8>, ptr %ptr, align 16505 %r = call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %a, <16 x i8> %a, i32 7)506 store <16 x i8> %r, ptr %ptr, align 16507 ret void508}509 510define void @slli_b(ptr %ptr) {511; MSA-LABEL: slli_b:512; MSA: # %bb.0: # %entry513; MSA-NEXT: ld.b $w0, 0($4)514; MSA-NEXT: slli.b $w0, $w0, 3515; MSA-NEXT: jr $ra516; MSA-NEXT: st.b $w0, 0($4)517;518; MSA64N32-LABEL: slli_b:519; MSA64N32: # %bb.0: # %entry520; MSA64N32-NEXT: sll $1, $4, 0521; MSA64N32-NEXT: ld.b $w0, 0($1)522; MSA64N32-NEXT: slli.b $w0, $w0, 3523; MSA64N32-NEXT: jr $ra524; MSA64N32-NEXT: st.b $w0, 0($1)525entry:526 %a = load <16 x i8>, ptr %ptr, align 16527 %r = call <16 x i8> @llvm.mips.slli.b(<16 x i8> %a, i32 3)528 store <16 x i8> %r, ptr %ptr, align 16529 ret void530}531 532define void @splati_b(ptr %ptr) {533; MSA-LABEL: splati_b:534; MSA: # %bb.0: # %entry535; MSA-NEXT: ld.b $w0, 0($4)536; MSA-NEXT: splati.b $w0, $w0[3]537; MSA-NEXT: jr $ra538; MSA-NEXT: st.b $w0, 0($4)539;540; MSA64N32-LABEL: splati_b:541; MSA64N32: # %bb.0: # %entry542; MSA64N32-NEXT: sll $1, $4, 0543; MSA64N32-NEXT: ld.b $w0, 0($1)544; MSA64N32-NEXT: splati.b $w0, $w0[3]545; MSA64N32-NEXT: jr $ra546; MSA64N32-NEXT: st.b $w0, 0($1)547entry:548 %a = load <16 x i8>, ptr %ptr, align 16549 %r = call <16 x i8> @llvm.mips.splati.b(<16 x i8> %a, i32 3)550 store <16 x i8> %r, ptr %ptr, align 16551 ret void552}553 554define void @srai_b(ptr %ptr) {555; MSA-LABEL: srai_b:556; MSA: # %bb.0: # %entry557; MSA-NEXT: ld.b $w0, 0($4)558; MSA-NEXT: srai.b $w0, $w0, 3559; MSA-NEXT: jr $ra560; MSA-NEXT: st.b $w0, 0($4)561;562; MSA64N32-LABEL: srai_b:563; MSA64N32: # %bb.0: # %entry564; MSA64N32-NEXT: sll $1, $4, 0565; MSA64N32-NEXT: ld.b $w0, 0($1)566; MSA64N32-NEXT: srai.b $w0, $w0, 3567; MSA64N32-NEXT: jr $ra568; MSA64N32-NEXT: st.b $w0, 0($1)569entry:570 %a = load <16 x i8>, ptr %ptr, align 16571 %r = call <16 x i8> @llvm.mips.srai.b(<16 x i8> %a, i32 3)572 store <16 x i8> %r, ptr %ptr, align 16573 ret void574}575 576define void @srari_b(ptr %ptr) {577; MSA-LABEL: srari_b:578; MSA: # %bb.0: # %entry579; MSA-NEXT: ld.b $w0, 0($4)580; MSA-NEXT: srari.b $w0, $w0, 3581; MSA-NEXT: jr $ra582; MSA-NEXT: st.b $w0, 0($4)583;584; MSA64N32-LABEL: srari_b:585; MSA64N32: # %bb.0: # %entry586; MSA64N32-NEXT: sll $1, $4, 0587; MSA64N32-NEXT: ld.b $w0, 0($1)588; MSA64N32-NEXT: srari.b $w0, $w0, 3589; MSA64N32-NEXT: jr $ra590; MSA64N32-NEXT: st.b $w0, 0($1)591entry:592 %a = load <16 x i8>, ptr %ptr, align 16593 %r = call <16 x i8> @llvm.mips.srari.b(<16 x i8> %a, i32 3)594 store <16 x i8> %r, ptr %ptr, align 16595 ret void596}597 598define void @srli_b(ptr %ptr) {599; MSA-LABEL: srli_b:600; MSA: # %bb.0: # %entry601; MSA-NEXT: ld.b $w0, 0($4)602; MSA-NEXT: srli.b $w0, $w0, 3603; MSA-NEXT: jr $ra604; MSA-NEXT: st.b $w0, 0($4)605;606; MSA64N32-LABEL: srli_b:607; MSA64N32: # %bb.0: # %entry608; MSA64N32-NEXT: sll $1, $4, 0609; MSA64N32-NEXT: ld.b $w0, 0($1)610; MSA64N32-NEXT: srli.b $w0, $w0, 3611; MSA64N32-NEXT: jr $ra612; MSA64N32-NEXT: st.b $w0, 0($1)613entry:614 %a = load <16 x i8>, ptr %ptr, align 16615 %r = call <16 x i8> @llvm.mips.srli.b(<16 x i8> %a, i32 3)616 store <16 x i8> %r, ptr %ptr, align 16617 ret void618}619 620define void @srlri_b(ptr %ptr) {621; MSA-LABEL: srlri_b:622; MSA: # %bb.0: # %entry623; MSA-NEXT: ld.b $w0, 0($4)624; MSA-NEXT: srlri.b $w0, $w0, 3625; MSA-NEXT: jr $ra626; MSA-NEXT: st.b $w0, 0($4)627;628; MSA64N32-LABEL: srlri_b:629; MSA64N32: # %bb.0: # %entry630; MSA64N32-NEXT: sll $1, $4, 0631; MSA64N32-NEXT: ld.b $w0, 0($1)632; MSA64N32-NEXT: srlri.b $w0, $w0, 3633; MSA64N32-NEXT: jr $ra634; MSA64N32-NEXT: st.b $w0, 0($1)635entry:636 %a = load <16 x i8>, ptr %ptr, align 16637 %r = call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %a, i32 3)638 store <16 x i8> %r, ptr %ptr, align 16639 ret void640}641 642define void @addvi_w(ptr %ptr) {643; MSA-LABEL: addvi_w:644; MSA: # %bb.0: # %entry645; MSA-NEXT: ld.w $w0, 0($4)646; MSA-NEXT: addvi.w $w0, $w0, 25647; MSA-NEXT: jr $ra648; MSA-NEXT: st.w $w0, 0($4)649;650; MSA64N32-LABEL: addvi_w:651; MSA64N32: # %bb.0: # %entry652; MSA64N32-NEXT: sll $1, $4, 0653; MSA64N32-NEXT: ld.w $w0, 0($1)654; MSA64N32-NEXT: addvi.w $w0, $w0, 25655; MSA64N32-NEXT: jr $ra656; MSA64N32-NEXT: st.w $w0, 0($1)657entry:658 %a = load <4 x i32>, ptr %ptr, align 16659 %r = call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %a, i32 25)660 store <4 x i32> %r, ptr %ptr, align 16661 ret void662}663 664define void @bclri_w(ptr %ptr) {665; MSA-LABEL: bclri_w:666; MSA: # %bb.0: # %entry667; MSA-NEXT: ld.w $w0, 0($4)668; MSA-NEXT: bclri.w $w0, $w0, 25669; MSA-NEXT: jr $ra670; MSA-NEXT: st.w $w0, 0($4)671;672; MSA64N32-LABEL: bclri_w:673; MSA64N32: # %bb.0: # %entry674; MSA64N32-NEXT: sll $1, $4, 0675; MSA64N32-NEXT: ld.w $w0, 0($1)676; MSA64N32-NEXT: bclri.w $w0, $w0, 25677; MSA64N32-NEXT: jr $ra678; MSA64N32-NEXT: st.w $w0, 0($1)679entry:680 %a = load <4 x i32>, ptr %ptr, align 16681 %r = call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %a, i32 25)682 store <4 x i32> %r, ptr %ptr, align 16683 ret void684}685 686define void @binsli_w(ptr %ptr, ptr %ptr2) {687; MSA-LABEL: binsli_w:688; MSA: # %bb.0: # %entry689; MSA-NEXT: ld.w $w0, 0($5)690; MSA-NEXT: ld.w $w1, 0($4)691; MSA-NEXT: binsli.w $w1, $w0, 25692; MSA-NEXT: jr $ra693; MSA-NEXT: st.w $w1, 0($4)694;695; MSA64N32-LABEL: binsli_w:696; MSA64N32: # %bb.0: # %entry697; MSA64N32-NEXT: sll $1, $4, 0698; MSA64N32-NEXT: sll $2, $5, 0699; MSA64N32-NEXT: ld.w $w0, 0($2)700; MSA64N32-NEXT: ld.w $w1, 0($1)701; MSA64N32-NEXT: binsli.w $w1, $w0, 25702; MSA64N32-NEXT: jr $ra703; MSA64N32-NEXT: st.w $w1, 0($1)704entry:705 %a = load <4 x i32>, ptr %ptr, align 16706 %b = load <4 x i32>, ptr %ptr2, align 16707 %r = call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %a, <4 x i32> %b, i32 25)708 store <4 x i32> %r, ptr %ptr, align 16709 ret void710}711 712define void @binsri_w(ptr %ptr, ptr %ptr2) {713; MSA-LABEL: binsri_w:714; MSA: # %bb.0: # %entry715; MSA-NEXT: ld.w $w0, 0($5)716; MSA-NEXT: ld.w $w1, 0($4)717; MSA-NEXT: binsri.w $w1, $w0, 25718; MSA-NEXT: jr $ra719; MSA-NEXT: st.w $w1, 0($4)720;721; MSA64N32-LABEL: binsri_w:722; MSA64N32: # %bb.0: # %entry723; MSA64N32-NEXT: sll $1, $4, 0724; MSA64N32-NEXT: sll $2, $5, 0725; MSA64N32-NEXT: ld.w $w0, 0($2)726; MSA64N32-NEXT: ld.w $w1, 0($1)727; MSA64N32-NEXT: binsri.w $w1, $w0, 25728; MSA64N32-NEXT: jr $ra729; MSA64N32-NEXT: st.w $w1, 0($1)730entry:731 %a = load <4 x i32>, ptr %ptr, align 16732 %b = load <4 x i32>, ptr %ptr2, align 16733 %r = call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %a, <4 x i32> %b, i32 25)734 store <4 x i32> %r, ptr %ptr, align 16735 ret void736}737 738define void @bnegi_w(ptr %ptr) {739; MSA-LABEL: bnegi_w:740; MSA: # %bb.0: # %entry741; MSA-NEXT: ld.w $w0, 0($4)742; MSA-NEXT: bnegi.w $w0, $w0, 25743; MSA-NEXT: jr $ra744; MSA-NEXT: st.w $w0, 0($4)745;746; MSA64N32-LABEL: bnegi_w:747; MSA64N32: # %bb.0: # %entry748; MSA64N32-NEXT: sll $1, $4, 0749; MSA64N32-NEXT: ld.w $w0, 0($1)750; MSA64N32-NEXT: bnegi.w $w0, $w0, 25751; MSA64N32-NEXT: jr $ra752; MSA64N32-NEXT: st.w $w0, 0($1)753entry:754 %a = load <4 x i32>, ptr %ptr, align 16755 %r = call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %a, i32 25)756 store <4 x i32> %r, ptr %ptr, align 16757 ret void758}759 760define void @bseti_w(ptr %ptr) {761; MSA-LABEL: bseti_w:762; MSA: # %bb.0: # %entry763; MSA-NEXT: ld.w $w0, 0($4)764; MSA-NEXT: bseti.w $w0, $w0, 25765; MSA-NEXT: jr $ra766; MSA-NEXT: st.w $w0, 0($4)767;768; MSA64N32-LABEL: bseti_w:769; MSA64N32: # %bb.0: # %entry770; MSA64N32-NEXT: sll $1, $4, 0771; MSA64N32-NEXT: ld.w $w0, 0($1)772; MSA64N32-NEXT: bseti.w $w0, $w0, 25773; MSA64N32-NEXT: jr $ra774; MSA64N32-NEXT: st.w $w0, 0($1)775entry:776 %a = load <4 x i32>, ptr %ptr, align 16777 %r = call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %a, i32 25)778 store <4 x i32> %r, ptr %ptr, align 16779 ret void780}781 782define void @clei_s_w(ptr %ptr) {783; MSA-LABEL: clei_s_w:784; MSA: # %bb.0: # %entry785; MSA-NEXT: ld.w $w0, 0($4)786; MSA-NEXT: clei_s.w $w0, $w0, 14787; MSA-NEXT: jr $ra788; MSA-NEXT: st.w $w0, 0($4)789;790; MSA64N32-LABEL: clei_s_w:791; MSA64N32: # %bb.0: # %entry792; MSA64N32-NEXT: sll $1, $4, 0793; MSA64N32-NEXT: ld.w $w0, 0($1)794; MSA64N32-NEXT: clei_s.w $w0, $w0, 14795; MSA64N32-NEXT: jr $ra796; MSA64N32-NEXT: st.w $w0, 0($1)797entry:798 %a = load <4 x i32>, ptr %ptr, align 16799 %r = call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %a, i32 14)800 store <4 x i32> %r, ptr %ptr, align 16801 ret void802}803 804define void @clei_u_w(ptr %ptr) {805; MSA-LABEL: clei_u_w:806; MSA: # %bb.0: # %entry807; MSA-NEXT: ld.w $w0, 0($4)808; MSA-NEXT: clei_u.w $w0, $w0, 25809; MSA-NEXT: jr $ra810; MSA-NEXT: st.w $w0, 0($4)811;812; MSA64N32-LABEL: clei_u_w:813; MSA64N32: # %bb.0: # %entry814; MSA64N32-NEXT: sll $1, $4, 0815; MSA64N32-NEXT: ld.w $w0, 0($1)816; MSA64N32-NEXT: clei_u.w $w0, $w0, 25817; MSA64N32-NEXT: jr $ra818; MSA64N32-NEXT: st.w $w0, 0($1)819entry:820 %a = load <4 x i32>, ptr %ptr, align 16821 %r = call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %a, i32 25)822 store <4 x i32> %r, ptr %ptr, align 16823 ret void824}825 826define void @clti_s_w(ptr %ptr) {827; MSA-LABEL: clti_s_w:828; MSA: # %bb.0: # %entry829; MSA-NEXT: ld.w $w0, 0($4)830; MSA-NEXT: clti_s.w $w0, $w0, 15831; MSA-NEXT: jr $ra832; MSA-NEXT: st.w $w0, 0($4)833;834; MSA64N32-LABEL: clti_s_w:835; MSA64N32: # %bb.0: # %entry836; MSA64N32-NEXT: sll $1, $4, 0837; MSA64N32-NEXT: ld.w $w0, 0($1)838; MSA64N32-NEXT: clti_s.w $w0, $w0, 15839; MSA64N32-NEXT: jr $ra840; MSA64N32-NEXT: st.w $w0, 0($1)841entry:842 %a = load <4 x i32>, ptr %ptr, align 16843 %r = call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %a, i32 15)844 store <4 x i32> %r, ptr %ptr, align 16845 ret void846}847 848define void @clti_u_w(ptr %ptr) {849; MSA-LABEL: clti_u_w:850; MSA: # %bb.0: # %entry851; MSA-NEXT: ld.w $w0, 0($4)852; MSA-NEXT: clti_u.w $w0, $w0, 25853; MSA-NEXT: jr $ra854; MSA-NEXT: st.w $w0, 0($4)855;856; MSA64N32-LABEL: clti_u_w:857; MSA64N32: # %bb.0: # %entry858; MSA64N32-NEXT: sll $1, $4, 0859; MSA64N32-NEXT: ld.w $w0, 0($1)860; MSA64N32-NEXT: clti_u.w $w0, $w0, 25861; MSA64N32-NEXT: jr $ra862; MSA64N32-NEXT: st.w $w0, 0($1)863entry:864 %a = load <4 x i32>, ptr %ptr, align 16865 %r = call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %a, i32 25)866 store <4 x i32> %r, ptr %ptr, align 16867 ret void868}869 870define void @maxi_s_w(ptr %ptr) {871; MSA-LABEL: maxi_s_w:872; MSA: # %bb.0: # %entry873; MSA-NEXT: ld.w $w0, 0($4)874; MSA-NEXT: maxi_s.w $w0, $w0, 2875; MSA-NEXT: jr $ra876; MSA-NEXT: st.w $w0, 0($4)877;878; MSA64N32-LABEL: maxi_s_w:879; MSA64N32: # %bb.0: # %entry880; MSA64N32-NEXT: sll $1, $4, 0881; MSA64N32-NEXT: ld.w $w0, 0($1)882; MSA64N32-NEXT: maxi_s.w $w0, $w0, 2883; MSA64N32-NEXT: jr $ra884; MSA64N32-NEXT: st.w $w0, 0($1)885entry:886 %a = load <4 x i32>, ptr %ptr, align 16887 %r = call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %a, i32 2)888 store <4 x i32> %r, ptr %ptr, align 16889 ret void890}891 892define void @maxi_u_w(ptr %ptr) {893; MSA-LABEL: maxi_u_w:894; MSA: # %bb.0: # %entry895; MSA-NEXT: ld.w $w0, 0($4)896; MSA-NEXT: maxi_u.w $w0, $w0, 2897; MSA-NEXT: jr $ra898; MSA-NEXT: st.w $w0, 0($4)899;900; MSA64N32-LABEL: maxi_u_w:901; MSA64N32: # %bb.0: # %entry902; MSA64N32-NEXT: sll $1, $4, 0903; MSA64N32-NEXT: ld.w $w0, 0($1)904; MSA64N32-NEXT: maxi_u.w $w0, $w0, 2905; MSA64N32-NEXT: jr $ra906; MSA64N32-NEXT: st.w $w0, 0($1)907entry:908 %a = load <4 x i32>, ptr %ptr, align 16909 %r = call <4 x i32> @llvm.mips.maxi.u.w(<4 x i32> %a, i32 2)910 store <4 x i32> %r, ptr %ptr, align 16911 ret void912}913 914define void @mini_s_w(ptr %ptr) {915; MSA-LABEL: mini_s_w:916; MSA: # %bb.0: # %entry917; MSA-NEXT: ld.w $w0, 0($4)918; MSA-NEXT: mini_s.w $w0, $w0, 2919; MSA-NEXT: jr $ra920; MSA-NEXT: st.w $w0, 0($4)921;922; MSA64N32-LABEL: mini_s_w:923; MSA64N32: # %bb.0: # %entry924; MSA64N32-NEXT: sll $1, $4, 0925; MSA64N32-NEXT: ld.w $w0, 0($1)926; MSA64N32-NEXT: mini_s.w $w0, $w0, 2927; MSA64N32-NEXT: jr $ra928; MSA64N32-NEXT: st.w $w0, 0($1)929entry:930 %a = load <4 x i32>, ptr %ptr, align 16931 %r = call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %a, i32 2)932 store <4 x i32> %r, ptr %ptr, align 16933 ret void934}935 936define void @mini_u_w(ptr %ptr) {937; MSA-LABEL: mini_u_w:938; MSA: # %bb.0: # %entry939; MSA-NEXT: ld.w $w0, 0($4)940; MSA-NEXT: mini_u.w $w0, $w0, 2941; MSA-NEXT: jr $ra942; MSA-NEXT: st.w $w0, 0($4)943;944; MSA64N32-LABEL: mini_u_w:945; MSA64N32: # %bb.0: # %entry946; MSA64N32-NEXT: sll $1, $4, 0947; MSA64N32-NEXT: ld.w $w0, 0($1)948; MSA64N32-NEXT: mini_u.w $w0, $w0, 2949; MSA64N32-NEXT: jr $ra950; MSA64N32-NEXT: st.w $w0, 0($1)951entry:952 %a = load <4 x i32>, ptr %ptr, align 16953 %r = call <4 x i32> @llvm.mips.mini.u.w(<4 x i32> %a, i32 2)954 store <4 x i32> %r, ptr %ptr, align 16955 ret void956}957 958define void @ldi_w(ptr %ptr) {959; MSA-LABEL: ldi_w:960; MSA: # %bb.0: # %entry961; MSA-NEXT: ldi.w $w0, 3962; MSA-NEXT: jr $ra963; MSA-NEXT: st.w $w0, 0($4)964;965; MSA64N32-LABEL: ldi_w:966; MSA64N32: # %bb.0: # %entry967; MSA64N32-NEXT: sll $1, $4, 0968; MSA64N32-NEXT: ldi.w $w0, 3969; MSA64N32-NEXT: jr $ra970; MSA64N32-NEXT: st.w $w0, 0($1)971entry:972 %r = call <4 x i32> @llvm.mips.ldi.w(i32 3)973 store <4 x i32> %r, ptr %ptr, align 16974 ret void975}976 977define void @sldi_w(ptr %ptr) {978; MSA-LABEL: sldi_w:979; MSA: # %bb.0: # %entry980; MSA-NEXT: ld.w $w0, 0($4)981; MSA-NEXT: sldi.w $w0, $w0[2]982; MSA-NEXT: jr $ra983; MSA-NEXT: st.w $w0, 0($4)984;985; MSA64N32-LABEL: sldi_w:986; MSA64N32: # %bb.0: # %entry987; MSA64N32-NEXT: sll $1, $4, 0988; MSA64N32-NEXT: ld.w $w0, 0($1)989; MSA64N32-NEXT: sldi.w $w0, $w0[2]990; MSA64N32-NEXT: jr $ra991; MSA64N32-NEXT: st.w $w0, 0($1)992entry:993 %a = load <4 x i32>, ptr %ptr, align 16994 %r = call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %a, <4 x i32> %a, i32 2)995 store <4 x i32> %r, ptr %ptr, align 16996 ret void997}998 999define void @slli_w(ptr %ptr) {1000; MSA-LABEL: slli_w:1001; MSA: # %bb.0: # %entry1002; MSA-NEXT: ld.w $w0, 0($4)1003; MSA-NEXT: slli.w $w0, $w0, 31004; MSA-NEXT: jr $ra1005; MSA-NEXT: st.w $w0, 0($4)1006;1007; MSA64N32-LABEL: slli_w:1008; MSA64N32: # %bb.0: # %entry1009; MSA64N32-NEXT: sll $1, $4, 01010; MSA64N32-NEXT: ld.w $w0, 0($1)1011; MSA64N32-NEXT: slli.w $w0, $w0, 31012; MSA64N32-NEXT: jr $ra1013; MSA64N32-NEXT: st.w $w0, 0($1)1014entry:1015 %a = load <4 x i32>, ptr %ptr, align 161016 %r = call <4 x i32> @llvm.mips.slli.w(<4 x i32> %a, i32 3)1017 store <4 x i32> %r, ptr %ptr, align 161018 ret void1019}1020 1021define void @splati_w(ptr %ptr) {1022; MSA-LABEL: splati_w:1023; MSA: # %bb.0: # %entry1024; MSA-NEXT: ld.w $w0, 0($4)1025; MSA-NEXT: splati.w $w0, $w0[3]1026; MSA-NEXT: jr $ra1027; MSA-NEXT: st.w $w0, 0($4)1028;1029; MSA64N32-LABEL: splati_w:1030; MSA64N32: # %bb.0: # %entry1031; MSA64N32-NEXT: sll $1, $4, 01032; MSA64N32-NEXT: ld.w $w0, 0($1)1033; MSA64N32-NEXT: splati.w $w0, $w0[3]1034; MSA64N32-NEXT: jr $ra1035; MSA64N32-NEXT: st.w $w0, 0($1)1036entry:1037 %a = load <4 x i32>, ptr %ptr, align 161038 %r = call <4 x i32> @llvm.mips.splati.w(<4 x i32> %a, i32 3)1039 store <4 x i32> %r, ptr %ptr, align 161040 ret void1041}1042 1043define void @srai_w(ptr %ptr) {1044; MSA-LABEL: srai_w:1045; MSA: # %bb.0: # %entry1046; MSA-NEXT: ld.w $w0, 0($4)1047; MSA-NEXT: srai.w $w0, $w0, 31048; MSA-NEXT: jr $ra1049; MSA-NEXT: st.w $w0, 0($4)1050;1051; MSA64N32-LABEL: srai_w:1052; MSA64N32: # %bb.0: # %entry1053; MSA64N32-NEXT: sll $1, $4, 01054; MSA64N32-NEXT: ld.w $w0, 0($1)1055; MSA64N32-NEXT: srai.w $w0, $w0, 31056; MSA64N32-NEXT: jr $ra1057; MSA64N32-NEXT: st.w $w0, 0($1)1058entry:1059 %a = load <4 x i32>, ptr %ptr, align 161060 %r = call <4 x i32> @llvm.mips.srai.w(<4 x i32> %a, i32 3)1061 store <4 x i32> %r, ptr %ptr, align 161062 ret void1063}1064 1065define void @srari_w(ptr %ptr) {1066; MSA-LABEL: srari_w:1067; MSA: # %bb.0: # %entry1068; MSA-NEXT: ld.w $w0, 0($4)1069; MSA-NEXT: srari.w $w0, $w0, 31070; MSA-NEXT: jr $ra1071; MSA-NEXT: st.w $w0, 0($4)1072;1073; MSA64N32-LABEL: srari_w:1074; MSA64N32: # %bb.0: # %entry1075; MSA64N32-NEXT: sll $1, $4, 01076; MSA64N32-NEXT: ld.w $w0, 0($1)1077; MSA64N32-NEXT: srari.w $w0, $w0, 31078; MSA64N32-NEXT: jr $ra1079; MSA64N32-NEXT: st.w $w0, 0($1)1080entry:1081 %a = load <4 x i32>, ptr %ptr, align 161082 %r = call <4 x i32> @llvm.mips.srari.w(<4 x i32> %a, i32 3)1083 store <4 x i32> %r, ptr %ptr, align 161084 ret void1085}1086 1087define void @srli_w(ptr %ptr) {1088; MSA-LABEL: srli_w:1089; MSA: # %bb.0: # %entry1090; MSA-NEXT: ld.w $w0, 0($4)1091; MSA-NEXT: srli.w $w0, $w0, 31092; MSA-NEXT: jr $ra1093; MSA-NEXT: st.w $w0, 0($4)1094;1095; MSA64N32-LABEL: srli_w:1096; MSA64N32: # %bb.0: # %entry1097; MSA64N32-NEXT: sll $1, $4, 01098; MSA64N32-NEXT: ld.w $w0, 0($1)1099; MSA64N32-NEXT: srli.w $w0, $w0, 31100; MSA64N32-NEXT: jr $ra1101; MSA64N32-NEXT: st.w $w0, 0($1)1102entry:1103 %a = load <4 x i32>, ptr %ptr, align 161104 %r = call <4 x i32> @llvm.mips.srli.w(<4 x i32> %a, i32 3)1105 store <4 x i32> %r, ptr %ptr, align 161106 ret void1107}1108 1109define void @srlri_w(ptr %ptr) {1110; MSA-LABEL: srlri_w:1111; MSA: # %bb.0: # %entry1112; MSA-NEXT: ld.w $w0, 0($4)1113; MSA-NEXT: srlri.w $w0, $w0, 31114; MSA-NEXT: jr $ra1115; MSA-NEXT: st.w $w0, 0($4)1116;1117; MSA64N32-LABEL: srlri_w:1118; MSA64N32: # %bb.0: # %entry1119; MSA64N32-NEXT: sll $1, $4, 01120; MSA64N32-NEXT: ld.w $w0, 0($1)1121; MSA64N32-NEXT: srlri.w $w0, $w0, 31122; MSA64N32-NEXT: jr $ra1123; MSA64N32-NEXT: st.w $w0, 0($1)1124entry:1125 %a = load <4 x i32>, ptr %ptr, align 161126 %r = call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %a, i32 3)1127 store <4 x i32> %r, ptr %ptr, align 161128 ret void1129}1130 1131define void @addvi_h(ptr %ptr) {1132; MSA-LABEL: addvi_h:1133; MSA: # %bb.0: # %entry1134; MSA-NEXT: ld.h $w0, 0($4)1135; MSA-NEXT: addvi.h $w0, $w0, 251136; MSA-NEXT: jr $ra1137; MSA-NEXT: st.h $w0, 0($4)1138;1139; MSA64N32-LABEL: addvi_h:1140; MSA64N32: # %bb.0: # %entry1141; MSA64N32-NEXT: sll $1, $4, 01142; MSA64N32-NEXT: ld.h $w0, 0($1)1143; MSA64N32-NEXT: addvi.h $w0, $w0, 251144; MSA64N32-NEXT: jr $ra1145; MSA64N32-NEXT: st.h $w0, 0($1)1146entry:1147 %a = load <8 x i16>, ptr %ptr, align 161148 %r = call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %a, i32 25)1149 store <8 x i16> %r, ptr %ptr, align 161150 ret void1151}1152 1153define void @bclri_h(ptr %ptr) {1154; MSA-LABEL: bclri_h:1155; MSA: # %bb.0: # %entry1156; MSA-NEXT: ld.h $w0, 0($4)1157; MSA-NEXT: bclri.h $w0, $w0, 81158; MSA-NEXT: jr $ra1159; MSA-NEXT: st.h $w0, 0($4)1160;1161; MSA64N32-LABEL: bclri_h:1162; MSA64N32: # %bb.0: # %entry1163; MSA64N32-NEXT: sll $1, $4, 01164; MSA64N32-NEXT: ld.h $w0, 0($1)1165; MSA64N32-NEXT: bclri.h $w0, $w0, 81166; MSA64N32-NEXT: jr $ra1167; MSA64N32-NEXT: st.h $w0, 0($1)1168entry:1169 %a = load <8 x i16>, ptr %ptr, align 161170 %r = call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %a, i32 8)1171 store <8 x i16> %r, ptr %ptr, align 161172 ret void1173}1174 1175define void @binsli_h(ptr %ptr, ptr %ptr2) {1176; MSA-LABEL: binsli_h:1177; MSA: # %bb.0: # %entry1178; MSA-NEXT: ld.h $w0, 0($5)1179; MSA-NEXT: ld.h $w1, 0($4)1180; MSA-NEXT: binsli.h $w1, $w0, 81181; MSA-NEXT: jr $ra1182; MSA-NEXT: st.h $w1, 0($4)1183;1184; MSA64N32-LABEL: binsli_h:1185; MSA64N32: # %bb.0: # %entry1186; MSA64N32-NEXT: sll $1, $4, 01187; MSA64N32-NEXT: sll $2, $5, 01188; MSA64N32-NEXT: ld.h $w0, 0($2)1189; MSA64N32-NEXT: ld.h $w1, 0($1)1190; MSA64N32-NEXT: binsli.h $w1, $w0, 81191; MSA64N32-NEXT: jr $ra1192; MSA64N32-NEXT: st.h $w1, 0($1)1193entry:1194 %a = load <8 x i16>, ptr %ptr, align 161195 %b = load <8 x i16>, ptr %ptr2, align 161196 %r = call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %a, <8 x i16> %b, i32 8)1197 store <8 x i16> %r, ptr %ptr, align 161198 ret void1199}1200 1201define void @binsri_h(ptr %ptr, ptr %ptr2) {1202; MSA-LABEL: binsri_h:1203; MSA: # %bb.0: # %entry1204; MSA-NEXT: ld.h $w0, 0($5)1205; MSA-NEXT: ld.h $w1, 0($4)1206; MSA-NEXT: binsri.h $w1, $w0, 141207; MSA-NEXT: jr $ra1208; MSA-NEXT: st.h $w1, 0($4)1209;1210; MSA64N32-LABEL: binsri_h:1211; MSA64N32: # %bb.0: # %entry1212; MSA64N32-NEXT: sll $1, $4, 01213; MSA64N32-NEXT: sll $2, $5, 01214; MSA64N32-NEXT: ld.h $w0, 0($2)1215; MSA64N32-NEXT: ld.h $w1, 0($1)1216; MSA64N32-NEXT: binsri.h $w1, $w0, 141217; MSA64N32-NEXT: jr $ra1218; MSA64N32-NEXT: st.h $w1, 0($1)1219entry:1220 %a = load <8 x i16>, ptr %ptr, align 161221 %b = load <8 x i16>, ptr %ptr2, align 161222 %r = call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %a, <8 x i16> %b, i32 14)1223 store <8 x i16> %r, ptr %ptr, align 161224 ret void1225}1226 1227define void @bnegi_h(ptr %ptr) {1228; MSA-LABEL: bnegi_h:1229; MSA: # %bb.0: # %entry1230; MSA-NEXT: ld.h $w0, 0($4)1231; MSA-NEXT: bnegi.h $w0, $w0, 141232; MSA-NEXT: jr $ra1233; MSA-NEXT: st.h $w0, 0($4)1234;1235; MSA64N32-LABEL: bnegi_h:1236; MSA64N32: # %bb.0: # %entry1237; MSA64N32-NEXT: sll $1, $4, 01238; MSA64N32-NEXT: ld.h $w0, 0($1)1239; MSA64N32-NEXT: bnegi.h $w0, $w0, 141240; MSA64N32-NEXT: jr $ra1241; MSA64N32-NEXT: st.h $w0, 0($1)1242entry:1243 %a = load <8 x i16>, ptr %ptr, align 161244 %r = call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %a, i32 14)1245 store <8 x i16> %r, ptr %ptr, align 161246 ret void1247}1248 1249define void @bseti_h(ptr %ptr) {1250; MSA-LABEL: bseti_h:1251; MSA: # %bb.0: # %entry1252; MSA-NEXT: ld.h $w0, 0($4)1253; MSA-NEXT: bseti.h $w0, $w0, 151254; MSA-NEXT: jr $ra1255; MSA-NEXT: st.h $w0, 0($4)1256;1257; MSA64N32-LABEL: bseti_h:1258; MSA64N32: # %bb.0: # %entry1259; MSA64N32-NEXT: sll $1, $4, 01260; MSA64N32-NEXT: ld.h $w0, 0($1)1261; MSA64N32-NEXT: bseti.h $w0, $w0, 151262; MSA64N32-NEXT: jr $ra1263; MSA64N32-NEXT: st.h $w0, 0($1)1264entry:1265 %a = load <8 x i16>, ptr %ptr, align 161266 %r = call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %a, i32 15)1267 store <8 x i16> %r, ptr %ptr, align 161268 ret void1269}1270 1271define void @clei_s_h(ptr %ptr) {1272; MSA-LABEL: clei_s_h:1273; MSA: # %bb.0: # %entry1274; MSA-NEXT: ld.h $w0, 0($4)1275; MSA-NEXT: clei_s.h $w0, $w0, 131276; MSA-NEXT: jr $ra1277; MSA-NEXT: st.h $w0, 0($4)1278;1279; MSA64N32-LABEL: clei_s_h:1280; MSA64N32: # %bb.0: # %entry1281; MSA64N32-NEXT: sll $1, $4, 01282; MSA64N32-NEXT: ld.h $w0, 0($1)1283; MSA64N32-NEXT: clei_s.h $w0, $w0, 131284; MSA64N32-NEXT: jr $ra1285; MSA64N32-NEXT: st.h $w0, 0($1)1286entry:1287 %a = load <8 x i16>, ptr %ptr, align 161288 %r = call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %a, i32 13)1289 store <8 x i16> %r, ptr %ptr, align 161290 ret void1291}1292 1293define void @clei_u_h(ptr %ptr) {1294; MSA-LABEL: clei_u_h:1295; MSA: # %bb.0: # %entry1296; MSA-NEXT: ld.h $w0, 0($4)1297; MSA-NEXT: clei_u.h $w0, $w0, 251298; MSA-NEXT: jr $ra1299; MSA-NEXT: st.h $w0, 0($4)1300;1301; MSA64N32-LABEL: clei_u_h:1302; MSA64N32: # %bb.0: # %entry1303; MSA64N32-NEXT: sll $1, $4, 01304; MSA64N32-NEXT: ld.h $w0, 0($1)1305; MSA64N32-NEXT: clei_u.h $w0, $w0, 251306; MSA64N32-NEXT: jr $ra1307; MSA64N32-NEXT: st.h $w0, 0($1)1308entry:1309 %a = load <8 x i16>, ptr %ptr, align 161310 %r = call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %a, i32 25)1311 store <8 x i16> %r, ptr %ptr, align 161312 ret void1313}1314 1315define void @clti_s_h(ptr %ptr) {1316; MSA-LABEL: clti_s_h:1317; MSA: # %bb.0: # %entry1318; MSA-NEXT: ld.h $w0, 0($4)1319; MSA-NEXT: clti_s.h $w0, $w0, 151320; MSA-NEXT: jr $ra1321; MSA-NEXT: st.h $w0, 0($4)1322;1323; MSA64N32-LABEL: clti_s_h:1324; MSA64N32: # %bb.0: # %entry1325; MSA64N32-NEXT: sll $1, $4, 01326; MSA64N32-NEXT: ld.h $w0, 0($1)1327; MSA64N32-NEXT: clti_s.h $w0, $w0, 151328; MSA64N32-NEXT: jr $ra1329; MSA64N32-NEXT: st.h $w0, 0($1)1330entry:1331 %a = load <8 x i16>, ptr %ptr, align 161332 %r = call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %a, i32 15)1333 store <8 x i16> %r, ptr %ptr, align 161334 ret void1335}1336 1337define void @clti_u_h(ptr %ptr) {1338; MSA-LABEL: clti_u_h:1339; MSA: # %bb.0: # %entry1340; MSA-NEXT: ld.h $w0, 0($4)1341; MSA-NEXT: clti_u.h $w0, $w0, 251342; MSA-NEXT: jr $ra1343; MSA-NEXT: st.h $w0, 0($4)1344;1345; MSA64N32-LABEL: clti_u_h:1346; MSA64N32: # %bb.0: # %entry1347; MSA64N32-NEXT: sll $1, $4, 01348; MSA64N32-NEXT: ld.h $w0, 0($1)1349; MSA64N32-NEXT: clti_u.h $w0, $w0, 251350; MSA64N32-NEXT: jr $ra1351; MSA64N32-NEXT: st.h $w0, 0($1)1352entry:1353 %a = load <8 x i16>, ptr %ptr, align 161354 %r = call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %a, i32 25)1355 store <8 x i16> %r, ptr %ptr, align 161356 ret void1357}1358 1359define void @maxi_s_h(ptr %ptr) {1360; MSA-LABEL: maxi_s_h:1361; MSA: # %bb.0: # %entry1362; MSA-NEXT: ld.h $w0, 0($4)1363; MSA-NEXT: maxi_s.h $w0, $w0, 21364; MSA-NEXT: jr $ra1365; MSA-NEXT: st.h $w0, 0($4)1366;1367; MSA64N32-LABEL: maxi_s_h:1368; MSA64N32: # %bb.0: # %entry1369; MSA64N32-NEXT: sll $1, $4, 01370; MSA64N32-NEXT: ld.h $w0, 0($1)1371; MSA64N32-NEXT: maxi_s.h $w0, $w0, 21372; MSA64N32-NEXT: jr $ra1373; MSA64N32-NEXT: st.h $w0, 0($1)1374entry:1375 %a = load <8 x i16>, ptr %ptr, align 161376 %r = call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %a, i32 2)1377 store <8 x i16> %r, ptr %ptr, align 161378 ret void1379}1380 1381define void @maxi_u_h(ptr %ptr) {1382; MSA-LABEL: maxi_u_h:1383; MSA: # %bb.0: # %entry1384; MSA-NEXT: ld.h $w0, 0($4)1385; MSA-NEXT: maxi_u.h $w0, $w0, 21386; MSA-NEXT: jr $ra1387; MSA-NEXT: st.h $w0, 0($4)1388;1389; MSA64N32-LABEL: maxi_u_h:1390; MSA64N32: # %bb.0: # %entry1391; MSA64N32-NEXT: sll $1, $4, 01392; MSA64N32-NEXT: ld.h $w0, 0($1)1393; MSA64N32-NEXT: maxi_u.h $w0, $w0, 21394; MSA64N32-NEXT: jr $ra1395; MSA64N32-NEXT: st.h $w0, 0($1)1396entry:1397 %a = load <8 x i16>, ptr %ptr, align 161398 %r = call <8 x i16> @llvm.mips.maxi.u.h(<8 x i16> %a, i32 2)1399 store <8 x i16> %r, ptr %ptr, align 161400 ret void1401}1402 1403define void @mini_s_h(ptr %ptr) {1404; MSA-LABEL: mini_s_h:1405; MSA: # %bb.0: # %entry1406; MSA-NEXT: ld.h $w0, 0($4)1407; MSA-NEXT: mini_s.h $w0, $w0, 21408; MSA-NEXT: jr $ra1409; MSA-NEXT: st.h $w0, 0($4)1410;1411; MSA64N32-LABEL: mini_s_h:1412; MSA64N32: # %bb.0: # %entry1413; MSA64N32-NEXT: sll $1, $4, 01414; MSA64N32-NEXT: ld.h $w0, 0($1)1415; MSA64N32-NEXT: mini_s.h $w0, $w0, 21416; MSA64N32-NEXT: jr $ra1417; MSA64N32-NEXT: st.h $w0, 0($1)1418entry:1419 %a = load <8 x i16>, ptr %ptr, align 161420 %r = call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %a, i32 2)1421 store <8 x i16> %r, ptr %ptr, align 161422 ret void1423}1424 1425define void @mini_u_h(ptr %ptr) {1426; MSA-LABEL: mini_u_h:1427; MSA: # %bb.0: # %entry1428; MSA-NEXT: ld.h $w0, 0($4)1429; MSA-NEXT: mini_u.h $w0, $w0, 21430; MSA-NEXT: jr $ra1431; MSA-NEXT: st.h $w0, 0($4)1432;1433; MSA64N32-LABEL: mini_u_h:1434; MSA64N32: # %bb.0: # %entry1435; MSA64N32-NEXT: sll $1, $4, 01436; MSA64N32-NEXT: ld.h $w0, 0($1)1437; MSA64N32-NEXT: mini_u.h $w0, $w0, 21438; MSA64N32-NEXT: jr $ra1439; MSA64N32-NEXT: st.h $w0, 0($1)1440entry:1441 %a = load <8 x i16>, ptr %ptr, align 161442 %r = call <8 x i16> @llvm.mips.mini.u.h(<8 x i16> %a, i32 2)1443 store <8 x i16> %r, ptr %ptr, align 161444 ret void1445}1446 1447define void @ldi_h(ptr %ptr) {1448; MSA-LABEL: ldi_h:1449; MSA: # %bb.0: # %entry1450; MSA-NEXT: ldi.h $w0, 31451; MSA-NEXT: jr $ra1452; MSA-NEXT: st.h $w0, 0($4)1453;1454; MSA64N32-LABEL: ldi_h:1455; MSA64N32: # %bb.0: # %entry1456; MSA64N32-NEXT: sll $1, $4, 01457; MSA64N32-NEXT: ldi.h $w0, 31458; MSA64N32-NEXT: jr $ra1459; MSA64N32-NEXT: st.h $w0, 0($1)1460entry:1461 %r = call <8 x i16> @llvm.mips.ldi.h(i32 3)1462 store <8 x i16> %r, ptr %ptr, align 161463 ret void1464}1465 1466define void @sldi_h(ptr %ptr) {1467; MSA-LABEL: sldi_h:1468; MSA: # %bb.0: # %entry1469; MSA-NEXT: ld.h $w0, 0($4)1470; MSA-NEXT: sldi.h $w0, $w0[3]1471; MSA-NEXT: jr $ra1472; MSA-NEXT: st.h $w0, 0($4)1473;1474; MSA64N32-LABEL: sldi_h:1475; MSA64N32: # %bb.0: # %entry1476; MSA64N32-NEXT: sll $1, $4, 01477; MSA64N32-NEXT: ld.h $w0, 0($1)1478; MSA64N32-NEXT: sldi.h $w0, $w0[3]1479; MSA64N32-NEXT: jr $ra1480; MSA64N32-NEXT: st.h $w0, 0($1)1481entry:1482 %a = load <8 x i16>, ptr %ptr, align 161483 %r = call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %a, <8 x i16> %a, i32 3)1484 store <8 x i16> %r, ptr %ptr, align 161485 ret void1486}1487 1488define void @slli_h(ptr %ptr) {1489; MSA-LABEL: slli_h:1490; MSA: # %bb.0: # %entry1491; MSA-NEXT: ld.h $w0, 0($4)1492; MSA-NEXT: slli.h $w0, $w0, 31493; MSA-NEXT: jr $ra1494; MSA-NEXT: st.h $w0, 0($4)1495;1496; MSA64N32-LABEL: slli_h:1497; MSA64N32: # %bb.0: # %entry1498; MSA64N32-NEXT: sll $1, $4, 01499; MSA64N32-NEXT: ld.h $w0, 0($1)1500; MSA64N32-NEXT: slli.h $w0, $w0, 31501; MSA64N32-NEXT: jr $ra1502; MSA64N32-NEXT: st.h $w0, 0($1)1503entry:1504 %a = load <8 x i16>, ptr %ptr, align 161505 %r = call <8 x i16> @llvm.mips.slli.h(<8 x i16> %a, i32 3)1506 store <8 x i16> %r, ptr %ptr, align 161507 ret void1508}1509 1510define void @splati_h(ptr %ptr) {1511; MSA-LABEL: splati_h:1512; MSA: # %bb.0: # %entry1513; MSA-NEXT: ld.h $w0, 0($4)1514; MSA-NEXT: splati.h $w0, $w0[3]1515; MSA-NEXT: jr $ra1516; MSA-NEXT: st.h $w0, 0($4)1517;1518; MSA64N32-LABEL: splati_h:1519; MSA64N32: # %bb.0: # %entry1520; MSA64N32-NEXT: sll $1, $4, 01521; MSA64N32-NEXT: ld.h $w0, 0($1)1522; MSA64N32-NEXT: splati.h $w0, $w0[3]1523; MSA64N32-NEXT: jr $ra1524; MSA64N32-NEXT: st.h $w0, 0($1)1525entry:1526 %a = load <8 x i16>, ptr %ptr, align 161527 %r = call <8 x i16> @llvm.mips.splati.h(<8 x i16> %a, i32 3)1528 store <8 x i16> %r, ptr %ptr, align 161529 ret void1530}1531 1532define void @srai_h(ptr %ptr) {1533; MSA-LABEL: srai_h:1534; MSA: # %bb.0: # %entry1535; MSA-NEXT: ld.h $w0, 0($4)1536; MSA-NEXT: srai.h $w0, $w0, 31537; MSA-NEXT: jr $ra1538; MSA-NEXT: st.h $w0, 0($4)1539;1540; MSA64N32-LABEL: srai_h:1541; MSA64N32: # %bb.0: # %entry1542; MSA64N32-NEXT: sll $1, $4, 01543; MSA64N32-NEXT: ld.h $w0, 0($1)1544; MSA64N32-NEXT: srai.h $w0, $w0, 31545; MSA64N32-NEXT: jr $ra1546; MSA64N32-NEXT: st.h $w0, 0($1)1547entry:1548 %a = load <8 x i16>, ptr %ptr, align 161549 %r = call <8 x i16> @llvm.mips.srai.h(<8 x i16> %a, i32 3)1550 store <8 x i16> %r, ptr %ptr, align 161551 ret void1552}1553 1554define void @srari_h(ptr %ptr) {1555; MSA-LABEL: srari_h:1556; MSA: # %bb.0: # %entry1557; MSA-NEXT: ld.h $w0, 0($4)1558; MSA-NEXT: srari.h $w0, $w0, 31559; MSA-NEXT: jr $ra1560; MSA-NEXT: st.h $w0, 0($4)1561;1562; MSA64N32-LABEL: srari_h:1563; MSA64N32: # %bb.0: # %entry1564; MSA64N32-NEXT: sll $1, $4, 01565; MSA64N32-NEXT: ld.h $w0, 0($1)1566; MSA64N32-NEXT: srari.h $w0, $w0, 31567; MSA64N32-NEXT: jr $ra1568; MSA64N32-NEXT: st.h $w0, 0($1)1569entry:1570 %a = load <8 x i16>, ptr %ptr, align 161571 %r = call <8 x i16> @llvm.mips.srari.h(<8 x i16> %a, i32 3)1572 store <8 x i16> %r, ptr %ptr, align 161573 ret void1574}1575 1576define void @srli_h(ptr %ptr) {1577; MSA-LABEL: srli_h:1578; MSA: # %bb.0: # %entry1579; MSA-NEXT: ld.h $w0, 0($4)1580; MSA-NEXT: srli.h $w0, $w0, 31581; MSA-NEXT: jr $ra1582; MSA-NEXT: st.h $w0, 0($4)1583;1584; MSA64N32-LABEL: srli_h:1585; MSA64N32: # %bb.0: # %entry1586; MSA64N32-NEXT: sll $1, $4, 01587; MSA64N32-NEXT: ld.h $w0, 0($1)1588; MSA64N32-NEXT: srli.h $w0, $w0, 31589; MSA64N32-NEXT: jr $ra1590; MSA64N32-NEXT: st.h $w0, 0($1)1591entry:1592 %a = load <8 x i16>, ptr %ptr, align 161593 %r = call <8 x i16> @llvm.mips.srli.h(<8 x i16> %a, i32 3)1594 store <8 x i16> %r, ptr %ptr, align 161595 ret void1596}1597 1598define void @srlri_h(ptr %ptr) {1599; MSA-LABEL: srlri_h:1600; MSA: # %bb.0: # %entry1601; MSA-NEXT: ld.h $w0, 0($4)1602; MSA-NEXT: srlri.h $w0, $w0, 31603; MSA-NEXT: jr $ra1604; MSA-NEXT: st.h $w0, 0($4)1605;1606; MSA64N32-LABEL: srlri_h:1607; MSA64N32: # %bb.0: # %entry1608; MSA64N32-NEXT: sll $1, $4, 01609; MSA64N32-NEXT: ld.h $w0, 0($1)1610; MSA64N32-NEXT: srlri.h $w0, $w0, 31611; MSA64N32-NEXT: jr $ra1612; MSA64N32-NEXT: st.h $w0, 0($1)1613entry:1614 %a = load <8 x i16>, ptr %ptr, align 161615 %r = call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %a, i32 3)1616 store <8 x i16> %r, ptr %ptr, align 161617 ret void1618}1619 1620define i32 @copy_s_b(ptr %ptr) {1621; MSA-LABEL: copy_s_b:1622; MSA: # %bb.0: # %entry1623; MSA-NEXT: ld.b $w0, 0($4)1624; MSA-NEXT: jr $ra1625; MSA-NEXT: copy_s.b $2, $w0[1]1626;1627; MSA64N32-LABEL: copy_s_b:1628; MSA64N32: # %bb.0: # %entry1629; MSA64N32-NEXT: sll $1, $4, 01630; MSA64N32-NEXT: ld.b $w0, 0($1)1631; MSA64N32-NEXT: jr $ra1632; MSA64N32-NEXT: copy_s.b $2, $w0[1]1633entry:1634 %a = load <16 x i8>, ptr %ptr, align 161635 %r = call i32 @llvm.mips.copy.s.b(<16 x i8> %a, i32 1)1636 ret i32 %r1637}1638define i32 @copy_s_h(ptr %ptr) {1639; MSA-LABEL: copy_s_h:1640; MSA: # %bb.0: # %entry1641; MSA-NEXT: ld.h $w0, 0($4)1642; MSA-NEXT: jr $ra1643; MSA-NEXT: copy_s.h $2, $w0[1]1644;1645; MSA64N32-LABEL: copy_s_h:1646; MSA64N32: # %bb.0: # %entry1647; MSA64N32-NEXT: sll $1, $4, 01648; MSA64N32-NEXT: ld.h $w0, 0($1)1649; MSA64N32-NEXT: jr $ra1650; MSA64N32-NEXT: copy_s.h $2, $w0[1]1651entry:1652 %a = load <8 x i16>, ptr %ptr, align 161653 %r = call i32 @llvm.mips.copy.s.h(<8 x i16> %a, i32 1)1654 ret i32 %r1655}1656define i32 @copy_s_w(ptr %ptr) {1657; MSA-LABEL: copy_s_w:1658; MSA: # %bb.0: # %entry1659; MSA-NEXT: ld.w $w0, 0($4)1660; MSA-NEXT: jr $ra1661; MSA-NEXT: copy_s.w $2, $w0[1]1662;1663; MSA64N32-LABEL: copy_s_w:1664; MSA64N32: # %bb.0: # %entry1665; MSA64N32-NEXT: sll $1, $4, 01666; MSA64N32-NEXT: ld.w $w0, 0($1)1667; MSA64N32-NEXT: jr $ra1668; MSA64N32-NEXT: copy_s.w $2, $w0[1]1669entry:1670 %a = load <4 x i32>, ptr %ptr, align 161671 %r = call i32 @llvm.mips.copy.s.w(<4 x i32> %a, i32 1)1672 ret i32 %r1673}1674define i32 @copy_u_b(ptr %ptr) {1675; MSA-LABEL: copy_u_b:1676; MSA: # %bb.0: # %entry1677; MSA-NEXT: ld.b $w0, 0($4)1678; MSA-NEXT: jr $ra1679; MSA-NEXT: copy_u.b $2, $w0[1]1680;1681; MSA64N32-LABEL: copy_u_b:1682; MSA64N32: # %bb.0: # %entry1683; MSA64N32-NEXT: sll $1, $4, 01684; MSA64N32-NEXT: ld.b $w0, 0($1)1685; MSA64N32-NEXT: jr $ra1686; MSA64N32-NEXT: copy_u.b $2, $w0[1]1687entry:1688 %a = load <16 x i8>, ptr %ptr, align 161689 %r = call i32 @llvm.mips.copy.u.b(<16 x i8> %a, i32 1)1690 ret i32 %r1691}1692define i32 @copy_u_h(ptr %ptr) {1693; MSA-LABEL: copy_u_h:1694; MSA: # %bb.0: # %entry1695; MSA-NEXT: ld.h $w0, 0($4)1696; MSA-NEXT: jr $ra1697; MSA-NEXT: copy_u.h $2, $w0[1]1698;1699; MSA64N32-LABEL: copy_u_h:1700; MSA64N32: # %bb.0: # %entry1701; MSA64N32-NEXT: sll $1, $4, 01702; MSA64N32-NEXT: ld.h $w0, 0($1)1703; MSA64N32-NEXT: jr $ra1704; MSA64N32-NEXT: copy_u.h $2, $w0[1]1705entry:1706 %a = load <8 x i16>, ptr %ptr, align 161707 %r = call i32 @llvm.mips.copy.u.h(<8 x i16> %a, i32 1)1708 ret i32 %r1709}1710define i32 @copy_u_w(ptr %ptr) {1711; MSA32-LABEL: copy_u_w:1712; MSA32: # %bb.0: # %entry1713; MSA32-NEXT: ld.w $w0, 0($4)1714; MSA32-NEXT: jr $ra1715; MSA32-NEXT: copy_s.w $2, $w0[1]1716;1717; MSA64N32-LABEL: copy_u_w:1718; MSA64N32: # %bb.0: # %entry1719; MSA64N32-NEXT: sll $1, $4, 01720; MSA64N32-NEXT: ld.w $w0, 0($1)1721; MSA64N32-NEXT: jr $ra1722; MSA64N32-NEXT: copy_u.w $2, $w0[1]1723;1724; MSA64N64-LABEL: copy_u_w:1725; MSA64N64: # %bb.0: # %entry1726; MSA64N64-NEXT: ld.w $w0, 0($4)1727; MSA64N64-NEXT: jr $ra1728; MSA64N64-NEXT: copy_u.w $2, $w0[1]1729entry:1730 %a = load <4 x i32>, ptr %ptr, align 161731 %r = call i32 @llvm.mips.copy.u.w(<4 x i32> %a, i32 1)1732 ret i32 %r1733}1734 1735define i64 @copy_s_d(ptr %ptr) {1736; MSA32-LABEL: copy_s_d:1737; MSA32: # %bb.0: # %entry1738; MSA32-NEXT: ld.w $w0, 0($4)1739; MSA32-NEXT: copy_s.w $2, $w0[2]1740; MSA32-NEXT: jr $ra1741; MSA32-NEXT: copy_s.w $3, $w0[3]1742;1743; MSA64N32-LABEL: copy_s_d:1744; MSA64N32: # %bb.0: # %entry1745; MSA64N32-NEXT: sll $1, $4, 01746; MSA64N32-NEXT: ld.d $w0, 0($1)1747; MSA64N32-NEXT: jr $ra1748; MSA64N32-NEXT: copy_s.d $2, $w0[1]1749;1750; MSA64N64-LABEL: copy_s_d:1751; MSA64N64: # %bb.0: # %entry1752; MSA64N64-NEXT: ld.d $w0, 0($4)1753; MSA64N64-NEXT: jr $ra1754; MSA64N64-NEXT: copy_s.d $2, $w0[1]1755entry:1756 %a = load <2 x i64>, ptr %ptr, align 161757 %r = call i64 @llvm.mips.copy.s.d(<2 x i64> %a, i32 1)1758 ret i64 %r1759}1760 1761define i64 @copy_u_d(ptr %ptr) {1762; MSA32-LABEL: copy_u_d:1763; MSA32: # %bb.0: # %entry1764; MSA32-NEXT: ld.w $w0, 0($4)1765; MSA32-NEXT: copy_s.w $2, $w0[2]1766; MSA32-NEXT: jr $ra1767; MSA32-NEXT: copy_s.w $3, $w0[3]1768;1769; MSA64N32-LABEL: copy_u_d:1770; MSA64N32: # %bb.0: # %entry1771; MSA64N32-NEXT: sll $1, $4, 01772; MSA64N32-NEXT: ld.d $w0, 0($1)1773; MSA64N32-NEXT: jr $ra1774; MSA64N32-NEXT: copy_s.d $2, $w0[1]1775;1776; MSA64N64-LABEL: copy_u_d:1777; MSA64N64: # %bb.0: # %entry1778; MSA64N64-NEXT: ld.d $w0, 0($4)1779; MSA64N64-NEXT: jr $ra1780; MSA64N64-NEXT: copy_s.d $2, $w0[1]1781entry:1782 %a = load <2 x i64>, ptr %ptr, align 161783 %r = call i64 @llvm.mips.copy.u.d(<2 x i64> %a, i32 1)1784 ret i64 %r1785}1786 1787define void @addvi_d(ptr %ptr) {1788; MSA-LABEL: addvi_d:1789; MSA: # %bb.0: # %entry1790; MSA-NEXT: ld.d $w0, 0($4)1791; MSA-NEXT: addvi.d $w0, $w0, 251792; MSA-NEXT: jr $ra1793; MSA-NEXT: st.d $w0, 0($4)1794;1795; MSA64N32-LABEL: addvi_d:1796; MSA64N32: # %bb.0: # %entry1797; MSA64N32-NEXT: sll $1, $4, 01798; MSA64N32-NEXT: ld.d $w0, 0($1)1799; MSA64N32-NEXT: addvi.d $w0, $w0, 251800; MSA64N32-NEXT: jr $ra1801; MSA64N32-NEXT: st.d $w0, 0($1)1802entry:1803 %a = load <2 x i64>, ptr %ptr, align 161804 %r = call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %a, i32 25)1805 store <2 x i64> %r, ptr %ptr, align 161806 ret void1807}1808 1809define void @bclri_d(ptr %ptr) {1810; MSA-LABEL: bclri_d:1811; MSA: # %bb.0: # %entry1812; MSA-NEXT: ld.d $w0, 0($4)1813; MSA-NEXT: bclri.d $w0, $w0, 161814; MSA-NEXT: jr $ra1815; MSA-NEXT: st.d $w0, 0($4)1816;1817; MSA64N32-LABEL: bclri_d:1818; MSA64N32: # %bb.0: # %entry1819; MSA64N32-NEXT: sll $1, $4, 01820; MSA64N32-NEXT: ld.d $w0, 0($1)1821; MSA64N32-NEXT: bclri.d $w0, $w0, 161822; MSA64N32-NEXT: jr $ra1823; MSA64N32-NEXT: st.d $w0, 0($1)1824entry:1825 %a = load <2 x i64>, ptr %ptr, align 161826 %r = call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %a, i32 16)1827 store <2 x i64> %r, ptr %ptr, align 161828 ret void1829}1830 1831define void @binsli_d(ptr %ptr, ptr %ptr2) {1832; MSA-LABEL: binsli_d:1833; MSA: # %bb.0: # %entry1834; MSA-NEXT: ld.d $w0, 0($5)1835; MSA-NEXT: ld.d $w1, 0($4)1836; MSA-NEXT: binsli.d $w1, $w0, 41837; MSA-NEXT: jr $ra1838; MSA-NEXT: st.d $w1, 0($4)1839;1840; MSA64N32-LABEL: binsli_d:1841; MSA64N32: # %bb.0: # %entry1842; MSA64N32-NEXT: sll $1, $4, 01843; MSA64N32-NEXT: sll $2, $5, 01844; MSA64N32-NEXT: ld.d $w0, 0($2)1845; MSA64N32-NEXT: ld.d $w1, 0($1)1846; MSA64N32-NEXT: binsli.d $w1, $w0, 41847; MSA64N32-NEXT: jr $ra1848; MSA64N32-NEXT: st.d $w1, 0($1)1849entry:1850 %a = load <2 x i64>, ptr %ptr, align 161851 %b = load <2 x i64>, ptr %ptr2, align 161852 %r = call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %a, <2 x i64> %b, i32 4)1853 store <2 x i64> %r, ptr %ptr, align 161854 ret void1855}1856 1857define void @binsri_d(ptr %ptr, ptr %ptr2) {1858; MSA-LABEL: binsri_d:1859; MSA: # %bb.0: # %entry1860; MSA-NEXT: ld.d $w0, 0($5)1861; MSA-NEXT: ld.d $w1, 0($4)1862; MSA-NEXT: binsri.d $w1, $w0, 51863; MSA-NEXT: jr $ra1864; MSA-NEXT: st.d $w1, 0($4)1865;1866; MSA64N32-LABEL: binsri_d:1867; MSA64N32: # %bb.0: # %entry1868; MSA64N32-NEXT: sll $1, $4, 01869; MSA64N32-NEXT: sll $2, $5, 01870; MSA64N32-NEXT: ld.d $w0, 0($2)1871; MSA64N32-NEXT: ld.d $w1, 0($1)1872; MSA64N32-NEXT: binsri.d $w1, $w0, 51873; MSA64N32-NEXT: jr $ra1874; MSA64N32-NEXT: st.d $w1, 0($1)1875entry:1876 %a = load <2 x i64>, ptr %ptr, align 161877 %b = load <2 x i64>, ptr %ptr2, align 161878 %r = call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %a, <2 x i64> %b, i32 5)1879 store <2 x i64> %r, ptr %ptr, align 161880 ret void1881}1882 1883define void @bnegi_d(ptr %ptr) {1884; MSA-LABEL: bnegi_d:1885; MSA: # %bb.0: # %entry1886; MSA-NEXT: ld.d $w0, 0($4)1887; MSA-NEXT: bnegi.d $w0, $w0, 91888; MSA-NEXT: jr $ra1889; MSA-NEXT: st.d $w0, 0($4)1890;1891; MSA64N32-LABEL: bnegi_d:1892; MSA64N32: # %bb.0: # %entry1893; MSA64N32-NEXT: sll $1, $4, 01894; MSA64N32-NEXT: ld.d $w0, 0($1)1895; MSA64N32-NEXT: bnegi.d $w0, $w0, 91896; MSA64N32-NEXT: jr $ra1897; MSA64N32-NEXT: st.d $w0, 0($1)1898entry:1899 %a = load <2 x i64>, ptr %ptr, align 161900 %r = call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %a, i32 9)1901 store <2 x i64> %r, ptr %ptr, align 161902 ret void1903}1904 1905define void @bseti_d(ptr %ptr) {1906; MSA-LABEL: bseti_d:1907; MSA: # %bb.0: # %entry1908; MSA-NEXT: ld.d $w0, 0($4)1909; MSA-NEXT: bseti.d $w0, $w0, 251910; MSA-NEXT: jr $ra1911; MSA-NEXT: st.d $w0, 0($4)1912;1913; MSA64N32-LABEL: bseti_d:1914; MSA64N32: # %bb.0: # %entry1915; MSA64N32-NEXT: sll $1, $4, 01916; MSA64N32-NEXT: ld.d $w0, 0($1)1917; MSA64N32-NEXT: bseti.d $w0, $w0, 251918; MSA64N32-NEXT: jr $ra1919; MSA64N32-NEXT: st.d $w0, 0($1)1920entry:1921 %a = load <2 x i64>, ptr %ptr, align 161922 %r = call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %a, i32 25)1923 store <2 x i64> %r, ptr %ptr, align 161924 ret void1925}1926 1927define void @clei_s_d(ptr %ptr) {1928; MSA-LABEL: clei_s_d:1929; MSA: # %bb.0: # %entry1930; MSA-NEXT: ld.d $w0, 0($4)1931; MSA-NEXT: clei_s.d $w0, $w0, 151932; MSA-NEXT: jr $ra1933; MSA-NEXT: st.d $w0, 0($4)1934;1935; MSA64N32-LABEL: clei_s_d:1936; MSA64N32: # %bb.0: # %entry1937; MSA64N32-NEXT: sll $1, $4, 01938; MSA64N32-NEXT: ld.d $w0, 0($1)1939; MSA64N32-NEXT: clei_s.d $w0, $w0, 151940; MSA64N32-NEXT: jr $ra1941; MSA64N32-NEXT: st.d $w0, 0($1)1942entry:1943 %a = load <2 x i64>, ptr %ptr, align 161944 %r = call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %a, i32 15)1945 store <2 x i64> %r, ptr %ptr, align 161946 ret void1947}1948 1949define void @clei_u_d(ptr %ptr) {1950; MSA-LABEL: clei_u_d:1951; MSA: # %bb.0: # %entry1952; MSA-NEXT: ld.d $w0, 0($4)1953; MSA-NEXT: clei_u.d $w0, $w0, 251954; MSA-NEXT: jr $ra1955; MSA-NEXT: st.d $w0, 0($4)1956;1957; MSA64N32-LABEL: clei_u_d:1958; MSA64N32: # %bb.0: # %entry1959; MSA64N32-NEXT: sll $1, $4, 01960; MSA64N32-NEXT: ld.d $w0, 0($1)1961; MSA64N32-NEXT: clei_u.d $w0, $w0, 251962; MSA64N32-NEXT: jr $ra1963; MSA64N32-NEXT: st.d $w0, 0($1)1964entry:1965 %a = load <2 x i64>, ptr %ptr, align 161966 %r = call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %a, i32 25)1967 store <2 x i64> %r, ptr %ptr, align 161968 ret void1969}1970 1971define void @clti_s_d(ptr %ptr) {1972; MSA-LABEL: clti_s_d:1973; MSA: # %bb.0: # %entry1974; MSA-NEXT: ld.d $w0, 0($4)1975; MSA-NEXT: clti_s.d $w0, $w0, 151976; MSA-NEXT: jr $ra1977; MSA-NEXT: st.d $w0, 0($4)1978;1979; MSA64N32-LABEL: clti_s_d:1980; MSA64N32: # %bb.0: # %entry1981; MSA64N32-NEXT: sll $1, $4, 01982; MSA64N32-NEXT: ld.d $w0, 0($1)1983; MSA64N32-NEXT: clti_s.d $w0, $w0, 151984; MSA64N32-NEXT: jr $ra1985; MSA64N32-NEXT: st.d $w0, 0($1)1986entry:1987 %a = load <2 x i64>, ptr %ptr, align 161988 %r = call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %a, i32 15)1989 store <2 x i64> %r, ptr %ptr, align 161990 ret void1991}1992 1993define void @clti_u_d(ptr %ptr) {1994; MSA-LABEL: clti_u_d:1995; MSA: # %bb.0: # %entry1996; MSA-NEXT: ld.d $w0, 0($4)1997; MSA-NEXT: clti_u.d $w0, $w0, 251998; MSA-NEXT: jr $ra1999; MSA-NEXT: st.d $w0, 0($4)2000;2001; MSA64N32-LABEL: clti_u_d:2002; MSA64N32: # %bb.0: # %entry2003; MSA64N32-NEXT: sll $1, $4, 02004; MSA64N32-NEXT: ld.d $w0, 0($1)2005; MSA64N32-NEXT: clti_u.d $w0, $w0, 252006; MSA64N32-NEXT: jr $ra2007; MSA64N32-NEXT: st.d $w0, 0($1)2008entry:2009 %a = load <2 x i64>, ptr %ptr, align 162010 %r = call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %a, i32 25)2011 store <2 x i64> %r, ptr %ptr, align 162012 ret void2013}2014 2015define void @ldi_d(ptr %ptr) {2016; MSA32-LABEL: ldi_d:2017; MSA32: # %bb.0: # %entry2018; MSA32-NEXT: ldi.d $w0, 32019; MSA32-NEXT: jr $ra2020; MSA32-NEXT: st.w $w0, 0($4)2021;2022; MSA64N32-LABEL: ldi_d:2023; MSA64N32: # %bb.0: # %entry2024; MSA64N32-NEXT: sll $1, $4, 02025; MSA64N32-NEXT: ldi.d $w0, 32026; MSA64N32-NEXT: jr $ra2027; MSA64N32-NEXT: st.d $w0, 0($1)2028;2029; MSA64N64-LABEL: ldi_d:2030; MSA64N64: # %bb.0: # %entry2031; MSA64N64-NEXT: ldi.d $w0, 32032; MSA64N64-NEXT: jr $ra2033; MSA64N64-NEXT: st.d $w0, 0($4)2034entry:2035 %r = call <2 x i64> @llvm.mips.ldi.d(i32 3)2036 store <2 x i64> %r, ptr %ptr, align 162037 ret void2038}2039 2040define void @maxi_s_d(ptr %ptr) {2041; MSA-LABEL: maxi_s_d:2042; MSA: # %bb.0: # %entry2043; MSA-NEXT: ld.d $w0, 0($4)2044; MSA-NEXT: maxi_s.d $w0, $w0, 22045; MSA-NEXT: jr $ra2046; MSA-NEXT: st.d $w0, 0($4)2047;2048; MSA64N32-LABEL: maxi_s_d:2049; MSA64N32: # %bb.0: # %entry2050; MSA64N32-NEXT: sll $1, $4, 02051; MSA64N32-NEXT: ld.d $w0, 0($1)2052; MSA64N32-NEXT: maxi_s.d $w0, $w0, 22053; MSA64N32-NEXT: jr $ra2054; MSA64N32-NEXT: st.d $w0, 0($1)2055entry:2056 %a = load <2 x i64>, ptr %ptr, align 162057 %r = call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %a, i32 2)2058 store <2 x i64> %r, ptr %ptr, align 162059 ret void2060}2061 2062define void @maxi_u_d(ptr %ptr) {2063; MSA-LABEL: maxi_u_d:2064; MSA: # %bb.0: # %entry2065; MSA-NEXT: ld.d $w0, 0($4)2066; MSA-NEXT: maxi_u.d $w0, $w0, 22067; MSA-NEXT: jr $ra2068; MSA-NEXT: st.d $w0, 0($4)2069;2070; MSA64N32-LABEL: maxi_u_d:2071; MSA64N32: # %bb.0: # %entry2072; MSA64N32-NEXT: sll $1, $4, 02073; MSA64N32-NEXT: ld.d $w0, 0($1)2074; MSA64N32-NEXT: maxi_u.d $w0, $w0, 22075; MSA64N32-NEXT: jr $ra2076; MSA64N32-NEXT: st.d $w0, 0($1)2077entry:2078 %a = load <2 x i64>, ptr %ptr, align 162079 %r = call <2 x i64> @llvm.mips.maxi.u.d(<2 x i64> %a, i32 2)2080 store <2 x i64> %r, ptr %ptr, align 162081 ret void2082}2083 2084define void @mini_s_d(ptr %ptr) {2085; MSA-LABEL: mini_s_d:2086; MSA: # %bb.0: # %entry2087; MSA-NEXT: ld.d $w0, 0($4)2088; MSA-NEXT: mini_s.d $w0, $w0, 22089; MSA-NEXT: jr $ra2090; MSA-NEXT: st.d $w0, 0($4)2091;2092; MSA64N32-LABEL: mini_s_d:2093; MSA64N32: # %bb.0: # %entry2094; MSA64N32-NEXT: sll $1, $4, 02095; MSA64N32-NEXT: ld.d $w0, 0($1)2096; MSA64N32-NEXT: mini_s.d $w0, $w0, 22097; MSA64N32-NEXT: jr $ra2098; MSA64N32-NEXT: st.d $w0, 0($1)2099entry:2100 %a = load <2 x i64>, ptr %ptr, align 162101 %r = call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %a, i32 2)2102 store <2 x i64> %r, ptr %ptr, align 162103 ret void2104}2105 2106define void @mini_u_d(ptr %ptr) {2107; MSA-LABEL: mini_u_d:2108; MSA: # %bb.0: # %entry2109; MSA-NEXT: ld.d $w0, 0($4)2110; MSA-NEXT: mini_u.d $w0, $w0, 22111; MSA-NEXT: jr $ra2112; MSA-NEXT: st.d $w0, 0($4)2113;2114; MSA64N32-LABEL: mini_u_d:2115; MSA64N32: # %bb.0: # %entry2116; MSA64N32-NEXT: sll $1, $4, 02117; MSA64N32-NEXT: ld.d $w0, 0($1)2118; MSA64N32-NEXT: mini_u.d $w0, $w0, 22119; MSA64N32-NEXT: jr $ra2120; MSA64N32-NEXT: st.d $w0, 0($1)2121entry:2122 %a = load <2 x i64>, ptr %ptr, align 162123 %r = call <2 x i64> @llvm.mips.mini.u.d(<2 x i64> %a, i32 2)2124 store <2 x i64> %r, ptr %ptr, align 162125 ret void2126}2127 2128define void @sldi_d(ptr %ptr) {2129; MSA-LABEL: sldi_d:2130; MSA: # %bb.0: # %entry2131; MSA-NEXT: ld.d $w0, 0($4)2132; MSA-NEXT: sldi.d $w0, $w0[1]2133; MSA-NEXT: jr $ra2134; MSA-NEXT: st.d $w0, 0($4)2135;2136; MSA64N32-LABEL: sldi_d:2137; MSA64N32: # %bb.0: # %entry2138; MSA64N32-NEXT: sll $1, $4, 02139; MSA64N32-NEXT: ld.d $w0, 0($1)2140; MSA64N32-NEXT: sldi.d $w0, $w0[1]2141; MSA64N32-NEXT: jr $ra2142; MSA64N32-NEXT: st.d $w0, 0($1)2143entry:2144 %a = load <2 x i64>, ptr %ptr, align 162145 %r = call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %a, <2 x i64> %a, i32 1)2146 store <2 x i64> %r, ptr %ptr, align 162147 ret void2148}2149 2150define void @slli_d(ptr %ptr) {2151; MSA-LABEL: slli_d:2152; MSA: # %bb.0: # %entry2153; MSA-NEXT: ld.d $w0, 0($4)2154; MSA-NEXT: slli.d $w0, $w0, 32155; MSA-NEXT: jr $ra2156; MSA-NEXT: st.d $w0, 0($4)2157;2158; MSA64N32-LABEL: slli_d:2159; MSA64N32: # %bb.0: # %entry2160; MSA64N32-NEXT: sll $1, $4, 02161; MSA64N32-NEXT: ld.d $w0, 0($1)2162; MSA64N32-NEXT: slli.d $w0, $w0, 32163; MSA64N32-NEXT: jr $ra2164; MSA64N32-NEXT: st.d $w0, 0($1)2165entry:2166 %a = load <2 x i64>, ptr %ptr, align 162167 %r = call <2 x i64> @llvm.mips.slli.d(<2 x i64> %a, i32 3)2168 store <2 x i64> %r, ptr %ptr, align 162169 ret void2170}2171 2172define void @srai_d(ptr %ptr) {2173; MSA-LABEL: srai_d:2174; MSA: # %bb.0: # %entry2175; MSA-NEXT: ld.d $w0, 0($4)2176; MSA-NEXT: srai.d $w0, $w0, 32177; MSA-NEXT: jr $ra2178; MSA-NEXT: st.d $w0, 0($4)2179;2180; MSA64N32-LABEL: srai_d:2181; MSA64N32: # %bb.0: # %entry2182; MSA64N32-NEXT: sll $1, $4, 02183; MSA64N32-NEXT: ld.d $w0, 0($1)2184; MSA64N32-NEXT: srai.d $w0, $w0, 32185; MSA64N32-NEXT: jr $ra2186; MSA64N32-NEXT: st.d $w0, 0($1)2187entry:2188 %a = load <2 x i64>, ptr %ptr, align 162189 %r = call <2 x i64> @llvm.mips.srai.d(<2 x i64> %a, i32 3)2190 store <2 x i64> %r, ptr %ptr, align 162191 ret void2192}2193 2194define void @srari_d(ptr %ptr) {2195; MSA-LABEL: srari_d:2196; MSA: # %bb.0: # %entry2197; MSA-NEXT: ld.d $w0, 0($4)2198; MSA-NEXT: srari.d $w0, $w0, 32199; MSA-NEXT: jr $ra2200; MSA-NEXT: st.d $w0, 0($4)2201;2202; MSA64N32-LABEL: srari_d:2203; MSA64N32: # %bb.0: # %entry2204; MSA64N32-NEXT: sll $1, $4, 02205; MSA64N32-NEXT: ld.d $w0, 0($1)2206; MSA64N32-NEXT: srari.d $w0, $w0, 32207; MSA64N32-NEXT: jr $ra2208; MSA64N32-NEXT: st.d $w0, 0($1)2209entry:2210 %a = load <2 x i64>, ptr %ptr, align 162211 %r = call <2 x i64> @llvm.mips.srari.d(<2 x i64> %a, i32 3)2212 store <2 x i64> %r, ptr %ptr, align 162213 ret void2214}2215 2216define void @srli_d(ptr %ptr) {2217; MSA-LABEL: srli_d:2218; MSA: # %bb.0: # %entry2219; MSA-NEXT: ld.d $w0, 0($4)2220; MSA-NEXT: srli.d $w0, $w0, 32221; MSA-NEXT: jr $ra2222; MSA-NEXT: st.d $w0, 0($4)2223;2224; MSA64N32-LABEL: srli_d:2225; MSA64N32: # %bb.0: # %entry2226; MSA64N32-NEXT: sll $1, $4, 02227; MSA64N32-NEXT: ld.d $w0, 0($1)2228; MSA64N32-NEXT: srli.d $w0, $w0, 32229; MSA64N32-NEXT: jr $ra2230; MSA64N32-NEXT: st.d $w0, 0($1)2231entry:2232 %a = load <2 x i64>, ptr %ptr, align 162233 %r = call <2 x i64> @llvm.mips.srli.d(<2 x i64> %a, i32 3)2234 store <2 x i64> %r, ptr %ptr, align 162235 ret void2236}2237 2238define void @srlri_d(ptr %ptr) {2239; MSA-LABEL: srlri_d:2240; MSA: # %bb.0: # %entry2241; MSA-NEXT: ld.d $w0, 0($4)2242; MSA-NEXT: srlri.d $w0, $w0, 32243; MSA-NEXT: jr $ra2244; MSA-NEXT: st.d $w0, 0($4)2245;2246; MSA64N32-LABEL: srlri_d:2247; MSA64N32: # %bb.0: # %entry2248; MSA64N32-NEXT: sll $1, $4, 02249; MSA64N32-NEXT: ld.d $w0, 0($1)2250; MSA64N32-NEXT: srlri.d $w0, $w0, 32251; MSA64N32-NEXT: jr $ra2252; MSA64N32-NEXT: st.d $w0, 0($1)2253entry:2254 %a = load <2 x i64>, ptr %ptr, align 162255 %r = call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %a, i32 3)2256 store <2 x i64> %r, ptr %ptr, align 162257 ret void2258}2259 2260define void @ld_d2(ptr %ptr, ptr %ldptr) {2261; MSA32-LABEL: ld_d2:2262; MSA32: # %bb.0: # %entry2263; MSA32-NEXT: addiu $1, $5, 40962264; MSA32-NEXT: ld.d $w0, 0($1)2265; MSA32-NEXT: jr $ra2266; MSA32-NEXT: st.d $w0, 0($4)2267;2268; MSA64N32-LABEL: ld_d2:2269; MSA64N32: # %bb.0: # %entry2270; MSA64N32-NEXT: sll $1, $4, 02271; MSA64N32-NEXT: sll $2, $5, 02272; MSA64N32-NEXT: addiu $2, $2, 40962273; MSA64N32-NEXT: ld.d $w0, 0($2)2274; MSA64N32-NEXT: jr $ra2275; MSA64N32-NEXT: st.d $w0, 0($1)2276;2277; MSA64N64-LABEL: ld_d2:2278; MSA64N64: # %bb.0: # %entry2279; MSA64N64-NEXT: daddiu $1, $5, 40962280; MSA64N64-NEXT: ld.d $w0, 0($1)2281; MSA64N64-NEXT: jr $ra2282; MSA64N64-NEXT: st.d $w0, 0($4)2283entry:2284 %a = call <2 x i64> @llvm.mips.ld.d(ptr %ldptr, i32 4096)2285 store <2 x i64> %a, ptr %ptr, align 162286 ret void2287}2288 2289declare <8 x i16> @llvm.mips.ldi.h(i32)2290declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32)2291declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32)2292declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32)2293declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32)2294declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32)2295declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32)2296declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32)2297declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32)2298declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32)2299declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32)2300declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32)2301declare <8 x i16> @llvm.mips.maxi.u.h(<8 x i16>, i32)2302declare <8 x i16> @llvm.mips.mini.s.h(<8 x i16>, i32)2303declare <8 x i16> @llvm.mips.mini.u.h(<8 x i16>, i32)2304declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32)2305declare <8 x i16> @llvm.mips.slli.h(<8 x i16>, i32)2306declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32)2307declare <8 x i16> @llvm.mips.srai.h(<8 x i16>, i32)2308declare <8 x i16> @llvm.mips.srari.h(<8 x i16>, i32)2309declare <8 x i16> @llvm.mips.srli.h(<8 x i16>, i32)2310declare <8 x i16> @llvm.mips.srlri.h(<8 x i16>, i32)2311declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32)2312declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32)2313declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32)2314declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32)2315declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32)2316declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32)2317declare <4 x i32> @llvm.mips.ldi.w(i32)2318declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32)2319declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32)2320declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32)2321declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32)2322declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32)2323declare <4 x i32> @llvm.mips.maxi.u.w(<4 x i32>, i32)2324declare <4 x i32> @llvm.mips.mini.s.w(<4 x i32>, i32)2325declare <4 x i32> @llvm.mips.mini.u.w(<4 x i32>, i32)2326declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32)2327declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32)2328declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32)2329declare <4 x i32> @llvm.mips.srai.w(<4 x i32>, i32)2330declare <4 x i32> @llvm.mips.srari.w(<4 x i32>, i32)2331declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32)2332declare <4 x i32> @llvm.mips.srlri.w(<4 x i32>, i32)2333declare <2 x i64> @llvm.mips.ldi.d(i32)2334declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32)2335declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32)2336declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32)2337declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32)2338declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32)2339declare <2 x i64> @llvm.mips.bseti.d(<2 x i64>, i32)2340declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32)2341declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32)2342declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32)2343declare <2 x i64> @llvm.mips.clti.u.d(<2 x i64>, i32)2344declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32)2345declare <2 x i64> @llvm.mips.maxi.u.d(<2 x i64>, i32)2346declare <2 x i64> @llvm.mips.mini.s.d(<2 x i64>, i32)2347declare <2 x i64> @llvm.mips.mini.u.d(<2 x i64>, i32)2348declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32)2349declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32)2350declare <2 x i64> @llvm.mips.splati.d(<2 x i64>, i32)2351declare <2 x i64> @llvm.mips.srai.d(<2 x i64>, i32)2352declare <2 x i64> @llvm.mips.srari.d(<2 x i64>, i32)2353declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32)2354declare <2 x i64> @llvm.mips.srlri.d(<2 x i64>, i32)2355declare <16 x i8> @llvm.mips.ldi.b(i32)2356declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32)2357declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32)2358declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32)2359declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32)2360declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32)2361declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32)2362declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32)2363declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32)2364declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32)2365declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32)2366declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32)2367declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32)2368declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32)2369declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32)2370declare <16 x i8> @llvm.mips.maxi.u.b(<16 x i8>, i32)2371declare <16 x i8> @llvm.mips.mini.s.b(<16 x i8>, i32)2372declare <16 x i8> @llvm.mips.mini.u.b(<16 x i8>, i32)2373declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32)2374declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32)2375declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32)2376declare <16 x i8> @llvm.mips.slli.b(<16 x i8>, i32)2377declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32)2378declare <16 x i8> @llvm.mips.srai.b(<16 x i8>, i32)2379declare <16 x i8> @llvm.mips.srari.b(<16 x i8>, i32)2380declare <16 x i8> @llvm.mips.srli.b(<16 x i8>, i32)2381declare <16 x i8> @llvm.mips.srlri.b(<16 x i8>, i32)2382declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32)2383declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32)2384declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32)2385declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32)2386declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32)2387declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32)2388declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32)2389declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32)2390declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32)2391declare <16 x i8> @llvm.mips.ld.b(ptr, i32)2392declare <8 x i16> @llvm.mips.ld.h(ptr, i32)2393declare <4 x i32> @llvm.mips.ld.w(ptr, i32)2394declare <2 x i64> @llvm.mips.ld.d(ptr, i32)2395declare void @llvm.mips.st.b(<16 x i8>, ptr, i32)2396declare void @llvm.mips.st.h(<8 x i16>, ptr, i32)2397declare void @llvm.mips.st.w(<4 x i32>, ptr, i32)2398declare void @llvm.mips.st.d(<2 x i64>, ptr, i32)2399