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1; RUN: llc -mtriple=mips < %s2; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s3; RUN: llc -mtriple=mipsel < %s4; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s5 6; This test is based on an llvm-stress generated test case with seed=4496096557 8; This test originally failed for MSA with a9; "Comparison requires equal bit widths" assertion.10; The legalizer legalized ; the <4 x i8>'s into <4 x i32>'s, then a call to11; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt12; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The13; assertion occurred when trying to check the values were bitwise inverses of14; each-other.15;16; It should at least successfully build.17 18define void @autogen_SD449609655(i8) {19BB:20 %Cmp = icmp ult i8 -3, %021 br label %CF7822 23CF78: ; preds = %CF81, %CF78, %BB24 %Sl31 = select i1 %Cmp, <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8> zeroinitializer25 br i1 undef, label %CF78, label %CF8126 27CF81: ; preds = %CF7828 br i1 undef, label %CF78, label %CF8029 30CF80: ; preds = %CF8131 %I59 = insertelement <4 x i8> %Sl31, i8 undef, i32 132 ret void33}34