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1; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s2 3define void @ashr_v4i32(ptr %c) nounwind {4 ; CHECK-LABEL: ashr_v4i32:5 6 %1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,7 <i32 0, i32 1, i32 2, i32 3>8 ; CHECK-NOT: sra9 ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 110 ; CHECK-NOT: sra11 store volatile <4 x i32> %1, ptr %c12 ; CHECK-DAG: st.w [[R1]], 0($4)13 14 %2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,15 <i32 0, i32 1, i32 2, i32 3>16 ; CHECK-NOT: sra17 ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -218 ; CHECK-NOT: sra19 store volatile <4 x i32> %2, ptr %c20 ; CHECK-DAG: st.w [[R1]], 0($4)21 22 ret void23 ; CHECK-LABEL: .size ashr_v4i3224}25 26define void @lshr_v4i32(ptr %c) nounwind {27 ; CHECK-LABEL: lshr_v4i32:28 29 %1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,30 <i32 0, i32 1, i32 2, i32 3>31 ; CHECK-NOT: srl32 ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 133 ; CHECK-NOT: srl34 store volatile <4 x i32> %1, ptr %c35 ; CHECK-DAG: st.w [[R1]], 0($4)36 37 %2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,38 <i32 0, i32 1, i32 2, i32 3>39 ; CHECK-NOT: srl40 ; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($41 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])42 ; CHECK-NOT: srl43 store volatile <4 x i32> %2, ptr %c44 ; CHECK-DAG: st.w [[R1]], 0($4)45 46 ret void47 ; CHECK-LABEL: .size lshr_v4i3248}49 50define void @shl_v4i32(ptr %c) nounwind {51 ; CHECK-LABEL: shl_v4i32:52 53 %1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>,54 <i32 0, i32 1, i32 2, i32 3>55 ; CHECK-NOT: sll56 ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 857 ; CHECK-NOT: sll58 store volatile <4 x i32> %1, ptr %c59 ; CHECK-DAG: st.w [[R1]], 0($4)60 61 %2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>,62 <i32 0, i32 1, i32 2, i32 3>63 ; CHECK-NOT: sll64 ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -865 ; CHECK-NOT: sll66 store volatile <4 x i32> %2, ptr %c67 ; CHECK-DAG: st.w [[R1]], 0($4)68 69 ret void70 ; CHECK-LABEL: .size shl_v4i3271}72