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1; Test whether the following functions, with vectors featuring negative or values larger than the element2; bit size have their results of operations generated correctly when placed into constant pools3 4; RUN: llc -mtriple=mips64-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \5; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s6; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \7; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s8; RUN: llc -mtriple=mips64el-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \9; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s10; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \11; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s12 13@llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 1614 15define void @llvm_mips_bclr_w_test_const_vec() nounwind {16entry:17 %0 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> <i32 2147483649, i32 2147483649, i32 7, i32 7>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)18 store <4 x i32> %0, ptr @llvm_mips_bclr_w_test_const_vec_res19 ret void20}21 22declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind23 24; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:25; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:26; ALL: .4byte 1 # 0x127; ALL: .4byte 1 # 0x128; ALL: .4byte 3 # 0x329; ALL: .4byte 3 # 0x330; ALL-LABEL: llvm_mips_bclr_w_test_const_vec:31; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])32; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])33; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bclr_w_test_const_vec_res)($[[R1]])34; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])35; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])36; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bclr_w_test_const_vec_res)($[[R1]])37; ALL: ld.w $w0, 0($[[R2]])38; ALL: st.w $w0, 0($[[R3]])39 40 41@llvm_mips_bneg_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 1642 43define void @llvm_mips_bneg_w_test_const_vec() nounwind {44entry:45 %0 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> <i32 2147483649, i32 2147483649, i32 7, i32 7>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)46 store <4 x i32> %0, ptr @llvm_mips_bneg_w_test_const_vec_res47 ret void48}49 50declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind51 52; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:53; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:54; ALL: .4byte 1 # 0x155; ALL: .4byte 1 # 0x156; ALL: .4byte 3 # 0x357; ALL: .4byte 3 # 0x358; ALL-LABEL: llvm_mips_bneg_w_test_const_vec:59; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])60; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])61; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bneg_w_test_const_vec_res)($[[R1]])62; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])63; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])64; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bneg_w_test_const_vec_res)($[[R1]])65; ALL: ld.w $w0, 0($[[R2]])66; ALL: st.w $w0, 0($[[R3]])67 68 69@llvm_mips_bset_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 1670 71define void @llvm_mips_bset_w_test_const_vec() nounwind {72entry:73 %0 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)74 store <4 x i32> %0, ptr @llvm_mips_bset_w_test_const_vec_res75 ret void76}77 78declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind79 80; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:81; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:82; ALL: .4byte 2147483648 # 0x8000000083; ALL: .4byte 2147483648 # 0x8000000084; ALL: .4byte 4 # 0x485; ALL: .4byte 4 # 0x486; ALL-LABEL: llvm_mips_bset_w_test_const_vec:87; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])88; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])89; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bset_w_test_const_vec_res)($[[R1]])90; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])91; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])92; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bset_w_test_const_vec_res)($[[R1]])93; ALL: ld.w $w0, 0($[[R2]])94; ALL: st.w $w0, 0($[[R3]])95 96@llvm_mips_sll_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 1697 98define void @llvm_mips_sll_w_test_const_vec() nounwind {99entry:100 %0 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)101 store <4 x i32> %0, ptr @llvm_mips_sll_w_test_const_vec_res102 ret void103}104 105declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind106 107; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:108; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:109; ALL: .4byte 2147483648 # 0x80000000110; ALL: .4byte 2147483648 # 0x80000000111; ALL: .4byte 4 # 0x4112; ALL: .4byte 4 # 0x4113; ALL-LABEL: llvm_mips_sll_w_test_const_vec:114; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])115; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])116; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sll_w_test_const_vec_res)($[[R1]])117; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])118; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])119; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sll_w_test_const_vec_res)($[[R1]])120; ALL: ld.w $w0, 0($[[R2]])121; ALL: st.w $w0, 0($[[R3]])122 123@llvm_mips_sra_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16124 125define void @llvm_mips_sra_w_test_const_vec() nounwind {126entry:127 %0 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> <i32 -16, i32 16, i32 16, i32 16>, <4 x i32> <i32 2, i32 -30, i32 33, i32 1>)128 store <4 x i32> %0, ptr @llvm_mips_sra_w_test_const_vec_res129 ret void130}131 132declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind133 134; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:135; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:136; ALL: .4byte 4294967292 # 0xfffffffc137; ALL: .4byte 4 # 0x4138; ALL: .4byte 8 # 0x8139; ALL: .4byte 8 # 0x8140; ALL-LABEL: llvm_mips_sra_w_test_const_vec:141; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])142; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])143; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sra_w_test_const_vec_res)($[[R1]])144; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])145; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])146; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sra_w_test_const_vec_res)($[[R1]])147; ALL: ld.w $w0, 0($[[R2]])148; ALL: st.w $w0, 0($[[R3]])149 150@llvm_mips_srl_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16151 152define void @llvm_mips_srl_w_test_const_vec() nounwind {153entry:154 %0 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> <i32 -16, i32 16, i32 16, i32 16>, <4 x i32> <i32 2, i32 -30, i32 33, i32 1>)155 store <4 x i32> %0, ptr @llvm_mips_srl_w_test_const_vec_res156 ret void157}158 159declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind160 161; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:162; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:163; ALL: .4byte 1073741820 # 0x3ffffffc164; ALL: .4byte 4 # 0x4165; ALL: .4byte 8 # 0x8166; ALL: .4byte 8 # 0x8167; ALL-LABEL: llvm_mips_srl_w_test_const_vec:168; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])169; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])170; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_srl_w_test_const_vec_res)($[[R1]])171; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])172; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])173; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_srl_w_test_const_vec_res)($[[R1]])174; ALL: ld.w $w0, 0($[[R2]])175; ALL: st.w $w0, 0($[[R3]])176