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1; Test the absence of the andi.b / and.v instructions2 3; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s4; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5 6@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 167@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 168@llvm_mips_bclr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 169 10define void @llvm_mips_bclr_b_test() nounwind {11entry:12 %0 = load <16 x i8>, ptr @llvm_mips_bclr_b_ARG113 %1 = load <16 x i8>, ptr @llvm_mips_bclr_b_ARG214 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1)15 store <16 x i8> %2, ptr @llvm_mips_bclr_b_RES16 ret void17}18 19declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind20 21; CHECK-LABEL: llvm_mips_bclr_b_test:22; CHECK-NOT: andi.b23; CHECK: bclr.b24 25@llvm_mips_bclr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1626@llvm_mips_bclr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1627@llvm_mips_bclr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1628 29define void @llvm_mips_bclr_h_test() nounwind {30entry:31 %0 = load <8 x i16>, ptr @llvm_mips_bclr_h_ARG132 %1 = load <8 x i16>, ptr @llvm_mips_bclr_h_ARG233 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1)34 store <8 x i16> %2, ptr @llvm_mips_bclr_h_RES35 ret void36}37 38declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind39 40; CHECK-LABEL: llvm_mips_bclr_h_test:41; CHECK-NOT: and.v42; CHECK: bclr.h43 44@llvm_mips_bclr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1645@llvm_mips_bclr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1646@llvm_mips_bclr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1647 48define void @llvm_mips_bclr_w_test() nounwind {49entry:50 %0 = load <4 x i32>, ptr @llvm_mips_bclr_w_ARG151 %1 = load <4 x i32>, ptr @llvm_mips_bclr_w_ARG252 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1)53 store <4 x i32> %2, ptr @llvm_mips_bclr_w_RES54 ret void55}56 57declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind58 59; CHECK-LABEL: llvm_mips_bclr_w_test:60; CHECK-NOT: and.v61; CHECK: bclr.w62 63@llvm_mips_bclr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1664@llvm_mips_bclr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1665@llvm_mips_bclr_d_RES = global <2 x i64> <i64 0, i64 0>, align 1666 67define void @llvm_mips_bclr_d_test() nounwind {68entry:69 %0 = load <2 x i64>, ptr @llvm_mips_bclr_d_ARG170 %1 = load <2 x i64>, ptr @llvm_mips_bclr_d_ARG271 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1)72 store <2 x i64> %2, ptr @llvm_mips_bclr_d_RES73 ret void74}75 76declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind77 78; CHECK-LABEL: llvm_mips_bclr_d_test:79; CHECK-NOT: and.v80; CHECK: bclr.d81 82@llvm_mips_bneg_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1683@llvm_mips_bneg_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1684@llvm_mips_bneg_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1685 86define void @llvm_mips_bneg_b_test() nounwind {87entry:88 %0 = load <16 x i8>, ptr @llvm_mips_bneg_b_ARG189 %1 = load <16 x i8>, ptr @llvm_mips_bneg_b_ARG290 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)91 store <16 x i8> %2, ptr @llvm_mips_bneg_b_RES92 ret void93}94 95declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind96 97; CHECK-LABEL: llvm_mips_bneg_b_test:98; CHECK-NOT: andi.b99; CHECK: bneg.b100 101@llvm_mips_bneg_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16102@llvm_mips_bneg_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16103@llvm_mips_bneg_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16104 105define void @llvm_mips_bneg_h_test() nounwind {106entry:107 %0 = load <8 x i16>, ptr @llvm_mips_bneg_h_ARG1108 %1 = load <8 x i16>, ptr @llvm_mips_bneg_h_ARG2109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)110 store <8 x i16> %2, ptr @llvm_mips_bneg_h_RES111 ret void112}113 114declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind115 116; CHECK-LABEL: llvm_mips_bneg_h_test:117; CHECK-NOT: and.v118; CHECK: bneg.h119 120@llvm_mips_bneg_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16121@llvm_mips_bneg_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16122@llvm_mips_bneg_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16123 124define void @llvm_mips_bneg_w_test() nounwind {125entry:126 %0 = load <4 x i32>, ptr @llvm_mips_bneg_w_ARG1127 %1 = load <4 x i32>, ptr @llvm_mips_bneg_w_ARG2128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)129 store <4 x i32> %2, ptr @llvm_mips_bneg_w_RES130 ret void131}132 133declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind134 135; CHECK-LABEL: llvm_mips_bneg_w_test:136; CHECK-NOT: and.v137; CHECK: bneg.w138 139@llvm_mips_bneg_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16140@llvm_mips_bneg_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16141@llvm_mips_bneg_d_RES = global <2 x i64> <i64 0, i64 0>, align 16142 143define void @llvm_mips_bneg_d_test() nounwind {144entry:145 %0 = load <2 x i64>, ptr @llvm_mips_bneg_d_ARG1146 %1 = load <2 x i64>, ptr @llvm_mips_bneg_d_ARG2147 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)148 store <2 x i64> %2, ptr @llvm_mips_bneg_d_RES149 ret void150}151 152declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind153 154; CHECK-LABEL: llvm_mips_bneg_d_test:155; CHECK-NOT: and.v156; CHECK: bneg.d157 158@llvm_mips_bset_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16159@llvm_mips_bset_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16160@llvm_mips_bset_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16161 162define void @llvm_mips_bset_b_test() nounwind {163entry:164 %0 = load <16 x i8>, ptr @llvm_mips_bset_b_ARG1165 %1 = load <16 x i8>, ptr @llvm_mips_bset_b_ARG2166 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)167 store <16 x i8> %2, ptr @llvm_mips_bset_b_RES168 ret void169}170 171declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind172 173; CHECK-LABEL: llvm_mips_bset_b_test:174; CHECK-NOT: andi.b175; CHECK: bset.b176 177@llvm_mips_bset_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16178@llvm_mips_bset_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16179@llvm_mips_bset_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16180 181define void @llvm_mips_bset_h_test() nounwind {182entry:183 %0 = load <8 x i16>, ptr @llvm_mips_bset_h_ARG1184 %1 = load <8 x i16>, ptr @llvm_mips_bset_h_ARG2185 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)186 store <8 x i16> %2, ptr @llvm_mips_bset_h_RES187 ret void188}189 190declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind191 192; CHECK-LABEL: llvm_mips_bset_h_test:193; CHECK-NOT: and.v194; CHECK: bset.h195 196@llvm_mips_bset_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16197@llvm_mips_bset_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16198@llvm_mips_bset_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16199 200define void @llvm_mips_bset_w_test() nounwind {201entry:202 %0 = load <4 x i32>, ptr @llvm_mips_bset_w_ARG1203 %1 = load <4 x i32>, ptr @llvm_mips_bset_w_ARG2204 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)205 store <4 x i32> %2, ptr @llvm_mips_bset_w_RES206 ret void207}208 209declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind210 211; CHECK-LABEL: llvm_mips_bset_w_test:212; CHECK-NOT: and.v213; CHECK: bset.w214 215@llvm_mips_bset_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16216@llvm_mips_bset_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16217@llvm_mips_bset_d_RES = global <2 x i64> <i64 0, i64 0>, align 16218 219define void @llvm_mips_bset_d_test() nounwind {220entry:221 %0 = load <2 x i64>, ptr @llvm_mips_bset_d_ARG1222 %1 = load <2 x i64>, ptr @llvm_mips_bset_d_ARG2223 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)224 store <2 x i64> %2, ptr @llvm_mips_bset_d_RES225 ret void226}227 228declare <2 x i64> @llvm.mips.bset.d(<2 x i64>, <2 x i64>) nounwind229 230; CHECK-LABEL: llvm_mips_bset_d_test:231; CHECK-NOT: and.v232; CHECK: bset.d233 234@llvm_mips_sll_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16235@llvm_mips_sll_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16236@llvm_mips_sll_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16237 238define void @llvm_mips_sll_b_test() nounwind {239entry:240 %0 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG1241 %1 = load <16 x i8>, ptr @llvm_mips_sll_b_ARG2242 %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1)243 store <16 x i8> %2, ptr @llvm_mips_sll_b_RES244 ret void245}246 247declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind248 249; CHECK-LABEL: llvm_mips_sll_b_test:250; CHECK-NOT: andi.b251; CHECK: sll.b252 253@llvm_mips_sll_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16254@llvm_mips_sll_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16255@llvm_mips_sll_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16256 257define void @llvm_mips_sll_h_test() nounwind {258entry:259 %0 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG1260 %1 = load <8 x i16>, ptr @llvm_mips_sll_h_ARG2261 %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1)262 store <8 x i16> %2, ptr @llvm_mips_sll_h_RES263 ret void264}265 266declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind267 268; CHECK-LABEL: llvm_mips_sll_h_test:269; CHECK-NOT: and.v270; CHECK: sll.h271 272@llvm_mips_sll_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16273@llvm_mips_sll_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16274@llvm_mips_sll_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16275 276define void @llvm_mips_sll_w_test() nounwind {277entry:278 %0 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG1279 %1 = load <4 x i32>, ptr @llvm_mips_sll_w_ARG2280 %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1)281 store <4 x i32> %2, ptr @llvm_mips_sll_w_RES282 ret void283}284 285declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind286 287; CHECK-LABEL: llvm_mips_sll_w_test:288; CHECK-NOT: and.v289; CHECK: sll.w290 291@llvm_mips_sll_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16292@llvm_mips_sll_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16293@llvm_mips_sll_d_RES = global <2 x i64> <i64 0, i64 0>, align 16294 295define void @llvm_mips_sll_d_test() nounwind {296entry:297 %0 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG1298 %1 = load <2 x i64>, ptr @llvm_mips_sll_d_ARG2299 %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1)300 store <2 x i64> %2, ptr @llvm_mips_sll_d_RES301 ret void302}303 304declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind305 306; CHECK-LABEL: llvm_mips_sll_d_test:307; CHECK-NOT: and.v308; CHECK: sll.d309 310@llvm_mips_sra_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16311@llvm_mips_sra_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16312@llvm_mips_sra_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16313 314define void @llvm_mips_sra_b_test() nounwind {315entry:316 %0 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG1317 %1 = load <16 x i8>, ptr @llvm_mips_sra_b_ARG2318 %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1)319 store <16 x i8> %2, ptr @llvm_mips_sra_b_RES320 ret void321}322 323declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind324 325; CHECK-LABEL: llvm_mips_sra_b_test:326; CHECK-NOT: andi.b327; CHECK: sra.b328 329@llvm_mips_sra_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16330@llvm_mips_sra_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16331@llvm_mips_sra_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16332 333define void @llvm_mips_sra_h_test() nounwind {334entry:335 %0 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG1336 %1 = load <8 x i16>, ptr @llvm_mips_sra_h_ARG2337 %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1)338 store <8 x i16> %2, ptr @llvm_mips_sra_h_RES339 ret void340}341 342declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind343 344; CHECK-LABEL: llvm_mips_sra_h_test:345; CHECK-NOT: and.v346; CHECK: sra.h347 348@llvm_mips_sra_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16349@llvm_mips_sra_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16350@llvm_mips_sra_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16351 352define void @llvm_mips_sra_w_test() nounwind {353entry:354 %0 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG1355 %1 = load <4 x i32>, ptr @llvm_mips_sra_w_ARG2356 %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1)357 store <4 x i32> %2, ptr @llvm_mips_sra_w_RES358 ret void359}360 361declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind362 363; CHECK-LABEL: llvm_mips_sra_w_test:364; CHECK-NOT: and.v365; CHECK: sra.w366 367@llvm_mips_sra_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16368@llvm_mips_sra_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16369@llvm_mips_sra_d_RES = global <2 x i64> <i64 0, i64 0>, align 16370 371define void @llvm_mips_sra_d_test() nounwind {372entry:373 %0 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG1374 %1 = load <2 x i64>, ptr @llvm_mips_sra_d_ARG2375 %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1)376 store <2 x i64> %2, ptr @llvm_mips_sra_d_RES377 ret void378}379 380declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind381 382; CHECK-LABEL: llvm_mips_sra_d_test:383; CHECK-NOT: and.v384; CHECK: sra.d385 386@llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16387@llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16388@llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16389 390define void @llvm_mips_srl_b_test() nounwind {391entry:392 %0 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG1393 %1 = load <16 x i8>, ptr @llvm_mips_srl_b_ARG2394 %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1)395 store <16 x i8> %2, ptr @llvm_mips_srl_b_RES396 ret void397}398 399declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind400 401; CHECK-LABEL: llvm_mips_srl_b_test:402; CHECK-NOT: andi.b403; CHECK: srl.b404 405@llvm_mips_srl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16406@llvm_mips_srl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16407@llvm_mips_srl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16408 409define void @llvm_mips_srl_h_test() nounwind {410entry:411 %0 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG1412 %1 = load <8 x i16>, ptr @llvm_mips_srl_h_ARG2413 %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1)414 store <8 x i16> %2, ptr @llvm_mips_srl_h_RES415 ret void416}417 418declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind419 420; CHECK-LABEL: llvm_mips_srl_h_test:421; CHECK-NOT: and.v422; CHECK: srl.h423 424@llvm_mips_srl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16425@llvm_mips_srl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16426@llvm_mips_srl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16427 428define void @llvm_mips_srl_w_test() nounwind {429entry:430 %0 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG1431 %1 = load <4 x i32>, ptr @llvm_mips_srl_w_ARG2432 %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1)433 store <4 x i32> %2, ptr @llvm_mips_srl_w_RES434 ret void435}436 437declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind438 439; CHECK-LABEL: llvm_mips_srl_w_test:440; CHECK-NOT: and.v441; CHECK: srl.w442 443@llvm_mips_srl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16444@llvm_mips_srl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16445@llvm_mips_srl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16446 447define void @llvm_mips_srl_d_test() nounwind {448entry:449 %0 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG1450 %1 = load <2 x i64>, ptr @llvm_mips_srl_d_ARG2451 %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1)452 store <2 x i64> %2, ptr @llvm_mips_srl_d_RES453 ret void454}455 456declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind457 458; CHECK-LABEL: llvm_mips_srl_d_test:459; CHECK-NOT: and.v460; CHECK: srl.d461