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1; Test the MSA intrinsics that are encoded with the VEC instruction format.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \4; RUN: | FileCheck -check-prefix=ANYENDIAN %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \6; RUN: | FileCheck -check-prefix=ANYENDIAN %s7 8@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 169@llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 1610@llvm_mips_and_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1611 12define void @llvm_mips_and_v_b_test() nounwind {13entry:14 %0 = load <16 x i8>, ptr @llvm_mips_and_v_b_ARG115 %1 = load <16 x i8>, ptr @llvm_mips_and_v_b_ARG216 %2 = bitcast <16 x i8> %0 to <16 x i8>17 %3 = bitcast <16 x i8> %1 to <16 x i8>18 %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)19 %5 = bitcast <16 x i8> %4 to <16 x i8>20 store <16 x i8> %5, ptr @llvm_mips_and_v_b_RES21 ret void22}23 24; ANYENDIAN: llvm_mips_and_v_b_test:25; ANYENDIAN: ld.b26; ANYENDIAN: ld.b27; ANYENDIAN: and.v28; ANYENDIAN: st.b29; ANYENDIAN: .size llvm_mips_and_v_b_test30;31@llvm_mips_and_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1632@llvm_mips_and_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 1633@llvm_mips_and_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1634 35define void @llvm_mips_and_v_h_test() nounwind {36entry:37 %0 = load <8 x i16>, ptr @llvm_mips_and_v_h_ARG138 %1 = load <8 x i16>, ptr @llvm_mips_and_v_h_ARG239 %2 = bitcast <8 x i16> %0 to <16 x i8>40 %3 = bitcast <8 x i16> %1 to <16 x i8>41 %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)42 %5 = bitcast <16 x i8> %4 to <8 x i16>43 store <8 x i16> %5, ptr @llvm_mips_and_v_h_RES44 ret void45}46 47; ANYENDIAN: llvm_mips_and_v_h_test:48; ANYENDIAN: ld.b49; ANYENDIAN: ld.b50; ANYENDIAN: and.v51; ANYENDIAN: st.b52; ANYENDIAN: .size llvm_mips_and_v_h_test53;54@llvm_mips_and_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1655@llvm_mips_and_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 1656@llvm_mips_and_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1657 58define void @llvm_mips_and_v_w_test() nounwind {59entry:60 %0 = load <4 x i32>, ptr @llvm_mips_and_v_w_ARG161 %1 = load <4 x i32>, ptr @llvm_mips_and_v_w_ARG262 %2 = bitcast <4 x i32> %0 to <16 x i8>63 %3 = bitcast <4 x i32> %1 to <16 x i8>64 %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)65 %5 = bitcast <16 x i8> %4 to <4 x i32>66 store <4 x i32> %5, ptr @llvm_mips_and_v_w_RES67 ret void68}69 70; ANYENDIAN: llvm_mips_and_v_w_test:71; ANYENDIAN: ld.b72; ANYENDIAN: ld.b73; ANYENDIAN: and.v74; ANYENDIAN: st.b75; ANYENDIAN: .size llvm_mips_and_v_w_test76;77@llvm_mips_and_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1678@llvm_mips_and_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 1679@llvm_mips_and_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 1680 81define void @llvm_mips_and_v_d_test() nounwind {82entry:83 %0 = load <2 x i64>, ptr @llvm_mips_and_v_d_ARG184 %1 = load <2 x i64>, ptr @llvm_mips_and_v_d_ARG285 %2 = bitcast <2 x i64> %0 to <16 x i8>86 %3 = bitcast <2 x i64> %1 to <16 x i8>87 %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)88 %5 = bitcast <16 x i8> %4 to <2 x i64>89 store <2 x i64> %5, ptr @llvm_mips_and_v_d_RES90 ret void91}92 93; ANYENDIAN: llvm_mips_and_v_d_test:94; ANYENDIAN: ld.b95; ANYENDIAN: ld.b96; ANYENDIAN: and.v97; ANYENDIAN: st.b98; ANYENDIAN: .size llvm_mips_and_v_d_test99;100define void @and_v_b_test() nounwind {101entry:102 %0 = load <16 x i8>, ptr @llvm_mips_and_v_b_ARG1103 %1 = load <16 x i8>, ptr @llvm_mips_and_v_b_ARG2104 %2 = and <16 x i8> %0, %1105 store <16 x i8> %2, ptr @llvm_mips_and_v_b_RES106 ret void107}108 109; ANYENDIAN: and_v_b_test:110; ANYENDIAN: ld.b111; ANYENDIAN: ld.b112; ANYENDIAN: and.v113; ANYENDIAN: st.b114; ANYENDIAN: .size and_v_b_test115;116define void @and_v_h_test() nounwind {117entry:118 %0 = load <8 x i16>, ptr @llvm_mips_and_v_h_ARG1119 %1 = load <8 x i16>, ptr @llvm_mips_and_v_h_ARG2120 %2 = and <8 x i16> %0, %1121 store <8 x i16> %2, ptr @llvm_mips_and_v_h_RES122 ret void123}124 125; ANYENDIAN: and_v_h_test:126; ANYENDIAN: ld.h127; ANYENDIAN: ld.h128; ANYENDIAN: and.v129; ANYENDIAN: st.h130; ANYENDIAN: .size and_v_h_test131;132 133define void @and_v_w_test() nounwind {134entry:135 %0 = load <4 x i32>, ptr @llvm_mips_and_v_w_ARG1136 %1 = load <4 x i32>, ptr @llvm_mips_and_v_w_ARG2137 %2 = and <4 x i32> %0, %1138 store <4 x i32> %2, ptr @llvm_mips_and_v_w_RES139 ret void140}141 142; ANYENDIAN: and_v_w_test:143; ANYENDIAN: ld.w144; ANYENDIAN: ld.w145; ANYENDIAN: and.v146; ANYENDIAN: st.w147; ANYENDIAN: .size and_v_w_test148;149 150define void @and_v_d_test() nounwind {151entry:152 %0 = load <2 x i64>, ptr @llvm_mips_and_v_d_ARG1153 %1 = load <2 x i64>, ptr @llvm_mips_and_v_d_ARG2154 %2 = and <2 x i64> %0, %1155 store <2 x i64> %2, ptr @llvm_mips_and_v_d_RES156 ret void157}158 159; ANYENDIAN: and_v_d_test:160; ANYENDIAN: ld.d161; ANYENDIAN: ld.d162; ANYENDIAN: and.v163; ANYENDIAN: st.d164; ANYENDIAN: .size and_v_d_test165;166@llvm_mips_bmnz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16167@llvm_mips_bmnz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16168@llvm_mips_bmnz_v_b_ARG3 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16169@llvm_mips_bmnz_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16170 171define void @llvm_mips_bmnz_v_b_test() nounwind {172entry:173 %0 = load <16 x i8>, ptr @llvm_mips_bmnz_v_b_ARG1174 %1 = load <16 x i8>, ptr @llvm_mips_bmnz_v_b_ARG2175 %2 = load <16 x i8>, ptr @llvm_mips_bmnz_v_b_ARG3176 %3 = bitcast <16 x i8> %0 to <16 x i8>177 %4 = bitcast <16 x i8> %1 to <16 x i8>178 %5 = bitcast <16 x i8> %2 to <16 x i8>179 %6 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)180 %7 = bitcast <16 x i8> %6 to <16 x i8>181 store <16 x i8> %7, ptr @llvm_mips_bmnz_v_b_RES182 ret void183}184 185; ANYENDIAN: llvm_mips_bmnz_v_b_test:186; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnz_v_b_ARG1)(187; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnz_v_b_ARG2)(188; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmnz_v_b_ARG3)(189; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])190; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])191; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])192; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]193; ANYENDIAN-DAG: st.b [[R4]], 0(194; ANYENDIAN: .size llvm_mips_bmnz_v_b_test195 196@llvm_mips_bmnz_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16197@llvm_mips_bmnz_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16198@llvm_mips_bmnz_v_h_ARG3 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16199@llvm_mips_bmnz_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16200 201define void @llvm_mips_bmnz_v_h_test() nounwind {202entry:203 %0 = load <8 x i16>, ptr @llvm_mips_bmnz_v_h_ARG1204 %1 = load <8 x i16>, ptr @llvm_mips_bmnz_v_h_ARG2205 %2 = load <8 x i16>, ptr @llvm_mips_bmnz_v_h_ARG3206 %3 = bitcast <8 x i16> %0 to <16 x i8>207 %4 = bitcast <8 x i16> %1 to <16 x i8>208 %5 = bitcast <8 x i16> %2 to <16 x i8>209 %6 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)210 %7 = bitcast <16 x i8> %6 to <8 x i16>211 store <8 x i16> %7, ptr @llvm_mips_bmnz_v_h_RES212 ret void213}214 215; ANYENDIAN: llvm_mips_bmnz_v_h_test:216; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnz_v_h_ARG1)(217; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnz_v_h_ARG2)(218; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmnz_v_h_ARG3)(219; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])220; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])221; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])222; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]223; ANYENDIAN-DAG: st.b [[R4]], 0(224; ANYENDIAN: .size llvm_mips_bmnz_v_h_test225 226@llvm_mips_bmnz_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16227@llvm_mips_bmnz_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16228@llvm_mips_bmnz_v_w_ARG3 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16229@llvm_mips_bmnz_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16230 231define void @llvm_mips_bmnz_v_w_test() nounwind {232entry:233 %0 = load <4 x i32>, ptr @llvm_mips_bmnz_v_w_ARG1234 %1 = load <4 x i32>, ptr @llvm_mips_bmnz_v_w_ARG2235 %2 = load <4 x i32>, ptr @llvm_mips_bmnz_v_w_ARG3236 %3 = bitcast <4 x i32> %0 to <16 x i8>237 %4 = bitcast <4 x i32> %1 to <16 x i8>238 %5 = bitcast <4 x i32> %2 to <16 x i8>239 %6 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)240 %7 = bitcast <16 x i8> %6 to <4 x i32>241 store <4 x i32> %7, ptr @llvm_mips_bmnz_v_w_RES242 ret void243}244 245; ANYENDIAN: llvm_mips_bmnz_v_w_test:246; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnz_v_w_ARG1)(247; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnz_v_w_ARG2)(248; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmnz_v_w_ARG3)(249; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])250; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])251; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])252; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]253; ANYENDIAN-DAG: st.b [[R4]], 0(254; ANYENDIAN: .size llvm_mips_bmnz_v_w_test255 256@llvm_mips_bmnz_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16257@llvm_mips_bmnz_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16258@llvm_mips_bmnz_v_d_ARG3 = global <2 x i64> <i64 0, i64 1>, align 16259@llvm_mips_bmnz_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16260 261define void @llvm_mips_bmnz_v_d_test() nounwind {262entry:263 %0 = load <2 x i64>, ptr @llvm_mips_bmnz_v_d_ARG1264 %1 = load <2 x i64>, ptr @llvm_mips_bmnz_v_d_ARG2265 %2 = load <2 x i64>, ptr @llvm_mips_bmnz_v_d_ARG3266 %3 = bitcast <2 x i64> %0 to <16 x i8>267 %4 = bitcast <2 x i64> %1 to <16 x i8>268 %5 = bitcast <2 x i64> %2 to <16 x i8>269 %6 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)270 %7 = bitcast <16 x i8> %6 to <2 x i64>271 store <2 x i64> %7, ptr @llvm_mips_bmnz_v_d_RES272 ret void273}274 275; ANYENDIAN: llvm_mips_bmnz_v_d_test:276; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnz_v_d_ARG1)(277; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnz_v_d_ARG2)(278; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmnz_v_d_ARG3)(279; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])280; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])281; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])282; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]283; ANYENDIAN-DAG: st.b [[R4]], 0(284; ANYENDIAN: .size llvm_mips_bmnz_v_d_test285 286@llvm_mips_bmz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16287@llvm_mips_bmz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16288@llvm_mips_bmz_v_b_ARG3 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16289@llvm_mips_bmz_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16290 291define void @llvm_mips_bmz_v_b_test() nounwind {292entry:293 %0 = load <16 x i8>, ptr @llvm_mips_bmz_v_b_ARG1294 %1 = load <16 x i8>, ptr @llvm_mips_bmz_v_b_ARG2295 %2 = load <16 x i8>, ptr @llvm_mips_bmz_v_b_ARG3296 %3 = bitcast <16 x i8> %0 to <16 x i8>297 %4 = bitcast <16 x i8> %1 to <16 x i8>298 %5 = bitcast <16 x i8> %2 to <16 x i8>299 %6 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)300 %7 = bitcast <16 x i8> %6 to <16 x i8>301 store <16 x i8> %7, ptr @llvm_mips_bmz_v_b_RES302 ret void303}304 305; ANYENDIAN: llvm_mips_bmz_v_b_test:306; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmz_v_b_ARG1)(307; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmz_v_b_ARG2)(308; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmz_v_b_ARG3)(309; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])310; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])311; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])312; bmnz.v is the same as bmz.v with ws and wd_in swapped313; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]314; ANYENDIAN-DAG: st.b [[R5]], 0(315; ANYENDIAN: .size llvm_mips_bmz_v_b_test316 317@llvm_mips_bmz_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16318@llvm_mips_bmz_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16319@llvm_mips_bmz_v_h_ARG3 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16320@llvm_mips_bmz_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16321 322define void @llvm_mips_bmz_v_h_test() nounwind {323entry:324 %0 = load <8 x i16>, ptr @llvm_mips_bmz_v_h_ARG1325 %1 = load <8 x i16>, ptr @llvm_mips_bmz_v_h_ARG2326 %2 = load <8 x i16>, ptr @llvm_mips_bmz_v_h_ARG3327 %3 = bitcast <8 x i16> %0 to <16 x i8>328 %4 = bitcast <8 x i16> %1 to <16 x i8>329 %5 = bitcast <8 x i16> %2 to <16 x i8>330 %6 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)331 %7 = bitcast <16 x i8> %6 to <8 x i16>332 store <8 x i16> %7, ptr @llvm_mips_bmz_v_h_RES333 ret void334}335 336; ANYENDIAN: llvm_mips_bmz_v_h_test:337; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmz_v_h_ARG1)(338; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmz_v_h_ARG2)(339; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmz_v_h_ARG3)(340; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])341; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])342; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])343; bmnz.v is the same as bmz.v with ws and wd_in swapped344; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]345; ANYENDIAN-DAG: st.b [[R5]], 0(346; ANYENDIAN: .size llvm_mips_bmz_v_h_test347 348@llvm_mips_bmz_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16349@llvm_mips_bmz_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16350@llvm_mips_bmz_v_w_ARG3 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16351@llvm_mips_bmz_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16352 353define void @llvm_mips_bmz_v_w_test() nounwind {354entry:355 %0 = load <4 x i32>, ptr @llvm_mips_bmz_v_w_ARG1356 %1 = load <4 x i32>, ptr @llvm_mips_bmz_v_w_ARG2357 %2 = load <4 x i32>, ptr @llvm_mips_bmz_v_w_ARG3358 %3 = bitcast <4 x i32> %0 to <16 x i8>359 %4 = bitcast <4 x i32> %1 to <16 x i8>360 %5 = bitcast <4 x i32> %2 to <16 x i8>361 %6 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)362 %7 = bitcast <16 x i8> %6 to <4 x i32>363 store <4 x i32> %7, ptr @llvm_mips_bmz_v_w_RES364 ret void365}366 367; ANYENDIAN: llvm_mips_bmz_v_w_test:368; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmz_v_w_ARG1)(369; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmz_v_w_ARG2)(370; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmz_v_w_ARG3)(371; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])372; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])373; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])374; bmnz.v is the same as bmz.v with ws and wd_in swapped375; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]376; ANYENDIAN-DAG: st.b [[R5]], 0(377; ANYENDIAN: .size llvm_mips_bmz_v_w_test378 379@llvm_mips_bmz_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16380@llvm_mips_bmz_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16381@llvm_mips_bmz_v_d_ARG3 = global <2 x i64> <i64 0, i64 1>, align 16382@llvm_mips_bmz_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16383 384define void @llvm_mips_bmz_v_d_test() nounwind {385entry:386 %0 = load <2 x i64>, ptr @llvm_mips_bmz_v_d_ARG1387 %1 = load <2 x i64>, ptr @llvm_mips_bmz_v_d_ARG2388 %2 = load <2 x i64>, ptr @llvm_mips_bmz_v_d_ARG3389 %3 = bitcast <2 x i64> %0 to <16 x i8>390 %4 = bitcast <2 x i64> %1 to <16 x i8>391 %5 = bitcast <2 x i64> %2 to <16 x i8>392 %6 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)393 %7 = bitcast <16 x i8> %6 to <2 x i64>394 store <2 x i64> %7, ptr @llvm_mips_bmz_v_d_RES395 ret void396}397 398; ANYENDIAN: llvm_mips_bmz_v_d_test:399; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmz_v_d_ARG1)(400; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmz_v_d_ARG2)(401; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bmz_v_d_ARG3)(402; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])403; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])404; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])405; bmnz.v is the same as bmz.v with ws and wd_in swapped406; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]407; ANYENDIAN-DAG: st.b [[R5]], 0(408; ANYENDIAN: .size llvm_mips_bmz_v_d_test409 410@llvm_mips_bsel_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16411@llvm_mips_bsel_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16412@llvm_mips_bsel_v_b_ARG3 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16413@llvm_mips_bsel_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16414 415define void @llvm_mips_bsel_v_b_test() nounwind {416entry:417 %0 = load <16 x i8>, ptr @llvm_mips_bsel_v_b_ARG1418 %1 = load <16 x i8>, ptr @llvm_mips_bsel_v_b_ARG2419 %2 = load <16 x i8>, ptr @llvm_mips_bsel_v_b_ARG3420 %3 = bitcast <16 x i8> %0 to <16 x i8>421 %4 = bitcast <16 x i8> %1 to <16 x i8>422 %5 = bitcast <16 x i8> %2 to <16 x i8>423 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)424 %7 = bitcast <16 x i8> %6 to <16 x i8>425 store <16 x i8> %7, ptr @llvm_mips_bsel_v_b_RES426 ret void427}428 429; ANYENDIAN: llvm_mips_bsel_v_b_test:430; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bsel_v_b_ARG1)(431; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bsel_v_b_ARG2)(432; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bsel_v_b_ARG3)(433; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])434; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])435; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])436; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)437; ANYENDIAN-DAG: bmnz.v [[R5]], [[R6]], [[R4]]438; ANYENDIAN-DAG: st.b [[R5]], 0(439; ANYENDIAN: .size llvm_mips_bsel_v_b_test440 441@llvm_mips_bsel_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16442@llvm_mips_bsel_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16443@llvm_mips_bsel_v_h_ARG3 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16444@llvm_mips_bsel_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16445 446define void @llvm_mips_bsel_v_h_test() nounwind {447entry:448 %0 = load <8 x i16>, ptr @llvm_mips_bsel_v_h_ARG1449 %1 = load <8 x i16>, ptr @llvm_mips_bsel_v_h_ARG2450 %2 = load <8 x i16>, ptr @llvm_mips_bsel_v_h_ARG3451 %3 = bitcast <8 x i16> %0 to <16 x i8>452 %4 = bitcast <8 x i16> %1 to <16 x i8>453 %5 = bitcast <8 x i16> %2 to <16 x i8>454 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)455 %7 = bitcast <16 x i8> %6 to <8 x i16>456 store <8 x i16> %7, ptr @llvm_mips_bsel_v_h_RES457 ret void458}459 460; ANYENDIAN: llvm_mips_bsel_v_h_test:461; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bsel_v_h_ARG1)(462; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bsel_v_h_ARG2)(463; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bsel_v_h_ARG3)(464; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])465; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])466; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])467; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)468; ANYENDIAN-DAG: bmnz.v [[R5]], [[R6]], [[R4]]469; ANYENDIAN-DAG: st.b [[R5]], 0(470; ANYENDIAN: .size llvm_mips_bsel_v_h_test471 472@llvm_mips_bsel_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16473@llvm_mips_bsel_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16474@llvm_mips_bsel_v_w_ARG3 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16475@llvm_mips_bsel_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16476 477define void @llvm_mips_bsel_v_w_test() nounwind {478entry:479 %0 = load <4 x i32>, ptr @llvm_mips_bsel_v_w_ARG1480 %1 = load <4 x i32>, ptr @llvm_mips_bsel_v_w_ARG2481 %2 = load <4 x i32>, ptr @llvm_mips_bsel_v_w_ARG3482 %3 = bitcast <4 x i32> %0 to <16 x i8>483 %4 = bitcast <4 x i32> %1 to <16 x i8>484 %5 = bitcast <4 x i32> %2 to <16 x i8>485 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)486 %7 = bitcast <16 x i8> %6 to <4 x i32>487 store <4 x i32> %7, ptr @llvm_mips_bsel_v_w_RES488 ret void489}490 491; ANYENDIAN: llvm_mips_bsel_v_w_test:492; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bsel_v_w_ARG1)(493; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bsel_v_w_ARG2)(494; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bsel_v_w_ARG3)(495; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])496; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])497; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])498; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)499; ANYENDIAN-DAG: bmnz.v [[R5]], [[R6]], [[R4]]500; ANYENDIAN-DAG: st.b [[R5]], 0(501; ANYENDIAN: .size llvm_mips_bsel_v_w_test502 503@llvm_mips_bsel_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16504@llvm_mips_bsel_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16505@llvm_mips_bsel_v_d_ARG3 = global <2 x i64> <i64 0, i64 1>, align 16506@llvm_mips_bsel_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16507 508define void @llvm_mips_bsel_v_d_test() nounwind {509entry:510 %0 = load <2 x i64>, ptr @llvm_mips_bsel_v_d_ARG1511 %1 = load <2 x i64>, ptr @llvm_mips_bsel_v_d_ARG2512 %2 = load <2 x i64>, ptr @llvm_mips_bsel_v_d_ARG3513 %3 = bitcast <2 x i64> %0 to <16 x i8>514 %4 = bitcast <2 x i64> %1 to <16 x i8>515 %5 = bitcast <2 x i64> %2 to <16 x i8>516 %6 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %3, <16 x i8> %4, <16 x i8> %5)517 %7 = bitcast <16 x i8> %6 to <2 x i64>518 store <2 x i64> %7, ptr @llvm_mips_bsel_v_d_RES519 ret void520}521 522; ANYENDIAN: llvm_mips_bsel_v_d_test:523; ANYENDIAN-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bsel_v_d_ARG1)(524; ANYENDIAN-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bsel_v_d_ARG2)(525; ANYENDIAN-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_bsel_v_d_ARG3)(526; ANYENDIAN-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])527; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])528; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])529; bmnz.v is the same as bsel.v with (wd_in, wt, ws) -> (wt, ws, wd_in)530; ANYENDIAN-DAG: bmnz.v [[R5]], [[R6]], [[R4]]531; ANYENDIAN-DAG: st.b [[R5]], 0(532; ANYENDIAN: .size llvm_mips_bsel_v_d_test533 534@llvm_mips_nor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16535@llvm_mips_nor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16536@llvm_mips_nor_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16537 538define void @llvm_mips_nor_v_b_test() nounwind {539entry:540 %0 = load <16 x i8>, ptr @llvm_mips_nor_v_b_ARG1541 %1 = load <16 x i8>, ptr @llvm_mips_nor_v_b_ARG2542 %2 = bitcast <16 x i8> %0 to <16 x i8>543 %3 = bitcast <16 x i8> %1 to <16 x i8>544 %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)545 %5 = bitcast <16 x i8> %4 to <16 x i8>546 store <16 x i8> %5, ptr @llvm_mips_nor_v_b_RES547 ret void548}549 550; ANYENDIAN: llvm_mips_nor_v_b_test:551; ANYENDIAN: ld.b552; ANYENDIAN: ld.b553; ANYENDIAN: nor.v554; ANYENDIAN: st.b555; ANYENDIAN: .size llvm_mips_nor_v_b_test556;557@llvm_mips_nor_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16558@llvm_mips_nor_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16559@llvm_mips_nor_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16560 561define void @llvm_mips_nor_v_h_test() nounwind {562entry:563 %0 = load <8 x i16>, ptr @llvm_mips_nor_v_h_ARG1564 %1 = load <8 x i16>, ptr @llvm_mips_nor_v_h_ARG2565 %2 = bitcast <8 x i16> %0 to <16 x i8>566 %3 = bitcast <8 x i16> %1 to <16 x i8>567 %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)568 %5 = bitcast <16 x i8> %4 to <8 x i16>569 store <8 x i16> %5, ptr @llvm_mips_nor_v_h_RES570 ret void571}572 573; ANYENDIAN: llvm_mips_nor_v_h_test:574; ANYENDIAN: ld.b575; ANYENDIAN: ld.b576; ANYENDIAN: nor.v577; ANYENDIAN: st.b578; ANYENDIAN: .size llvm_mips_nor_v_h_test579;580@llvm_mips_nor_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16581@llvm_mips_nor_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16582@llvm_mips_nor_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16583 584define void @llvm_mips_nor_v_w_test() nounwind {585entry:586 %0 = load <4 x i32>, ptr @llvm_mips_nor_v_w_ARG1587 %1 = load <4 x i32>, ptr @llvm_mips_nor_v_w_ARG2588 %2 = bitcast <4 x i32> %0 to <16 x i8>589 %3 = bitcast <4 x i32> %1 to <16 x i8>590 %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)591 %5 = bitcast <16 x i8> %4 to <4 x i32>592 store <4 x i32> %5, ptr @llvm_mips_nor_v_w_RES593 ret void594}595 596; ANYENDIAN: llvm_mips_nor_v_w_test:597; ANYENDIAN: ld.b598; ANYENDIAN: ld.b599; ANYENDIAN: nor.v600; ANYENDIAN: st.b601; ANYENDIAN: .size llvm_mips_nor_v_w_test602;603@llvm_mips_nor_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16604@llvm_mips_nor_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16605@llvm_mips_nor_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16606 607define void @llvm_mips_nor_v_d_test() nounwind {608entry:609 %0 = load <2 x i64>, ptr @llvm_mips_nor_v_d_ARG1610 %1 = load <2 x i64>, ptr @llvm_mips_nor_v_d_ARG2611 %2 = bitcast <2 x i64> %0 to <16 x i8>612 %3 = bitcast <2 x i64> %1 to <16 x i8>613 %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)614 %5 = bitcast <16 x i8> %4 to <2 x i64>615 store <2 x i64> %5, ptr @llvm_mips_nor_v_d_RES616 ret void617}618 619; ANYENDIAN: llvm_mips_nor_v_d_test:620; ANYENDIAN: ld.b621; ANYENDIAN: ld.b622; ANYENDIAN: nor.v623; ANYENDIAN: st.b624; ANYENDIAN: .size llvm_mips_nor_v_d_test625;626@llvm_mips_or_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16627@llvm_mips_or_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16628@llvm_mips_or_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16629 630define void @llvm_mips_or_v_b_test() nounwind {631entry:632 %0 = load <16 x i8>, ptr @llvm_mips_or_v_b_ARG1633 %1 = load <16 x i8>, ptr @llvm_mips_or_v_b_ARG2634 %2 = bitcast <16 x i8> %0 to <16 x i8>635 %3 = bitcast <16 x i8> %1 to <16 x i8>636 %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)637 %5 = bitcast <16 x i8> %4 to <16 x i8>638 store <16 x i8> %5, ptr @llvm_mips_or_v_b_RES639 ret void640}641 642; ANYENDIAN: llvm_mips_or_v_b_test:643; ANYENDIAN: ld.b644; ANYENDIAN: ld.b645; ANYENDIAN: or.v646; ANYENDIAN: st.b647; ANYENDIAN: .size llvm_mips_or_v_b_test648;649@llvm_mips_or_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16650@llvm_mips_or_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16651@llvm_mips_or_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16652 653define void @llvm_mips_or_v_h_test() nounwind {654entry:655 %0 = load <8 x i16>, ptr @llvm_mips_or_v_h_ARG1656 %1 = load <8 x i16>, ptr @llvm_mips_or_v_h_ARG2657 %2 = bitcast <8 x i16> %0 to <16 x i8>658 %3 = bitcast <8 x i16> %1 to <16 x i8>659 %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)660 %5 = bitcast <16 x i8> %4 to <8 x i16>661 store <8 x i16> %5, ptr @llvm_mips_or_v_h_RES662 ret void663}664 665; ANYENDIAN: llvm_mips_or_v_h_test:666; ANYENDIAN: ld.b667; ANYENDIAN: ld.b668; ANYENDIAN: or.v669; ANYENDIAN: st.b670; ANYENDIAN: .size llvm_mips_or_v_h_test671;672@llvm_mips_or_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16673@llvm_mips_or_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16674@llvm_mips_or_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16675 676define void @llvm_mips_or_v_w_test() nounwind {677entry:678 %0 = load <4 x i32>, ptr @llvm_mips_or_v_w_ARG1679 %1 = load <4 x i32>, ptr @llvm_mips_or_v_w_ARG2680 %2 = bitcast <4 x i32> %0 to <16 x i8>681 %3 = bitcast <4 x i32> %1 to <16 x i8>682 %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)683 %5 = bitcast <16 x i8> %4 to <4 x i32>684 store <4 x i32> %5, ptr @llvm_mips_or_v_w_RES685 ret void686}687 688; ANYENDIAN: llvm_mips_or_v_w_test:689; ANYENDIAN: ld.b690; ANYENDIAN: ld.b691; ANYENDIAN: or.v692; ANYENDIAN: st.b693; ANYENDIAN: .size llvm_mips_or_v_w_test694;695@llvm_mips_or_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16696@llvm_mips_or_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16697@llvm_mips_or_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16698 699define void @llvm_mips_or_v_d_test() nounwind {700entry:701 %0 = load <2 x i64>, ptr @llvm_mips_or_v_d_ARG1702 %1 = load <2 x i64>, ptr @llvm_mips_or_v_d_ARG2703 %2 = bitcast <2 x i64> %0 to <16 x i8>704 %3 = bitcast <2 x i64> %1 to <16 x i8>705 %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)706 %5 = bitcast <16 x i8> %4 to <2 x i64>707 store <2 x i64> %5, ptr @llvm_mips_or_v_d_RES708 ret void709}710 711; ANYENDIAN: llvm_mips_or_v_d_test:712; ANYENDIAN: ld.b713; ANYENDIAN: ld.b714; ANYENDIAN: or.v715; ANYENDIAN: st.b716; ANYENDIAN: .size llvm_mips_or_v_d_test717;718define void @or_v_b_test() nounwind {719entry:720 %0 = load <16 x i8>, ptr @llvm_mips_or_v_b_ARG1721 %1 = load <16 x i8>, ptr @llvm_mips_or_v_b_ARG2722 %2 = or <16 x i8> %0, %1723 store <16 x i8> %2, ptr @llvm_mips_or_v_b_RES724 ret void725}726 727; ANYENDIAN: or_v_b_test:728; ANYENDIAN: ld.b729; ANYENDIAN: ld.b730; ANYENDIAN: or.v731; ANYENDIAN: st.b732; ANYENDIAN: .size or_v_b_test733;734define void @or_v_h_test() nounwind {735entry:736 %0 = load <8 x i16>, ptr @llvm_mips_or_v_h_ARG1737 %1 = load <8 x i16>, ptr @llvm_mips_or_v_h_ARG2738 %2 = or <8 x i16> %0, %1739 store <8 x i16> %2, ptr @llvm_mips_or_v_h_RES740 ret void741}742 743; ANYENDIAN: or_v_h_test:744; ANYENDIAN: ld.h745; ANYENDIAN: ld.h746; ANYENDIAN: or.v747; ANYENDIAN: st.h748; ANYENDIAN: .size or_v_h_test749;750 751define void @or_v_w_test() nounwind {752entry:753 %0 = load <4 x i32>, ptr @llvm_mips_or_v_w_ARG1754 %1 = load <4 x i32>, ptr @llvm_mips_or_v_w_ARG2755 %2 = or <4 x i32> %0, %1756 store <4 x i32> %2, ptr @llvm_mips_or_v_w_RES757 ret void758}759 760; ANYENDIAN: or_v_w_test:761; ANYENDIAN: ld.w762; ANYENDIAN: ld.w763; ANYENDIAN: or.v764; ANYENDIAN: st.w765; ANYENDIAN: .size or_v_w_test766;767 768define void @or_v_d_test() nounwind {769entry:770 %0 = load <2 x i64>, ptr @llvm_mips_or_v_d_ARG1771 %1 = load <2 x i64>, ptr @llvm_mips_or_v_d_ARG2772 %2 = or <2 x i64> %0, %1773 store <2 x i64> %2, ptr @llvm_mips_or_v_d_RES774 ret void775}776 777; ANYENDIAN: or_v_d_test:778; ANYENDIAN: ld.d779; ANYENDIAN: ld.d780; ANYENDIAN: or.v781; ANYENDIAN: st.d782; ANYENDIAN: .size or_v_d_test783;784@llvm_mips_xor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16785@llvm_mips_xor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16786@llvm_mips_xor_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16787 788define void @llvm_mips_xor_v_b_test() nounwind {789entry:790 %0 = load <16 x i8>, ptr @llvm_mips_xor_v_b_ARG1791 %1 = load <16 x i8>, ptr @llvm_mips_xor_v_b_ARG2792 %2 = bitcast <16 x i8> %0 to <16 x i8>793 %3 = bitcast <16 x i8> %1 to <16 x i8>794 %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)795 %5 = bitcast <16 x i8> %4 to <16 x i8>796 store <16 x i8> %5, ptr @llvm_mips_xor_v_b_RES797 ret void798}799 800; ANYENDIAN: llvm_mips_xor_v_b_test:801; ANYENDIAN: ld.b802; ANYENDIAN: ld.b803; ANYENDIAN: xor.v804; ANYENDIAN: st.b805; ANYENDIAN: .size llvm_mips_xor_v_b_test806;807@llvm_mips_xor_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16808@llvm_mips_xor_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16809@llvm_mips_xor_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16810 811define void @llvm_mips_xor_v_h_test() nounwind {812entry:813 %0 = load <8 x i16>, ptr @llvm_mips_xor_v_h_ARG1814 %1 = load <8 x i16>, ptr @llvm_mips_xor_v_h_ARG2815 %2 = bitcast <8 x i16> %0 to <16 x i8>816 %3 = bitcast <8 x i16> %1 to <16 x i8>817 %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)818 %5 = bitcast <16 x i8> %4 to <8 x i16>819 store <8 x i16> %5, ptr @llvm_mips_xor_v_h_RES820 ret void821}822 823; ANYENDIAN: llvm_mips_xor_v_h_test:824; ANYENDIAN: ld.b825; ANYENDIAN: ld.b826; ANYENDIAN: xor.v827; ANYENDIAN: st.b828; ANYENDIAN: .size llvm_mips_xor_v_h_test829;830@llvm_mips_xor_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16831@llvm_mips_xor_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16832@llvm_mips_xor_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16833 834define void @llvm_mips_xor_v_w_test() nounwind {835entry:836 %0 = load <4 x i32>, ptr @llvm_mips_xor_v_w_ARG1837 %1 = load <4 x i32>, ptr @llvm_mips_xor_v_w_ARG2838 %2 = bitcast <4 x i32> %0 to <16 x i8>839 %3 = bitcast <4 x i32> %1 to <16 x i8>840 %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)841 %5 = bitcast <16 x i8> %4 to <4 x i32>842 store <4 x i32> %5, ptr @llvm_mips_xor_v_w_RES843 ret void844}845 846; ANYENDIAN: llvm_mips_xor_v_w_test:847; ANYENDIAN: ld.b848; ANYENDIAN: ld.b849; ANYENDIAN: xor.v850; ANYENDIAN: st.b851; ANYENDIAN: .size llvm_mips_xor_v_w_test852;853@llvm_mips_xor_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16854@llvm_mips_xor_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16855@llvm_mips_xor_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16856 857define void @llvm_mips_xor_v_d_test() nounwind {858entry:859 %0 = load <2 x i64>, ptr @llvm_mips_xor_v_d_ARG1860 %1 = load <2 x i64>, ptr @llvm_mips_xor_v_d_ARG2861 %2 = bitcast <2 x i64> %0 to <16 x i8>862 %3 = bitcast <2 x i64> %1 to <16 x i8>863 %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)864 %5 = bitcast <16 x i8> %4 to <2 x i64>865 store <2 x i64> %5, ptr @llvm_mips_xor_v_d_RES866 ret void867}868 869; ANYENDIAN: llvm_mips_xor_v_d_test:870; ANYENDIAN: ld.b871; ANYENDIAN: ld.b872; ANYENDIAN: xor.v873; ANYENDIAN: st.b874; ANYENDIAN: .size llvm_mips_xor_v_d_test875;876define void @xor_v_b_test() nounwind {877entry:878 %0 = load <16 x i8>, ptr @llvm_mips_xor_v_b_ARG1879 %1 = load <16 x i8>, ptr @llvm_mips_xor_v_b_ARG2880 %2 = xor <16 x i8> %0, %1881 store <16 x i8> %2, ptr @llvm_mips_xor_v_b_RES882 ret void883}884 885; ANYENDIAN: xor_v_b_test:886; ANYENDIAN: ld.b887; ANYENDIAN: ld.b888; ANYENDIAN: xor.v889; ANYENDIAN: st.b890; ANYENDIAN: .size xor_v_b_test891;892define void @xor_v_h_test() nounwind {893entry:894 %0 = load <8 x i16>, ptr @llvm_mips_xor_v_h_ARG1895 %1 = load <8 x i16>, ptr @llvm_mips_xor_v_h_ARG2896 %2 = xor <8 x i16> %0, %1897 store <8 x i16> %2, ptr @llvm_mips_xor_v_h_RES898 ret void899}900 901; ANYENDIAN: xor_v_h_test:902; ANYENDIAN: ld.h903; ANYENDIAN: ld.h904; ANYENDIAN: xor.v905; ANYENDIAN: st.h906; ANYENDIAN: .size xor_v_h_test907;908 909define void @xor_v_w_test() nounwind {910entry:911 %0 = load <4 x i32>, ptr @llvm_mips_xor_v_w_ARG1912 %1 = load <4 x i32>, ptr @llvm_mips_xor_v_w_ARG2913 %2 = xor <4 x i32> %0, %1914 store <4 x i32> %2, ptr @llvm_mips_xor_v_w_RES915 ret void916}917 918; ANYENDIAN: xor_v_w_test:919; ANYENDIAN: ld.w920; ANYENDIAN: ld.w921; ANYENDIAN: xor.v922; ANYENDIAN: st.w923; ANYENDIAN: .size xor_v_w_test924;925 926define void @xor_v_d_test() nounwind {927entry:928 %0 = load <2 x i64>, ptr @llvm_mips_xor_v_d_ARG1929 %1 = load <2 x i64>, ptr @llvm_mips_xor_v_d_ARG2930 %2 = xor <2 x i64> %0, %1931 store <2 x i64> %2, ptr @llvm_mips_xor_v_d_RES932 ret void933}934 935; ANYENDIAN: xor_v_d_test:936; ANYENDIAN: ld.d937; ANYENDIAN: ld.d938; ANYENDIAN: xor.v939; ANYENDIAN: st.d940; ANYENDIAN: .size xor_v_d_test941;942declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind943declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind944declare <16 x i8> @llvm.mips.bmz.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind945declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>, <16 x i8>) nounwind946declare <16 x i8> @llvm.mips.nor.v(<16 x i8>, <16 x i8>) nounwind947declare <16 x i8> @llvm.mips.or.v(<16 x i8>, <16 x i8>) nounwind948declare <16 x i8> @llvm.mips.xor.v(<16 x i8>, <16 x i8>) nounwind949