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1; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \2; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \3; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG4; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \5; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \6; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG7 8@v4f32 = global <4 x float> zeroinitializer9 10define void @msa_insert_0(float %a) {11entry:12 ; Force the float into an odd-numbered register using named registers and13 ; load the vector.14 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)15 %0 = load volatile <4 x float>, ptr @v4f3216 17 ; Clobber all except $f12/$w12 and $f1318 ;19 ; The intention is that if odd single precision registers are permitted, the20 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to21 ; avoid the spill/reload.22 ;23 ; On the other hand, if odd single precision registers are not permitted, it24 ; must copy $f13 to an even-numbered register before inserting into the25 ; vector.26 call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()27 %1 = insertelement <4 x float> %0, float %b, i32 028 store <4 x float> %1, ptr @v4f3229 ret void30}31 32; ALL-LABEL: msa_insert_0:33; ALL: mov.s $f13, $f1234; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f1335; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(36; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])37; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]38; ODDSPREG: insve.w $w[[W0]][0], $w13[0]39; ALL: teqi $zero, 140; ALL-NOT: sdc141; ALL-NOT: ldc142; ALL: st.w $w[[W0]], 0($[[R0]])43 44define void @msa_insert_1(float %a) {45entry:46 ; Force the float into an odd-numbered register using named registers and47 ; load the vector.48 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)49 %0 = load volatile <4 x float>, ptr @v4f3250 51 ; Clobber all except $f12/$w12 and $f1352 ;53 ; The intention is that if odd single precision registers are permitted, the54 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to55 ; avoid the spill/reload.56 ;57 ; On the other hand, if odd single precision registers are not permitted, it58 ; must copy $f13 to an even-numbered register before inserting into the59 ; vector.60 call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()61 %1 = insertelement <4 x float> %0, float %b, i32 162 store <4 x float> %1, ptr @v4f3263 ret void64}65 66; ALL-LABEL: msa_insert_1:67; ALL: mov.s $f13, $f1268; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f1369; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(70; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])71; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]72; ODDSPREG: insve.w $w[[W0]][1], $w13[0]73; ALL: teqi $zero, 174; ALL-NOT: sdc175; ALL-NOT: ldc176; ALL: st.w $w[[W0]], 0($[[R0]])77 78define float @msa_extract_0() {79entry:80 %0 = load volatile <4 x float>, ptr @v4f3281 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)82 83 ; Clobber all except $f12, and $f1384 ;85 ; The intention is that if odd single precision registers are permitted, the86 ; allocator will choose $f13/$w13 for the vector since that saves on moves.87 ;88 ; On the other hand, if odd single precision registers are not permitted, it89 ; must move it to $f12/$w12.90 call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()91 92 %2 = extractelement <4 x float> %1, i32 093 ret float %294}95 96; ALL-LABEL: msa_extract_0:97; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(98; ALL: ld.w $w12, 0($[[R0]])99; ALL: move.v $w[[W0:13]], $w12100; ALL: teqi $zero, 1101; ALL-NOT: st.w102; ALL-NOT: ld.w103; ALL: mov.s $f0, $f[[W0]]104 105define float @msa_extract_1() {106entry:107 %0 = load volatile <4 x float>, ptr @v4f32108 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)109 110 ; Clobber all except $f13111 ;112 ; The intention is that if odd single precision registers are permitted, the113 ; allocator will choose $f13/$w13 for the vector since that saves on moves.114 ;115 ; On the other hand, if odd single precision registers are not permitted, it116 ; must be spilled.117 call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()118 119 %2 = extractelement <4 x float> %1, i32 1120 ret float %2121}122 123; ALL-LABEL: msa_extract_1:124; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(125; ALL: ld.w $w12, 0($[[R0]])126; ALL: splati.w $w[[W0:[0-9]+]], $w13[1]127; NOODDSPREG: st.w $w[[W0]], 0($sp)128; ODDSPREG-NOT: st.w129; ODDSPREG-NOT: ld.w130; ALL: teqi $zero, 1131; ODDSPREG-NOT: st.w132; ODDSPREG-NOT: ld.w133; NOODDSPREG: ld.w $w0, 0($sp)134; ODDSPREG: mov.s $f0, $f[[W0]]135