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1; RUN: llc -mtriple=mipsel -pre-RA-sched=source < %s | FileCheck %s2 3; All test functions do the same thing - they return the first variable4; argument.5 6; All CHECK's do the same thing - they check whether variable arguments from7; registers are placed on correct stack locations, and whether the first8; variable argument is returned from the correct stack location.9 10 11declare void @llvm.va_start(ptr) nounwind12declare void @llvm.va_end(ptr) nounwind13 14; return int15define i32 @va1(i32 %a, ...) nounwind {16entry:17 %a.addr = alloca i32, align 418 %ap = alloca ptr, align 419 %b = alloca i32, align 420 store i32 %a, ptr %a.addr, align 421 call void @llvm.va_start(ptr %ap)22 %0 = va_arg ptr %ap, i3223 store i32 %0, ptr %b, align 424 call void @llvm.va_end(ptr %ap)25 %tmp = load i32, ptr %b, align 426 ret i32 %tmp27 28; CHECK-LABEL: va1:29; CHECK: addiu $sp, $sp, -1630; CHECK: sw $7, 28($sp)31; CHECK: sw $6, 24($sp)32; CHECK: sw $5, 20($sp)33; CHECK: move $2, $534}35 36; check whether the variable double argument will be accessed from the 8-byte37; aligned location (i.e. whether the address is computed by adding 7 and38; clearing lower 3 bits)39define double @va2(i32 %a, ...) nounwind {40entry:41 %a.addr = alloca i32, align 442 %ap = alloca ptr, align 443 %b = alloca double, align 844 store i32 %a, ptr %a.addr, align 445 call void @llvm.va_start(ptr %ap)46 %0 = va_arg ptr %ap, double47 store double %0, ptr %b, align 848 call void @llvm.va_end(ptr %ap)49 %tmp = load double, ptr %b, align 850 ret double %tmp51 52; CHECK-LABEL: va2:53; CHECK: addiu $sp, $sp, -1654; CHECK: sw $7, 28($sp)55; CHECK: sw $6, 24($sp)56; CHECK: sw $5, 20($sp)57; CHECK: addiu $[[R0:[0-9]+]], $sp, 2058; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 759; CHECK: addiu $[[R2:[0-9]+]], $zero, -860; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]61; CHECK: ldc1 $f0, 0($[[R3]])62}63 64; int65define i32 @va3(double %a, ...) nounwind {66entry:67 %a.addr = alloca double, align 868 %ap = alloca ptr, align 469 %b = alloca i32, align 470 store double %a, ptr %a.addr, align 871 call void @llvm.va_start(ptr %ap)72 %0 = va_arg ptr %ap, i3273 store i32 %0, ptr %b, align 474 call void @llvm.va_end(ptr %ap)75 %tmp = load i32, ptr %b, align 476 ret i32 %tmp77 78; CHECK-LABEL: va3:79; CHECK: addiu $sp, $sp, -1680; CHECK: sw $7, 28($sp)81; CHECK: sw $6, 24($sp)82; CHECK: move $2, $683}84 85; double86define double @va4(double %a, ...) nounwind {87entry:88 %a.addr = alloca double, align 889 %ap = alloca ptr, align 490 %b = alloca double, align 891 store double %a, ptr %a.addr, align 892 call void @llvm.va_start(ptr %ap)93 %0 = va_arg ptr %ap, double94 store double %0, ptr %b, align 895 call void @llvm.va_end(ptr %ap)96 %tmp = load double, ptr %b, align 897 ret double %tmp98 99; CHECK-LABEL: va4:100; CHECK: addiu $sp, $sp, -24101; CHECK: sw $7, 36($sp)102; CHECK: sw $6, 32($sp)103; CHECK: addiu ${{[0-9]+}}, $sp, 32104; CHECK: ldc1 $f0, 32($sp)105}106 107; int108define i32 @va5(i32 %a, i32 %b, i32 %c, ...) nounwind {109entry:110 %a.addr = alloca i32, align 4111 %b.addr = alloca i32, align 4112 %c.addr = alloca i32, align 4113 %ap = alloca ptr, align 4114 %d = alloca i32, align 4115 store i32 %a, ptr %a.addr, align 4116 store i32 %b, ptr %b.addr, align 4117 store i32 %c, ptr %c.addr, align 4118 call void @llvm.va_start(ptr %ap)119 %0 = va_arg ptr %ap, i32120 store i32 %0, ptr %d, align 4121 call void @llvm.va_end(ptr %ap)122 %tmp = load i32, ptr %d, align 4123 ret i32 %tmp124 125; CHECK-LABEL: va5:126; CHECK: addiu $sp, $sp, -24127; CHECK: sw $7, 36($sp)128; CHECK: move $2, $7129}130 131; double132define double @va6(i32 %a, i32 %b, i32 %c, ...) nounwind {133entry:134 %a.addr = alloca i32, align 4135 %b.addr = alloca i32, align 4136 %c.addr = alloca i32, align 4137 %ap = alloca ptr, align 4138 %d = alloca double, align 8139 store i32 %a, ptr %a.addr, align 4140 store i32 %b, ptr %b.addr, align 4141 store i32 %c, ptr %c.addr, align 4142 call void @llvm.va_start(ptr %ap)143 %0 = va_arg ptr %ap, double144 store double %0, ptr %d, align 8145 call void @llvm.va_end(ptr %ap)146 %tmp = load double, ptr %d, align 8147 ret double %tmp148 149; CHECK-LABEL: va6:150; CHECK: addiu $sp, $sp, -24151; CHECK: sw $7, 36($sp)152; CHECK: addiu $[[R0:[0-9]+]], $sp, 36153; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7154; CHECK: addiu $[[R2:[0-9]+]], $zero, -8155; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]156; CHECK: ldc1 $f0, 0($[[R3]])157}158 159; int160define i32 @va7(i32 %a, double %b, ...) nounwind {161entry:162 %a.addr = alloca i32, align 4163 %b.addr = alloca double, align 8164 %ap = alloca ptr, align 4165 %c = alloca i32, align 4166 store i32 %a, ptr %a.addr, align 4167 store double %b, ptr %b.addr, align 8168 call void @llvm.va_start(ptr %ap)169 %0 = va_arg ptr %ap, i32170 store i32 %0, ptr %c, align 4171 call void @llvm.va_end(ptr %ap)172 %tmp = load i32, ptr %c, align 4173 ret i32 %tmp174 175; CHECK-LABEL: va7:176; CHECK: addiu $sp, $sp, -24177; CHECK: lw $2, 40($sp)178}179 180; double181define double @va8(i32 %a, double %b, ...) nounwind {182entry:183 %a.addr = alloca i32, align 4184 %b.addr = alloca double, align 8185 %ap = alloca ptr, align 4186 %c = alloca double, align 8187 store i32 %a, ptr %a.addr, align 4188 store double %b, ptr %b.addr, align 8189 call void @llvm.va_start(ptr %ap)190 %0 = va_arg ptr %ap, double191 store double %0, ptr %c, align 8192 call void @llvm.va_end(ptr %ap)193 %tmp = load double, ptr %c, align 8194 ret double %tmp195 196; CHECK-LABEL: va8:197; CHECK: addiu $sp, $sp, -32198; CHECK: addiu ${{[0-9]+}}, $sp, 48199; CHECK: ldc1 $f0, 48($sp)200}201 202; int203define i32 @va9(double %a, double %b, i32 %c, ...) nounwind {204entry:205 %a.addr = alloca double, align 8206 %b.addr = alloca double, align 8207 %c.addr = alloca i32, align 4208 %ap = alloca ptr, align 4209 %d = alloca i32, align 4210 store double %a, ptr %a.addr, align 8211 store double %b, ptr %b.addr, align 8212 store i32 %c, ptr %c.addr, align 4213 call void @llvm.va_start(ptr %ap)214 %0 = va_arg ptr %ap, i32215 store i32 %0, ptr %d, align 4216 call void @llvm.va_end(ptr %ap)217 %tmp = load i32, ptr %d, align 4218 ret i32 %tmp219 220; CHECK-LABEL: va9:221; CHECK: addiu $sp, $sp, -24222; CHECK: lw $2, 44($sp)223}224 225; double226define double @va10(double %a, double %b, i32 %c, ...) nounwind {227entry:228 %a.addr = alloca double, align 8229 %b.addr = alloca double, align 8230 %c.addr = alloca i32, align 4231 %ap = alloca ptr, align 4232 %d = alloca double, align 8233 store double %a, ptr %a.addr, align 8234 store double %b, ptr %b.addr, align 8235 store i32 %c, ptr %c.addr, align 4236 call void @llvm.va_start(ptr %ap)237 %0 = va_arg ptr %ap, double238 store double %0, ptr %d, align 8239 call void @llvm.va_end(ptr %ap)240 %tmp = load double, ptr %d, align 8241 ret double %tmp242 243; CHECK-LABEL: va10:244; CHECK: addiu $sp, $sp, -32245; CHECK: addiu $[[R0:[0-9]+]], $sp, 52246; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7247; CHECK: addiu $[[R2:[0-9]+]], $zero, -8248; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]249; CHECK: ldc1 $f0, 0($[[R3]])250}251