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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mipsel-unknown-linux-musl-gnu < %s | FileCheck %s3 4; Check that in microMIPSr5 with a 64 bit fpu configuration, the following5; code can be compiled. This previously failed due to missing load/store6; patterns and instructions to handle the 64 bit FPU case for microMIPS.7 8%union.anon = type { { double, double } }9 10define dso_local void @foo() #0 {11; CHECK-LABEL: foo:12; CHECK: # %bb.0: # %entry13; CHECK-NEXT: addiusp -2414; CHECK-NEXT: mtc1 $zero, $f015; CHECK-NEXT: mthc1 $zero, $f016; CHECK-NEXT: sdc1 $f0, 0($sp)17; CHECK-NEXT: sdc1 $f0, 8($sp)18; CHECK-NEXT: ldc1 $f0, 0($sp)19; CHECK-NEXT: sdc1 $f0, 16($sp)20; CHECK-NEXT: addiusp 2421; CHECK-NEXT: jrc $ra22entry:23 %bleh = alloca double, align 824 %.compoundliteral = alloca %union.anon, align 825 %arrayinit.begin = getelementptr inbounds [2 x double], ptr %.compoundliteral, i32 0, i32 026 store double 0.000000e+00, ptr %arrayinit.begin, align 827 %arrayinit.element = getelementptr inbounds double, ptr %arrayinit.begin, i32 128 store double 0.000000e+00, ptr %arrayinit.element, align 829 %.compoundliteral.realp = getelementptr inbounds { double, double }, ptr %.compoundliteral, i32 0, i32 030 %.compoundliteral.real = load double, ptr %.compoundliteral.realp, align 831 store double %.compoundliteral.real, ptr %bleh, align 832 ret void33}34attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="mips32r5" "target-features"="+dspr2,+fp64,+mips32r5,-noabicalls,+micromips" }35