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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s3 4; Test that the delay slot filler correctly handles indirect branches for5; microMIPS in regard to incorrectly using 16bit instructions in delay slots of6; 32bit instructions.7 8define i32 @test(i32 signext %x, i32 signext %c) {9; CHECK-LABEL: test:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: lui $2, %hi(_gp_disp)12; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)13; CHECK-NEXT: addiur2 $5, $5, -114; CHECK-NEXT: sltiu $1, $5, 415; CHECK-NEXT: beqz $1, $BB0_616; CHECK-NEXT: addu $3, $2, $2517; CHECK-NEXT: # %bb.1: # %entry18; CHECK-NEXT: li16 $2, 019; CHECK-NEXT: sll16 $5, $5, 220; CHECK-NEXT: lw $6, %got($JTI0_0)($3)21; CHECK-NEXT: addu16 $5, $5, $622; CHECK-NEXT: lw $5, %lo($JTI0_0)($5)23; CHECK-NEXT: addu16 $3, $3, $524; CHECK-NEXT: jr $325; CHECK-NEXT: nop26; CHECK-NEXT: $BB0_2: # %sw.bb227; CHECK-NEXT: addiur2 $2, $4, 128; CHECK-NEXT: jrc $ra29; CHECK-NEXT: $BB0_3: # %sw.bb330; CHECK-NEXT: addius5 $4, 231; CHECK-NEXT: move $2, $432; CHECK-NEXT: jrc $ra33; CHECK-NEXT: $BB0_4: # %sw.bb534; CHECK-NEXT: addius5 $4, 335; CHECK-NEXT: move $2, $436; CHECK-NEXT: $BB0_5: # %for.cond.cleanup37; CHECK-NEXT: jrc $ra38; CHECK-NEXT: $BB0_6:39; CHECK-NEXT: move $2, $440; CHECK-NEXT: jrc $ra41entry:42 switch i32 %c, label %sw.epilog [43 i32 4, label %sw.bb544 i32 1, label %for.cond.cleanup45 i32 2, label %sw.bb246 i32 3, label %sw.bb347 ]48 49sw.bb2:50 %add = add nsw i32 %x, 151 br label %sw.epilog52 53sw.bb3:54 %add4 = add nsw i32 %x, 255 br label %sw.epilog56 57sw.bb5:58 %add6 = add nsw i32 %x, 359 br label %sw.epilog60 61sw.epilog:62 %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]63 br label %for.cond.cleanup64 65for.cond.cleanup:66 %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]67 ret i32 %a.02868}69