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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=mipsel < %s | FileCheck %s3; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR64 5@g1 = external global i326 7define i32 @seteq0(i32 %a) {8; CHECK-LABEL: seteq0:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: jr $ra11; CHECK-NEXT: sltiu $2, $4, 112;13; MMR6-LABEL: seteq0:14; MMR6: # %bb.0: # %entry15; MMR6-NEXT: sltiu $2, $4, 1 # <MCInst #[[#MCINST1:]] SLTiu_MM16; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>17; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>18; MMR6-NEXT: # <MCOperand Imm:1>>19; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2:]] JRC16_MM20; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>21entry:22 %cmp = icmp eq i32 %a, 023 %conv = zext i1 %cmp to i3224 ret i32 %conv25}26 27define i32 @setne0(i32 %a) {28; CHECK-LABEL: setne0:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: jr $ra31; CHECK-NEXT: sltu $2, $zero, $432;33; MMR6-LABEL: setne0:34; MMR6: # %bb.0: # %entry35; MMR6-NEXT: sltu $2, $zero, $4 # <MCInst #[[#MCINST3:]] SLTu_MM36; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>37; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>38; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>39; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM40; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>41entry:42 %cmp = icmp ne i32 %a, 043 %conv = zext i1 %cmp to i3244 ret i32 %conv45}46 47define void @slti_beq0(i32 %a) {48; CHECK-LABEL: slti_beq0:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: slti $1, $4, -3276851; CHECK-NEXT: beqz $1, $BB2_252; CHECK-NEXT: nop53; CHECK-NEXT: # %bb.1: # %if.then54; CHECK-NEXT: lui $1, %hi(g1)55; CHECK-NEXT: sw $4, %lo(g1)($1)56; CHECK-NEXT: $BB2_2: # %if.end57; CHECK-NEXT: jr $ra58; CHECK-NEXT: nop59;60; MMR6-LABEL: slti_beq0:61; MMR6: # %bb.0: # %entry62; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4:]] LUi63; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>64; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>65; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5:]] ADDiu66; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>67; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>68; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>69; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6:]] ADDu70; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>71; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>72; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5:]]>>73; MMR6-NEXT: slti $1, $4, -32768 # <MCInst #[[#MCINST7:]] SLTi_MM74; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>75; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>76; MMR6-NEXT: # <MCOperand Imm:-32768>>77; MMR6-NEXT: beqzc $1, $BB2_2 # <MCInst #[[#MCINST8:]] BEQZC_MMR678; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>79; MMR6-NEXT: # <MCOperand Expr:$BB2_2>>80; MMR6-NEXT: # %bb.1: # %if.then81; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9:]] LW_MM82; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>83; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>84; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>85; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10:]] SW16_MM86; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>87; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>88; MMR6-NEXT: # <MCOperand Imm:0>>89; MMR6-NEXT: $BB2_2: # %if.end90; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM91; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>92entry:93 %cmp = icmp slt i32 %a, -3276894 br i1 %cmp, label %if.then, label %if.end95 96if.then:97 store i32 %a, ptr @g1, align 498 br label %if.end99 100if.end:101 ret void102}103 104define void @slti_beq1(i32 %a) {105; CHECK-LABEL: slti_beq1:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: lui $1, 65535108; CHECK-NEXT: ori $1, $1, 32766109; CHECK-NEXT: slt $1, $1, $4110; CHECK-NEXT: bnez $1, $BB3_2111; CHECK-NEXT: nop112; CHECK-NEXT: # %bb.1: # %if.then113; CHECK-NEXT: lui $1, %hi(g1)114; CHECK-NEXT: sw $4, %lo(g1)($1)115; CHECK-NEXT: $BB3_2: # %if.end116; CHECK-NEXT: jr $ra117; CHECK-NEXT: nop118;119; MMR6-LABEL: slti_beq1:120; MMR6: # %bb.0: # %entry121; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi122; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>123; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>124; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu125; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>126; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>127; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>128; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu129; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>130; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>131; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>132; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11:]] LUi_MM133; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>134; MMR6-NEXT: # <MCOperand Imm:65535>>135; MMR6-NEXT: ori $1, $1, 32766 # <MCInst #[[#MCINST12:]] ORi_MM136; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>137; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>138; MMR6-NEXT: # <MCOperand Imm:32766>>139; MMR6-NEXT: slt $1, $1, $4 # <MCInst #[[#MCINST13:]] SLT_MM140; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>141; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>142; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>143; MMR6-NEXT: bnezc $1, $BB3_2 # <MCInst #[[#MCINST14:]] BNEZC_MMR6144; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>145; MMR6-NEXT: # <MCOperand Expr:$BB3_2>>146; MMR6-NEXT: # %bb.1: # %if.then147; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM148; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>149; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>150; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>151; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM152; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>153; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>154; MMR6-NEXT: # <MCOperand Imm:0>>155; MMR6-NEXT: $BB3_2: # %if.end156; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM157; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>158entry:159 %cmp = icmp slt i32 %a, -32769160 br i1 %cmp, label %if.then, label %if.end161 162if.then:163 store i32 %a, ptr @g1, align 4164 br label %if.end165 166if.end:167 ret void168}169 170define void @slti_beq2(i32 %a) {171; CHECK-LABEL: slti_beq2:172; CHECK: # %bb.0: # %entry173; CHECK-NEXT: slti $1, $4, 32767174; CHECK-NEXT: beqz $1, $BB4_2175; CHECK-NEXT: nop176; CHECK-NEXT: # %bb.1: # %if.then177; CHECK-NEXT: lui $1, %hi(g1)178; CHECK-NEXT: sw $4, %lo(g1)($1)179; CHECK-NEXT: $BB4_2: # %if.end180; CHECK-NEXT: jr $ra181; CHECK-NEXT: nop182;183; MMR6-LABEL: slti_beq2:184; MMR6: # %bb.0: # %entry185; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi186; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>187; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>188; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu189; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>190; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>191; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>192; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu193; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>194; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>195; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>196; MMR6-NEXT: slti $1, $4, 32767 # <MCInst #[[#MCINST7]] SLTi_MM197; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>198; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>199; MMR6-NEXT: # <MCOperand Imm:32767>>200; MMR6-NEXT: beqzc $1, $BB4_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6201; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>202; MMR6-NEXT: # <MCOperand Expr:$BB4_2>>203; MMR6-NEXT: # %bb.1: # %if.then204; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM205; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>206; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>207; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>208; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM209; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>210; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>211; MMR6-NEXT: # <MCOperand Imm:0>>212; MMR6-NEXT: $BB4_2: # %if.end213; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM214; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>215entry:216 %cmp = icmp slt i32 %a, 32767217 br i1 %cmp, label %if.then, label %if.end218 219if.then:220 store i32 %a, ptr @g1, align 4221 br label %if.end222 223if.end:224 ret void225}226 227define void @slti_beq3(i32 %a) {228; CHECK-LABEL: slti_beq3:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: addiu $1, $zero, 32767231; CHECK-NEXT: slt $1, $1, $4232; CHECK-NEXT: bnez $1, $BB5_2233; CHECK-NEXT: nop234; CHECK-NEXT: # %bb.1: # %if.then235; CHECK-NEXT: lui $1, %hi(g1)236; CHECK-NEXT: sw $4, %lo(g1)($1)237; CHECK-NEXT: $BB5_2: # %if.end238; CHECK-NEXT: jr $ra239; CHECK-NEXT: nop240;241; MMR6-LABEL: slti_beq3:242; MMR6: # %bb.0: # %entry243; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi244; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>245; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>246; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu247; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>248; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>249; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>250; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu251; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>252; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>253; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>254; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15:]] ADDiu_MM255; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>256; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4]]>257; MMR6-NEXT: # <MCOperand Imm:32767>>258; MMR6-NEXT: slt $1, $1, $4 # <MCInst #[[#MCINST13]] SLT_MM259; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>260; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>261; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>262; MMR6-NEXT: bnezc $1, $BB5_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6263; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>264; MMR6-NEXT: # <MCOperand Expr:$BB5_2>>265; MMR6-NEXT: # %bb.1: # %if.then266; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM267; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>268; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>269; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>270; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM271; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>272; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>273; MMR6-NEXT: # <MCOperand Imm:0>>274; MMR6-NEXT: $BB5_2: # %if.end275; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM276; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>277entry:278 %cmp = icmp slt i32 %a, 32768279 br i1 %cmp, label %if.then, label %if.end280 281if.then:282 store i32 %a, ptr @g1, align 4283 br label %if.end284 285if.end:286 ret void287}288 289define void @sltiu_beq0(i32 %a) {290; CHECK-LABEL: sltiu_beq0:291; CHECK: # %bb.0: # %entry292; CHECK-NEXT: sltiu $1, $4, 32767293; CHECK-NEXT: beqz $1, $BB6_2294; CHECK-NEXT: nop295; CHECK-NEXT: # %bb.1: # %if.then296; CHECK-NEXT: lui $1, %hi(g1)297; CHECK-NEXT: sw $4, %lo(g1)($1)298; CHECK-NEXT: $BB6_2: # %if.end299; CHECK-NEXT: jr $ra300; CHECK-NEXT: nop301;302; MMR6-LABEL: sltiu_beq0:303; MMR6: # %bb.0: # %entry304; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi305; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>306; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>307; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu308; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>309; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>310; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>311; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu312; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>313; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>314; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>315; MMR6-NEXT: sltiu $1, $4, 32767 # <MCInst #[[#MCINST1]] SLTiu_MM316; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>317; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>318; MMR6-NEXT: # <MCOperand Imm:32767>>319; MMR6-NEXT: beqzc $1, $BB6_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6320; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>321; MMR6-NEXT: # <MCOperand Expr:$BB6_2>>322; MMR6-NEXT: # %bb.1: # %if.then323; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM324; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>325; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>326; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>327; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM328; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>329; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>330; MMR6-NEXT: # <MCOperand Imm:0>>331; MMR6-NEXT: $BB6_2: # %if.end332; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM333; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>334entry:335 %cmp = icmp ult i32 %a, 32767336 br i1 %cmp, label %if.then, label %if.end337 338if.then:339 store i32 %a, ptr @g1, align 4340 br label %if.end341 342if.end:343 ret void344}345 346define void @sltiu_beq1(i32 %a) {347; CHECK-LABEL: sltiu_beq1:348; CHECK: # %bb.0: # %entry349; CHECK-NEXT: addiu $1, $zero, 32767350; CHECK-NEXT: sltu $1, $1, $4351; CHECK-NEXT: bnez $1, $BB7_2352; CHECK-NEXT: nop353; CHECK-NEXT: # %bb.1: # %if.then354; CHECK-NEXT: lui $1, %hi(g1)355; CHECK-NEXT: sw $4, %lo(g1)($1)356; CHECK-NEXT: $BB7_2: # %if.end357; CHECK-NEXT: jr $ra358; CHECK-NEXT: nop359;360; MMR6-LABEL: sltiu_beq1:361; MMR6: # %bb.0: # %entry362; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi363; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>364; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>365; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu366; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>367; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>368; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>369; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu370; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>371; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>372; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>373; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15]] ADDiu_MM374; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>375; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4]]>376; MMR6-NEXT: # <MCOperand Imm:32767>>377; MMR6-NEXT: sltu $1, $1, $4 # <MCInst #[[#MCINST3]] SLTu_MM378; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>379; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>380; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>381; MMR6-NEXT: bnezc $1, $BB7_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6382; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>383; MMR6-NEXT: # <MCOperand Expr:$BB7_2>>384; MMR6-NEXT: # %bb.1: # %if.then385; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM386; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>387; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>388; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>389; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM390; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>391; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>392; MMR6-NEXT: # <MCOperand Imm:0>>393; MMR6-NEXT: $BB7_2: # %if.end394; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM395; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>396entry:397 %cmp = icmp ult i32 %a, 32768398 br i1 %cmp, label %if.then, label %if.end399 400if.then:401 store i32 %a, ptr @g1, align 4402 br label %if.end403 404if.end:405 ret void406}407 408define void @sltiu_beq2(i32 %a) {409; CHECK-LABEL: sltiu_beq2:410; CHECK: # %bb.0: # %entry411; CHECK-NEXT: sltiu $1, $4, -32768412; CHECK-NEXT: beqz $1, $BB8_2413; CHECK-NEXT: nop414; CHECK-NEXT: # %bb.1: # %if.then415; CHECK-NEXT: lui $1, %hi(g1)416; CHECK-NEXT: sw $4, %lo(g1)($1)417; CHECK-NEXT: $BB8_2: # %if.end418; CHECK-NEXT: jr $ra419; CHECK-NEXT: nop420;421; MMR6-LABEL: sltiu_beq2:422; MMR6: # %bb.0: # %entry423; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi424; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>425; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>426; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu427; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>428; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>429; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>430; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu431; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>432; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>433; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>434; MMR6-NEXT: sltiu $1, $4, -32768 # <MCInst #[[#MCINST1]] SLTiu_MM435; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>436; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>437; MMR6-NEXT: # <MCOperand Imm:-32768>>438; MMR6-NEXT: beqzc $1, $BB8_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6439; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>440; MMR6-NEXT: # <MCOperand Expr:$BB8_2>>441; MMR6-NEXT: # %bb.1: # %if.then442; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM443; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>444; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>445; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>446; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM447; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>448; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>449; MMR6-NEXT: # <MCOperand Imm:0>>450; MMR6-NEXT: $BB8_2: # %if.end451; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM452; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>453entry:454 %cmp = icmp ult i32 %a, -32768455 br i1 %cmp, label %if.then, label %if.end456 457if.then:458 store i32 %a, ptr @g1, align 4459 br label %if.end460 461if.end:462 ret void463}464 465define void @sltiu_beq3(i32 %a) {466; CHECK-LABEL: sltiu_beq3:467; CHECK: # %bb.0: # %entry468; CHECK-NEXT: lui $1, 65535469; CHECK-NEXT: ori $1, $1, 32766470; CHECK-NEXT: sltu $1, $1, $4471; CHECK-NEXT: bnez $1, $BB9_2472; CHECK-NEXT: nop473; CHECK-NEXT: # %bb.1: # %if.then474; CHECK-NEXT: lui $1, %hi(g1)475; CHECK-NEXT: sw $4, %lo(g1)($1)476; CHECK-NEXT: $BB9_2: # %if.end477; CHECK-NEXT: jr $ra478; CHECK-NEXT: nop479;480; MMR6-LABEL: sltiu_beq3:481; MMR6: # %bb.0: # %entry482; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi483; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>484; MMR6-NEXT: # <MCOperand Expr:specifier(4024,_gp_disp)>>485; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu486; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>487; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>488; MMR6-NEXT: # <MCOperand Expr:specifier(4027,_gp_disp)>>489; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu490; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>491; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>492; MMR6-NEXT: # <MCOperand Reg:[[#MCREG5]]>>493; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11]] LUi_MM494; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>495; MMR6-NEXT: # <MCOperand Imm:65535>>496; MMR6-NEXT: ori $1, $1, 32766 # <MCInst #[[#MCINST12]] ORi_MM497; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>498; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>499; MMR6-NEXT: # <MCOperand Imm:32766>>500; MMR6-NEXT: sltu $1, $1, $4 # <MCInst #[[#MCINST3]] SLTu_MM501; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>502; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>503; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>504; MMR6-NEXT: bnezc $1, $BB9_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6505; MMR6-NEXT: # <MCOperand Reg:[[#MCREG6]]>506; MMR6-NEXT: # <MCOperand Expr:$BB9_2>>507; MMR6-NEXT: # %bb.1: # %if.then508; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM509; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>510; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>511; MMR6-NEXT: # <MCOperand Expr:specifier(4015,g1)>>512; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM513; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>514; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>515; MMR6-NEXT: # <MCOperand Imm:0>>516; MMR6-NEXT: $BB9_2: # %if.end517; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM518; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>519entry:520 %cmp = icmp ult i32 %a, -32769521 br i1 %cmp, label %if.then, label %if.end522 523if.then:524 store i32 %a, ptr @g1, align 4525 br label %if.end526 527if.end:528 ret void529}530